| blob | f6c0ec083096ec393cc3cc4dbce04f03ea64cb9c |
1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -run-pass=aarch64-mi-peephole-opt -o - -mtriple=aarch64-unknown-linux -verify-machineinstrs %s | FileCheck %s
4 # Main intention is to verify machine instructions have valid register classes.
5 # Use of UBFM[W|X]ri is used as an arbitrary instruction that requires GPR[32|64]RegClass.
6 # If the ADD/SUB optimization generates invalid register classes, this test will fail.
7 ---
8 name: addi
9 body: |
10 bb.0.entry:
11 liveins: $w0
12 ; CHECK-LABEL: name: addi
13 ; CHECK: liveins: $w0
14 ; CHECK-NEXT: {{ $}}
15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
16 ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 273, 12
17 ; CHECK-NEXT: [[ADDWri1:%[0-9]+]]:gpr32common = ADDWri [[ADDWri]], 3549, 0
18 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[ADDWri1]], 28, 31
19 ; CHECK-NEXT: $w0 = COPY [[UBFMWri]]
20 ; CHECK-NEXT: RET_ReallyLR implicit $w0
21 %0:gpr32 = COPY $w0
22 %1:gpr32 = MOVi32imm 1121757
23 %2:gpr32 = ADDWrr %0, %1
24 %3:gpr32 = UBFMWri %2, 28, 31
25 $w0 = COPY %3
26 RET_ReallyLR implicit $w0
27 ...
28 ---
29 name: addl
30 body: |
31 bb.0.entry:
32 liveins: $x0
33 ; CHECK-LABEL: name: addl
34 ; CHECK: liveins: $x0
35 ; CHECK-NEXT: {{ $}}
36 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
37 ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 273, 12
38 ; CHECK-NEXT: [[ADDXri1:%[0-9]+]]:gpr64common = ADDXri [[ADDXri]], 3549, 0
39 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[ADDXri1]].sub_32
40 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 28, 31
41 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[UBFMWri]], %subreg.sub_32
42 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
43 ; CHECK-NEXT: RET_ReallyLR implicit $x0
44 %0:gpr64 = COPY $x0
45 %1:gpr32 = MOVi32imm 1121757
46 %2:gpr64 = SUBREG_TO_REG 0, %1, %subreg.sub_32
47 %3:gpr64 = ADDXrr %0, killed %2
48 %4:gpr64 = UBFMXri %3, 28, 31
49 $x0 = COPY %4
50 RET_ReallyLR implicit $x0
51 ...
52 ---
53 name: addl_negate
54 body: |
55 bb.0.entry:
56 liveins: $x0
57 ; CHECK-LABEL: name: addl_negate
58 ; CHECK: liveins: $x0
59 ; CHECK-NEXT: {{ $}}
60 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
61 ; CHECK-NEXT: [[SUBXri:%[0-9]+]]:gpr64sp = SUBXri [[COPY]], 273, 12
62 ; CHECK-NEXT: [[SUBXri1:%[0-9]+]]:gpr64common = SUBXri [[SUBXri]], 3549, 0
63 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY [[SUBXri1]].sub_32
64 ; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 28, 31
65 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[UBFMWri]], %subreg.sub_32
66 ; CHECK-NEXT: $x0 = COPY [[SUBREG_TO_REG]]
67 ; CHECK-NEXT: RET_ReallyLR implicit $x0
68 %0:gpr64 = COPY $x0
69 %1:gpr64 = MOVi64imm -1121757
70 %2:gpr64 = ADDXrr %0, killed %1
71 %3:gpr64 = UBFMXri %2, 28, 31
72 $x0 = COPY %3
73 RET_ReallyLR implicit $x0
74 ...
75 ---
76 name: add_xzr
77 body: |
78 bb.0.entry:
79 liveins: $x0
80 ; CHECK-LABEL: name: add_xzr
81 ; CHECK: liveins: $x0
82 ; CHECK-NEXT: {{ $}}
83 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
84 ; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -2105098
85 ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64common = ADDXrr $xzr, [[MOVi64imm]]
86 ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY]], [[ADDXrr]]
87 ; CHECK-NEXT: $x0 = COPY [[MADDXrrr]]
88 ; CHECK-NEXT: RET_ReallyLR implicit $x0
89 %0:gpr64 = COPY $x0
90 %2:gpr64 = MOVi64imm -2105098
91 %4:gpr64common = ADDXrr $xzr, %2
92 %3:gpr64 = MADDXrrr %0, %0, %4
93 $x0 = COPY %3
94 RET_ReallyLR implicit $x0
95 ...
96 ---
97 name: sub_xzr
98 body: |
99 bb.0.entry:
100 liveins: $x0
101 ; CHECK-LABEL: name: sub_xzr
102 ; CHECK: liveins: $x0
103 ; CHECK-NEXT: {{ $}}
104 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
105 ; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -2105098
106 ; CHECK-NEXT: [[SUBXrr:%[0-9]+]]:gpr64common = SUBXrr $xzr, [[MOVi64imm]]
107 ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY]], [[SUBXrr]]
108 ; CHECK-NEXT: $x0 = COPY [[MADDXrrr]]
109 ; CHECK-NEXT: RET_ReallyLR implicit $x0
110 %0:gpr64 = COPY $x0
111 %2:gpr64 = MOVi64imm -2105098
112 %4:gpr64common = SUBXrr $xzr, %2
113 %3:gpr64 = MADDXrrr %0, %0, %4
114 $x0 = COPY %3
115 RET_ReallyLR implicit $x0
116 ...
117 ---
118 name: adds_xzr
119 body: |
120 bb.0.entry:
121 liveins: $x0
122 ; CHECK-LABEL: name: adds_xzr
123 ; CHECK: liveins: $x0
124 ; CHECK-NEXT: {{ $}}
125 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
126 ; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -2105098
127 ; CHECK-NEXT: [[ADDSXrr:%[0-9]+]]:gpr64common = ADDSXrr $xzr, [[MOVi64imm]], implicit-def $nzcv
128 ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY]], [[ADDSXrr]]
129 ; CHECK-NEXT: $x0 = COPY [[MADDXrrr]]
130 ; CHECK-NEXT: RET_ReallyLR implicit $x0
131 %0:gpr64 = COPY $x0
132 %2:gpr64 = MOVi64imm -2105098
133 %4:gpr64common = ADDSXrr $xzr, %2, implicit-def $nzcv
134 %3:gpr64 = MADDXrrr %0, %0, %4
135 $x0 = COPY %3
136 RET_ReallyLR implicit $x0
137 ...
138 ---
139 name: subs_xzr
140 body: |
141 bb.0.entry:
142 liveins: $x0
143 ; CHECK-LABEL: name: subs_xzr
144 ; CHECK: liveins: $x0
145 ; CHECK-NEXT: {{ $}}
146 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
147 ; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -2105098
148 ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64common = SUBSXrr $xzr, [[MOVi64imm]], implicit-def $nzcv
149 ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY]], [[SUBSXrr]]
150 ; CHECK-NEXT: $x0 = COPY [[MADDXrrr]]
151 ; CHECK-NEXT: RET_ReallyLR implicit $x0
152 %0:gpr64 = COPY $x0
153 %2:gpr64 = MOVi64imm -2105098
154 %4:gpr64common = SUBSXrr $xzr, %2, implicit-def $nzcv
155 %3:gpr64 = MADDXrrr %0, %0, %4
156 $x0 = COPY %3
157 RET_ReallyLR implicit $x0