1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3 ; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
5 define <4 x half> @interleave2_v4f16(<2 x half> %vec0, <2 x half> %vec1) {
6 ; CHECK-LABEL: interleave2_v4f16:
8 ; CHECK-NEXT: zip1 v0.4h, v0.4h, v1.4h
10 %retval = call <4 x half> @llvm.vector.interleave2.v4f16(<2 x half> %vec0, <2 x half> %vec1)
11 ret <4 x half> %retval
14 define <8 x half> @interleave2_v8f16(<4 x half> %vec0, <4 x half> %vec1) {
15 ; CHECK-SD-LABEL: interleave2_v8f16:
17 ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
18 ; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
19 ; CHECK-SD-NEXT: adrp x8, .LCPI1_0
20 ; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
21 ; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]
22 ; CHECK-SD-NEXT: tbl v0.16b, { v0.16b }, v1.16b
25 ; CHECK-GI-LABEL: interleave2_v8f16:
27 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
28 ; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
29 ; CHECK-GI-NEXT: zip1 v0.8h, v0.8h, v1.8h
31 %retval = call <8 x half> @llvm.vector.interleave2.v8f16(<4 x half> %vec0, <4 x half> %vec1)
32 ret <8 x half> %retval
35 define <16 x half> @interleave2_v16f16(<8 x half> %vec0, <8 x half> %vec1) {
36 ; CHECK-LABEL: interleave2_v16f16:
38 ; CHECK-NEXT: zip1 v2.8h, v0.8h, v1.8h
39 ; CHECK-NEXT: zip2 v1.8h, v0.8h, v1.8h
40 ; CHECK-NEXT: mov v0.16b, v2.16b
42 %retval = call <16 x half> @llvm.vector.interleave2.v16f16(<8 x half> %vec0, <8 x half> %vec1)
43 ret <16 x half> %retval
46 define <4 x float> @interleave2_v4f32(<2 x float> %vec0, <2 x float> %vec1) {
47 ; CHECK-SD-LABEL: interleave2_v4f32:
49 ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
50 ; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
51 ; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
52 ; CHECK-SD-NEXT: rev64 v1.4s, v0.4s
53 ; CHECK-SD-NEXT: uzp1 v0.4s, v0.4s, v1.4s
56 ; CHECK-GI-LABEL: interleave2_v4f32:
58 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
59 ; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1
60 ; CHECK-GI-NEXT: zip1 v0.4s, v0.4s, v1.4s
62 %retval = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %vec0, <2 x float> %vec1)
63 ret <4 x float> %retval
66 define <8 x float> @interleave2_v8f32(<4 x float> %vec0, <4 x float> %vec1) {
67 ; CHECK-LABEL: interleave2_v8f32:
69 ; CHECK-NEXT: zip1 v2.4s, v0.4s, v1.4s
70 ; CHECK-NEXT: zip2 v1.4s, v0.4s, v1.4s
71 ; CHECK-NEXT: mov v0.16b, v2.16b
73 %retval = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %vec0, <4 x float> %vec1)
74 ret <8 x float> %retval
77 define <4 x double> @interleave2_v4f64(<2 x double> %vec0, <2 x double> %vec1) {
78 ; CHECK-LABEL: interleave2_v4f64:
80 ; CHECK-NEXT: zip1 v2.2d, v0.2d, v1.2d
81 ; CHECK-NEXT: zip2 v1.2d, v0.2d, v1.2d
82 ; CHECK-NEXT: mov v0.16b, v2.16b
84 %retval = call <4 x double>@llvm.vector.interleave2.v4f64(<2 x double> %vec0, <2 x double> %vec1)
85 ret <4 x double> %retval
90 define <32 x i8> @interleave2_v32i8(<16 x i8> %vec0, <16 x i8> %vec1) {
91 ; CHECK-LABEL: interleave2_v32i8:
93 ; CHECK-NEXT: zip1 v2.16b, v0.16b, v1.16b
94 ; CHECK-NEXT: zip2 v1.16b, v0.16b, v1.16b
95 ; CHECK-NEXT: mov v0.16b, v2.16b
97 %retval = call <32 x i8> @llvm.vector.interleave2.v32i8(<16 x i8> %vec0, <16 x i8> %vec1)
101 define <16 x i16> @interleave2_v16i16(<8 x i16> %vec0, <8 x i16> %vec1) {
102 ; CHECK-LABEL: interleave2_v16i16:
104 ; CHECK-NEXT: zip1 v2.8h, v0.8h, v1.8h
105 ; CHECK-NEXT: zip2 v1.8h, v0.8h, v1.8h
106 ; CHECK-NEXT: mov v0.16b, v2.16b
108 %retval = call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %vec0, <8 x i16> %vec1)
109 ret <16 x i16> %retval
112 define <8 x i32> @interleave2_v8i32(<4 x i32> %vec0, <4 x i32> %vec1) {
113 ; CHECK-LABEL: interleave2_v8i32:
115 ; CHECK-NEXT: zip1 v2.4s, v0.4s, v1.4s
116 ; CHECK-NEXT: zip2 v1.4s, v0.4s, v1.4s
117 ; CHECK-NEXT: mov v0.16b, v2.16b
119 %retval = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %vec0, <4 x i32> %vec1)
120 ret <8 x i32> %retval
123 define <4 x i64> @interleave2_v4i64(<2 x i64> %vec0, <2 x i64> %vec1) {
124 ; CHECK-LABEL: interleave2_v4i64:
126 ; CHECK-NEXT: zip1 v2.2d, v0.2d, v1.2d
127 ; CHECK-NEXT: zip2 v1.2d, v0.2d, v1.2d
128 ; CHECK-NEXT: mov v0.16b, v2.16b
130 %retval = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %vec0, <2 x i64> %vec1)
131 ret <4 x i64> %retval
136 declare <4 x half> @llvm.vector.interleave2.v4f16(<2 x half>, <2 x half>)
137 declare <8 x half> @llvm.vector.interleave2.v8f16(<4 x half>, <4 x half>)
138 declare <16 x half> @llvm.vector.interleave2.v16f16(<8 x half>, <8 x half>)
139 declare <4 x float> @llvm.vector.interleave2.v4f32(<2 x float>, <2 x float>)
140 declare <8 x float> @llvm.vector.interleave2.v8f32(<4 x float>, <4 x float>)
141 declare <4 x double> @llvm.vector.interleave2.v4f64(<2 x double>, <2 x double>)
143 ; Integer declarations
144 declare <32 x i8> @llvm.vector.interleave2.v32i8(<16 x i8>, <16 x i8>)
145 declare <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16>, <8 x i16>)
146 declare <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32>, <4 x i32>)
147 declare <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64>, <2 x i64>)