| blob | 468a33ce5bfcf6f164ba20a422e13b7b049d4cf2 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
4 define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
5 ; CHECK-LABEL: fold_urem_vec_1:
6 ; CHECK: // %bb.0:
7 ; CHECK-NEXT: adrp x8, .LCPI0_0
8 ; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI0_0]
9 ; CHECK-NEXT: adrp x8, .LCPI0_1
10 ; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI0_1]
11 ; CHECK-NEXT: adrp x8, .LCPI0_2
12 ; CHECK-NEXT: ushl v1.4h, v0.4h, v1.4h
13 ; CHECK-NEXT: umull v1.4s, v1.4h, v2.4h
14 ; CHECK-NEXT: movi d2, #0000000000000000
15 ; CHECK-NEXT: shrn v1.4h, v1.4s, #16
16 ; CHECK-NEXT: fneg d2, d2
17 ; CHECK-NEXT: sub v3.4h, v0.4h, v1.4h
18 ; CHECK-NEXT: umull v2.4s, v3.4h, v2.4h
19 ; CHECK-NEXT: shrn v2.4h, v2.4s, #16
20 ; CHECK-NEXT: add v1.4h, v2.4h, v1.4h
21 ; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI0_2]
22 ; CHECK-NEXT: adrp x8, .LCPI0_3
23 ; CHECK-NEXT: ushl v1.4h, v1.4h, v2.4h
24 ; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI0_3]
25 ; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h
26 ; CHECK-NEXT: ret
27 %1 = urem <4 x i16> %x, <i16 95, i16 124, i16 98, i16 1003>
28 ret <4 x i16> %1
29 }
31 define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
32 ; CHECK-LABEL: fold_urem_vec_2:
33 ; CHECK: // %bb.0:
34 ; CHECK-NEXT: mov w8, #44151 // =0xac77
35 ; CHECK-NEXT: movi v2.4h, #95
36 ; CHECK-NEXT: dup v1.4h, w8
37 ; CHECK-NEXT: umull v1.4s, v0.4h, v1.4h
38 ; CHECK-NEXT: ushr v1.4s, v1.4s, #22
39 ; CHECK-NEXT: xtn v1.4h, v1.4s
40 ; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h
41 ; CHECK-NEXT: ret
42 %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
43 ret <4 x i16> %1
44 }
47 ; Don't fold if we can combine urem with udiv.
48 define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
49 ; CHECK-LABEL: combine_urem_udiv:
50 ; CHECK: // %bb.0:
51 ; CHECK-NEXT: mov w8, #44151 // =0xac77
52 ; CHECK-NEXT: movi v2.4h, #95
53 ; CHECK-NEXT: dup v1.4h, w8
54 ; CHECK-NEXT: umull v1.4s, v0.4h, v1.4h
55 ; CHECK-NEXT: ushr v1.4s, v1.4s, #22
56 ; CHECK-NEXT: xtn v1.4h, v1.4s
57 ; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h
58 ; CHECK-NEXT: add v0.4h, v0.4h, v1.4h
59 ; CHECK-NEXT: ret
60 %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
61 %2 = udiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
62 %3 = add <4 x i16> %1, %2
63 ret <4 x i16> %3
64 }
67 ; Don't fold for divisors that are a power of two.
68 define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) {
69 ; CHECK-LABEL: dont_fold_urem_power_of_two:
70 ; CHECK: // %bb.0:
71 ; CHECK-NEXT: adrp x8, .LCPI3_0
72 ; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI3_0]
73 ; CHECK-NEXT: adrp x8, .LCPI3_1
74 ; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI3_1]
75 ; CHECK-NEXT: adrp x8, .LCPI3_2
76 ; CHECK-NEXT: umull v1.4s, v0.4h, v1.4h
77 ; CHECK-NEXT: shrn v1.4h, v1.4s, #16
78 ; CHECK-NEXT: ushl v1.4h, v1.4h, v2.4h
79 ; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI3_2]
80 ; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h
81 ; CHECK-NEXT: ret
82 %1 = urem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>
83 ret <4 x i16> %1
84 }
86 ; Don't fold if the divisor is one.
87 define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {
88 ; CHECK-LABEL: dont_fold_urem_one:
89 ; CHECK: // %bb.0:
90 ; CHECK-NEXT: adrp x8, .LCPI4_0
91 ; CHECK-NEXT: movi d4, #0x0000000000ffff
92 ; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI4_0]
93 ; CHECK-NEXT: adrp x8, .LCPI4_1
94 ; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI4_1]
95 ; CHECK-NEXT: adrp x8, .LCPI4_2
96 ; CHECK-NEXT: umull v1.4s, v0.4h, v1.4h
97 ; CHECK-NEXT: shrn v1.4h, v1.4s, #16
98 ; CHECK-NEXT: sub v2.4h, v0.4h, v1.4h
99 ; CHECK-NEXT: umull v2.4s, v2.4h, v3.4h
100 ; CHECK-NEXT: movi d3, #0xffffffffffff0000
101 ; CHECK-NEXT: shrn v2.4h, v2.4s, #16
102 ; CHECK-NEXT: add v1.4h, v2.4h, v1.4h
103 ; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI4_2]
104 ; CHECK-NEXT: adrp x8, .LCPI4_3
105 ; CHECK-NEXT: ushl v1.4h, v1.4h, v2.4h
106 ; CHECK-NEXT: and v2.8b, v0.8b, v4.8b
107 ; CHECK-NEXT: and v1.8b, v1.8b, v3.8b
108 ; CHECK-NEXT: orr v1.8b, v2.8b, v1.8b
109 ; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI4_3]
110 ; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h
111 ; CHECK-NEXT: ret
112 %1 = urem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>
113 ret <4 x i16> %1
114 }
116 ; Don't fold if the divisor is 2^16.
117 define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
118 ; CHECK-LABEL: dont_fold_urem_i16_smax:
119 ; CHECK: // %bb.0:
120 ; CHECK-NEXT: ret
121 %1 = urem <4 x i16> %x, <i16 1, i16 65536, i16 23, i16 5423>
122 ret <4 x i16> %1
123 }
125 ; Don't fold i64 urem.
126 define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) {
127 ; CHECK-LABEL: dont_fold_urem_i64:
128 ; CHECK: // %bb.0:
129 ; CHECK-NEXT: mov x8, #17097 // =0x42c9
130 ; CHECK-NEXT: fmov x9, d1
131 ; CHECK-NEXT: mov x10, v1.d[1]
132 ; CHECK-NEXT: movk x8, #45590, lsl #16
133 ; CHECK-NEXT: mov x11, v0.d[1]
134 ; CHECK-NEXT: mov x12, #12109 // =0x2f4d
135 ; CHECK-NEXT: movk x8, #34192, lsl #32
136 ; CHECK-NEXT: movk x12, #52170, lsl #16
137 ; CHECK-NEXT: movi v0.2d, #0000000000000000
138 ; CHECK-NEXT: movk x8, #25644, lsl #48
139 ; CHECK-NEXT: movk x12, #28749, lsl #32
140 ; CHECK-NEXT: umulh x8, x9, x8
141 ; CHECK-NEXT: movk x12, #49499, lsl #48
142 ; CHECK-NEXT: lsr x13, x11, #1
143 ; CHECK-NEXT: umulh x12, x10, x12
144 ; CHECK-NEXT: sub x14, x9, x8
145 ; CHECK-NEXT: add x8, x8, x14, lsr #1
146 ; CHECK-NEXT: mov x14, #21445 // =0x53c5
147 ; CHECK-NEXT: movk x14, #1603, lsl #16
148 ; CHECK-NEXT: movk x14, #15432, lsl #32
149 ; CHECK-NEXT: lsr x8, x8, #4
150 ; CHECK-NEXT: movk x14, #25653, lsl #48
151 ; CHECK-NEXT: umulh x13, x13, x14
152 ; CHECK-NEXT: mov w14, #23 // =0x17
153 ; CHECK-NEXT: msub x8, x8, x14, x9
154 ; CHECK-NEXT: lsr x9, x12, #12
155 ; CHECK-NEXT: mov w12, #5423 // =0x152f
156 ; CHECK-NEXT: msub x9, x9, x12, x10
157 ; CHECK-NEXT: mov w12, #654 // =0x28e
158 ; CHECK-NEXT: lsr x10, x13, #7
159 ; CHECK-NEXT: msub x10, x10, x12, x11
160 ; CHECK-NEXT: fmov d1, x8
161 ; CHECK-NEXT: mov v1.d[1], x9
162 ; CHECK-NEXT: mov v0.d[1], x10
163 ; CHECK-NEXT: ret
164 %1 = urem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
165 ret <4 x i64> %1
166 }
168 define <16 x i8> @fold_urem_v16i8(<16 x i8> %x) {
169 ; CHECK-LABEL: fold_urem_v16i8:
170 ; CHECK: // %bb.0:
171 ; CHECK-NEXT: movi v1.16b, #205
172 ; CHECK-NEXT: umull2 v2.8h, v0.16b, v1.16b
173 ; CHECK-NEXT: umull v1.8h, v0.8b, v1.8b
174 ; CHECK-NEXT: uzp2 v1.16b, v1.16b, v2.16b
175 ; CHECK-NEXT: movi v2.16b, #10
176 ; CHECK-NEXT: ushr v1.16b, v1.16b, #3
177 ; CHECK-NEXT: mls v0.16b, v1.16b, v2.16b
178 ; CHECK-NEXT: ret
179 %1 = urem <16 x i8> %x, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>
180 ret <16 x i8> %1
181 }
183 define <8 x i8> @fold_urem_v8i8(<8 x i8> %x) {
184 ; CHECK-LABEL: fold_urem_v8i8:
185 ; CHECK: // %bb.0:
186 ; CHECK-NEXT: movi v1.8b, #205
187 ; CHECK-NEXT: movi v2.8b, #10
188 ; CHECK-NEXT: umull v1.8h, v0.8b, v1.8b
189 ; CHECK-NEXT: shrn v1.8b, v1.8h, #8
190 ; CHECK-NEXT: ushr v1.8b, v1.8b, #3
191 ; CHECK-NEXT: mls v0.8b, v1.8b, v2.8b
192 ; CHECK-NEXT: ret
193 %1 = urem <8 x i8> %x, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>
194 ret <8 x i8> %1
195 }
197 define <8 x i16> @fold_urem_v8i16(<8 x i16> %x) {
198 ; CHECK-LABEL: fold_urem_v8i16:
199 ; CHECK: // %bb.0:
200 ; CHECK-NEXT: mov w8, #52429 // =0xcccd
201 ; CHECK-NEXT: dup v1.8h, w8
202 ; CHECK-NEXT: umull2 v2.4s, v0.8h, v1.8h
203 ; CHECK-NEXT: umull v1.4s, v0.4h, v1.4h
204 ; CHECK-NEXT: uzp2 v1.8h, v1.8h, v2.8h
205 ; CHECK-NEXT: movi v2.8h, #10
206 ; CHECK-NEXT: ushr v1.8h, v1.8h, #3
207 ; CHECK-NEXT: mls v0.8h, v1.8h, v2.8h
208 ; CHECK-NEXT: ret
209 %1 = urem <8 x i16> %x, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
210 ret <8 x i16> %1
211 }
213 define <4 x i16> @fold_urem_v4i16(<4 x i16> %x) {
214 ; CHECK-LABEL: fold_urem_v4i16:
215 ; CHECK: // %bb.0:
216 ; CHECK-NEXT: mov w8, #52429 // =0xcccd
217 ; CHECK-NEXT: movi v2.4h, #10
218 ; CHECK-NEXT: dup v1.4h, w8
219 ; CHECK-NEXT: umull v1.4s, v0.4h, v1.4h
220 ; CHECK-NEXT: ushr v1.4s, v1.4s, #19
221 ; CHECK-NEXT: xtn v1.4h, v1.4s
222 ; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h
223 ; CHECK-NEXT: ret
224 %1 = urem <4 x i16> %x, <i16 10, i16 10, i16 10, i16 10>
225 ret <4 x i16> %1
226 }
228 define <4 x i32> @fold_urem_v4i32(<4 x i32> %x) {
229 ; CHECK-LABEL: fold_urem_v4i32:
230 ; CHECK: // %bb.0:
231 ; CHECK-NEXT: mov w8, #52429 // =0xcccd
232 ; CHECK-NEXT: movk w8, #52428, lsl #16
233 ; CHECK-NEXT: dup v1.4s, w8
234 ; CHECK-NEXT: umull2 v2.2d, v0.4s, v1.4s
235 ; CHECK-NEXT: umull v1.2d, v0.2s, v1.2s
236 ; CHECK-NEXT: uzp2 v1.4s, v1.4s, v2.4s
237 ; CHECK-NEXT: movi v2.4s, #10
238 ; CHECK-NEXT: ushr v1.4s, v1.4s, #3
239 ; CHECK-NEXT: mls v0.4s, v1.4s, v2.4s
240 ; CHECK-NEXT: ret
241 %1 = urem <4 x i32> %x, <i32 10, i32 10, i32 10, i32 10>
242 ret <4 x i32> %1
243 }
245 define <2 x i32> @fold_urem_v2i32(<2 x i32> %x) {
246 ; CHECK-LABEL: fold_urem_v2i32:
247 ; CHECK: // %bb.0:
248 ; CHECK-NEXT: mov w8, #52429 // =0xcccd
249 ; CHECK-NEXT: movi v2.2s, #10
250 ; CHECK-NEXT: movk w8, #52428, lsl #16
251 ; CHECK-NEXT: dup v1.2s, w8
252 ; CHECK-NEXT: umull v1.2d, v0.2s, v1.2s
253 ; CHECK-NEXT: ushr v1.2d, v1.2d, #35
254 ; CHECK-NEXT: xtn v1.2s, v1.2d
255 ; CHECK-NEXT: mls v0.2s, v1.2s, v2.2s
256 ; CHECK-NEXT: ret
257 %1 = urem <2 x i32> %x, <i32 10, i32 10>
258 ret <2 x i32> %1
259 }
261 define <2 x i64> @fold_urem_v2i64(<2 x i64> %x) {
262 ; CHECK-LABEL: fold_urem_v2i64:
263 ; CHECK: // %bb.0:
264 ; CHECK-NEXT: fmov x10, d0
265 ; CHECK-NEXT: mov x8, #-3689348814741910324 // =0xcccccccccccccccc
266 ; CHECK-NEXT: mov x9, v0.d[1]
267 ; CHECK-NEXT: movk x8, #52429
268 ; CHECK-NEXT: mov w12, #10 // =0xa
269 ; CHECK-NEXT: umulh x11, x10, x8
270 ; CHECK-NEXT: umulh x8, x9, x8
271 ; CHECK-NEXT: lsr x11, x11, #3
272 ; CHECK-NEXT: msub x10, x11, x12, x10
273 ; CHECK-NEXT: lsr x8, x8, #3
274 ; CHECK-NEXT: msub x8, x8, x12, x9
275 ; CHECK-NEXT: fmov d0, x10
276 ; CHECK-NEXT: mov v0.d[1], x8
277 ; CHECK-NEXT: ret
278 %1 = urem <2 x i64> %x, <i64 10, i64 10>
279 ret <2 x i64> %1
280 }
282 define <1 x i64> @fold_urem_v1i64(<1 x i64> %x) {
283 ; CHECK-LABEL: fold_urem_v1i64:
284 ; CHECK: // %bb.0:
285 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
286 ; CHECK-NEXT: fmov x9, d0
287 ; CHECK-NEXT: mov x8, #-3689348814741910324 // =0xcccccccccccccccc
288 ; CHECK-NEXT: mov w10, #10 // =0xa
289 ; CHECK-NEXT: movk x8, #52429
290 ; CHECK-NEXT: umulh x8, x9, x8
291 ; CHECK-NEXT: lsr x8, x8, #3
292 ; CHECK-NEXT: msub x8, x8, x10, x9
293 ; CHECK-NEXT: fmov d0, x8
294 ; CHECK-NEXT: ret
295 %1 = urem <1 x i64> %x, <i64 10>
296 ret <1 x i64> %1
297 }