[RISCV][VLOPT] Add vector narrowing integer right shift instructions to isSupportedIn...
[llvm-project.git] / llvm / test / CodeGen / PowerPC / early-ret2.ll
blob67a496adf14a0108a05f7eff1613b0b88e4c99f3
1 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-crbits | FileCheck %s
2 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-CRB
3 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
4 target triple = "powerpc64-unknown-linux-gnu"
6 define void @_Z8example3iPiS_() #0 {
7 entry:
8   br i1 undef, label %while.end, label %while.body.lr.ph
10 while.body.lr.ph:                                 ; preds = %entry
11   br i1 undef, label %while.end, label %while.body
13 while.body:                                       ; preds = %while.body, %while.body.lr.ph
14   br i1 false, label %while.end, label %while.body, !llvm.loop.vectorize.already_vectorized !0
16 while.end:                                        ; preds = %while.body, %while.body.lr.ph, %entry
17   ret void
19 ; CHECK: @_Z8example3iPiS_
20 ; CHECK: bnelr
22 ; CHECK-CRB: @_Z8example3iPiS_
23 ; CHECK-CRB: bclr 12,
26 attributes #0 = { noinline nounwind }
28 !0 = !{}