[TableGen] Fix validateOperandClass for non Phyical Reg (#118146)
[llvm-project.git] / llvm / test / CodeGen / SPIRV / transcoding / ReqdSubgroupSize.ll
blob2bc0a95e56be22d290b9963ea8f788f2be841410
1 ;; Check translation of intel_reqd_sub_group_size metadata to SubgroupSize
2 ;; execution mode and back. The IR is producded from the following OpenCL C code:
3 ;; kernel __attribute__((intel_reqd_sub_group_size(8)))
4 ;; void foo() {}
6 ; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
8 ; CHECK-SPIRV: OpCapability SubgroupDispatch
9 ; CHECK-SPIRV: OpEntryPoint Kernel %[[#kernel:]] "foo"
10 ; CHECK-SPIRV: OpExecutionMode %[[#kernel]] SubgroupSize 8
12 define spir_kernel void @foo() !intel_reqd_sub_group_size !0 {
13 entry:
14   ret void
17 !0 = !{i32 8}