1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt -mtriple=s390x-unknown-linux -mcpu=z16 -passes=slp-vectorizer -S -slp-revec %s | FileCheck %s
4 @g_155 = external dso_local global i64, align 8
5 @g_855 = external dso_local global i8, align 2
6 @g_3_1_0 = external dso_local global i32, align 4
7 @g_7 = external dso_local global [5 x i32], align 4
9 ; Function Attrs: nofree norecurse noreturn nounwind memory(readwrite, argmem: none)
10 define void @func_1() {
11 ; CHECK-LABEL: @func_1(
12 ; CHECK-NEXT: [[DOTPRE:%.*]] = load i32, ptr @g_7, align 4
13 ; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr getelementptr inbounds nuw (i8, ptr @g_7, i64 4), align 4
14 ; CHECK-NEXT: br label [[DOTLOOPEXIT:%.*]]
16 ; CHECK-NEXT: [[TMP2:%.*]] = phi i32 [ [[OP_RDX15:%.*]], [[DOTLOOPEXIT]] ], [ [[DOTPRE]], [[TMP0:%.*]] ]
17 ; CHECK-NEXT: [[TMP3:%.*]] = phi <4 x i32> [ [[TMP71:%.*]], [[DOTLOOPEXIT]] ], [ [[TMP1]], [[TMP0]] ]
18 ; CHECK-NEXT: [[TMP4:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
19 ; CHECK-NEXT: [[TMP5:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
20 ; CHECK-NEXT: [[TMP6:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
21 ; CHECK-NEXT: [[TMP7:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
22 ; CHECK-NEXT: [[TMP8:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
23 ; CHECK-NEXT: [[TMP9:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
24 ; CHECK-NEXT: [[TMP10:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
25 ; CHECK-NEXT: [[TMP11:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
26 ; CHECK-NEXT: [[TMP12:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
27 ; CHECK-NEXT: [[TMP13:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
28 ; CHECK-NEXT: [[TMP14:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
29 ; CHECK-NEXT: [[TMP15:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
30 ; CHECK-NEXT: [[TMP16:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
31 ; CHECK-NEXT: [[TMP17:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
32 ; CHECK-NEXT: [[TMP18:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
33 ; CHECK-NEXT: [[TMP19:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
34 ; CHECK-NEXT: [[TMP20:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i32 0
35 ; CHECK-NEXT: [[TMP21:%.*]] = insertelement <4 x i32> [[TMP20]], i32 [[TMP9]], i32 1
36 ; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i32> [[TMP21]], i32 [[TMP14]], i32 2
37 ; CHECK-NEXT: [[TMP23:%.*]] = insertelement <4 x i32> [[TMP22]], i32 [[TMP19]], i32 3
38 ; CHECK-NEXT: [[TMP24:%.*]] = icmp eq <4 x i32> [[TMP23]], zeroinitializer
39 ; CHECK-NEXT: [[TMP25:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
40 ; CHECK-NEXT: [[TMP26:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
41 ; CHECK-NEXT: [[TMP27:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
42 ; CHECK-NEXT: [[TMP28:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
43 ; CHECK-NEXT: [[TMP29:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
44 ; CHECK-NEXT: [[DOTNOT2_410:%.*]] = icmp eq i32 [[TMP29]], 0
45 ; CHECK-NEXT: [[TMP30:%.*]] = zext i1 [[DOTNOT2_410]] to i32
46 ; CHECK-NEXT: [[TMP31:%.*]] = zext <4 x i1> [[TMP24]] to <4 x i32>
47 ; CHECK-NEXT: [[TMP32:%.*]] = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> [[TMP31]])
48 ; CHECK-NEXT: [[OP_RDX:%.*]] = xor i32 [[TMP32]], [[TMP30]]
49 ; CHECK-NEXT: [[OP_RDX15]] = xor i32 [[OP_RDX]], [[TMP2]]
50 ; CHECK-NEXT: [[TMP33:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
51 ; CHECK-NEXT: [[TMP34:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
52 ; CHECK-NEXT: [[TMP35:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
53 ; CHECK-NEXT: [[TMP36:%.*]] = load volatile i32, ptr @g_3_1_0, align 4
54 ; CHECK-NEXT: [[TMP37:%.*]] = insertelement <4 x i32> poison, i32 [[TMP5]], i32 0
55 ; CHECK-NEXT: [[TMP38:%.*]] = insertelement <4 x i32> [[TMP37]], i32 [[TMP6]], i32 1
56 ; CHECK-NEXT: [[TMP39:%.*]] = insertelement <4 x i32> [[TMP38]], i32 [[TMP7]], i32 2
57 ; CHECK-NEXT: [[TMP40:%.*]] = insertelement <4 x i32> [[TMP39]], i32 [[TMP8]], i32 3
58 ; CHECK-NEXT: [[TMP41:%.*]] = icmp eq <4 x i32> [[TMP40]], zeroinitializer
59 ; CHECK-NEXT: [[TMP42:%.*]] = zext <4 x i1> [[TMP41]] to <4 x i32>
60 ; CHECK-NEXT: [[TMP43:%.*]] = xor <4 x i32> [[TMP3]], [[TMP42]]
61 ; CHECK-NEXT: [[TMP44:%.*]] = insertelement <4 x i32> poison, i32 [[TMP10]], i32 0
62 ; CHECK-NEXT: [[TMP45:%.*]] = insertelement <4 x i32> [[TMP44]], i32 [[TMP11]], i32 1
63 ; CHECK-NEXT: [[TMP46:%.*]] = insertelement <4 x i32> [[TMP45]], i32 [[TMP12]], i32 2
64 ; CHECK-NEXT: [[TMP47:%.*]] = insertelement <4 x i32> [[TMP46]], i32 [[TMP13]], i32 3
65 ; CHECK-NEXT: [[TMP48:%.*]] = icmp eq <4 x i32> [[TMP47]], zeroinitializer
66 ; CHECK-NEXT: [[TMP49:%.*]] = zext <4 x i1> [[TMP48]] to <4 x i32>
67 ; CHECK-NEXT: [[TMP50:%.*]] = xor <4 x i32> [[TMP43]], [[TMP49]]
68 ; CHECK-NEXT: [[TMP51:%.*]] = insertelement <4 x i32> poison, i32 [[TMP15]], i32 0
69 ; CHECK-NEXT: [[TMP52:%.*]] = insertelement <4 x i32> [[TMP51]], i32 [[TMP16]], i32 1
70 ; CHECK-NEXT: [[TMP53:%.*]] = insertelement <4 x i32> [[TMP52]], i32 [[TMP17]], i32 2
71 ; CHECK-NEXT: [[TMP54:%.*]] = insertelement <4 x i32> [[TMP53]], i32 [[TMP18]], i32 3
72 ; CHECK-NEXT: [[TMP55:%.*]] = icmp eq <4 x i32> [[TMP54]], zeroinitializer
73 ; CHECK-NEXT: [[TMP56:%.*]] = zext <4 x i1> [[TMP55]] to <4 x i32>
74 ; CHECK-NEXT: [[TMP57:%.*]] = xor <4 x i32> [[TMP50]], [[TMP56]]
75 ; CHECK-NEXT: [[TMP58:%.*]] = insertelement <4 x i32> poison, i32 [[TMP25]], i32 0
76 ; CHECK-NEXT: [[TMP59:%.*]] = insertelement <4 x i32> [[TMP58]], i32 [[TMP26]], i32 1
77 ; CHECK-NEXT: [[TMP60:%.*]] = insertelement <4 x i32> [[TMP59]], i32 [[TMP27]], i32 2
78 ; CHECK-NEXT: [[TMP61:%.*]] = insertelement <4 x i32> [[TMP60]], i32 [[TMP28]], i32 3
79 ; CHECK-NEXT: [[TMP62:%.*]] = icmp eq <4 x i32> [[TMP61]], zeroinitializer
80 ; CHECK-NEXT: [[TMP63:%.*]] = zext <4 x i1> [[TMP62]] to <4 x i32>
81 ; CHECK-NEXT: [[TMP64:%.*]] = xor <4 x i32> [[TMP57]], [[TMP63]]
82 ; CHECK-NEXT: [[TMP65:%.*]] = insertelement <4 x i32> poison, i32 [[TMP33]], i32 0
83 ; CHECK-NEXT: [[TMP66:%.*]] = insertelement <4 x i32> [[TMP65]], i32 [[TMP34]], i32 1
84 ; CHECK-NEXT: [[TMP67:%.*]] = insertelement <4 x i32> [[TMP66]], i32 [[TMP35]], i32 2
85 ; CHECK-NEXT: [[TMP68:%.*]] = insertelement <4 x i32> [[TMP67]], i32 [[TMP36]], i32 3
86 ; CHECK-NEXT: [[TMP69:%.*]] = icmp eq <4 x i32> [[TMP68]], zeroinitializer
87 ; CHECK-NEXT: [[TMP70:%.*]] = zext <4 x i1> [[TMP69]] to <4 x i32>
88 ; CHECK-NEXT: [[TMP71]] = xor <4 x i32> [[TMP64]], [[TMP70]]
89 ; CHECK-NEXT: br label [[DOTLOOPEXIT]]
91 %.pre = load i32, ptr @g_7, align 4
92 %1 = load <4 x i32>, ptr getelementptr inbounds nuw (i8, ptr @g_7, i64 4), align 4
95 .loopexit: ; preds = %.loopexit, %0
96 %2 = phi i32 [ %op.rdx15, %.loopexit ], [ %.pre, %0 ]
97 %3 = phi <4 x i32> [ %71, %.loopexit ], [ %1, %0 ]
98 %4 = load volatile i32, ptr @g_3_1_0, align 4
99 %5 = load volatile i32, ptr @g_3_1_0, align 4
100 %6 = load volatile i32, ptr @g_3_1_0, align 4
101 %7 = load volatile i32, ptr @g_3_1_0, align 4
102 %8 = load volatile i32, ptr @g_3_1_0, align 4
103 %9 = load volatile i32, ptr @g_3_1_0, align 4
104 %10 = load volatile i32, ptr @g_3_1_0, align 4
105 %11 = load volatile i32, ptr @g_3_1_0, align 4
106 %12 = load volatile i32, ptr @g_3_1_0, align 4
107 %13 = load volatile i32, ptr @g_3_1_0, align 4
108 %14 = load volatile i32, ptr @g_3_1_0, align 4
109 %15 = load volatile i32, ptr @g_3_1_0, align 4
110 %16 = load volatile i32, ptr @g_3_1_0, align 4
111 %17 = load volatile i32, ptr @g_3_1_0, align 4
112 %18 = load volatile i32, ptr @g_3_1_0, align 4
113 %19 = load volatile i32, ptr @g_3_1_0, align 4
114 %20 = insertelement <4 x i32> poison, i32 %4, i32 0
115 %21 = insertelement <4 x i32> %20, i32 %9, i32 1
116 %22 = insertelement <4 x i32> %21, i32 %14, i32 2
117 %23 = insertelement <4 x i32> %22, i32 %19, i32 3
118 %24 = icmp eq <4 x i32> %23, zeroinitializer
119 %25 = load volatile i32, ptr @g_3_1_0, align 4
120 %26 = load volatile i32, ptr @g_3_1_0, align 4
121 %27 = load volatile i32, ptr @g_3_1_0, align 4
122 %28 = load volatile i32, ptr @g_3_1_0, align 4
123 %29 = load volatile i32, ptr @g_3_1_0, align 4
124 %.not2.410 = icmp eq i32 %29, 0
125 %30 = zext i1 %.not2.410 to i32
126 %31 = zext <4 x i1> %24 to <4 x i32>
127 %32 = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %31)
128 %op.rdx = xor i32 %32, %30
129 %op.rdx15 = xor i32 %op.rdx, %2
130 %33 = load volatile i32, ptr @g_3_1_0, align 4
131 %34 = load volatile i32, ptr @g_3_1_0, align 4
132 %35 = load volatile i32, ptr @g_3_1_0, align 4
133 %36 = load volatile i32, ptr @g_3_1_0, align 4
134 %37 = insertelement <4 x i32> poison, i32 %5, i32 0
135 %38 = insertelement <4 x i32> %37, i32 %6, i32 1
136 %39 = insertelement <4 x i32> %38, i32 %7, i32 2
137 %40 = insertelement <4 x i32> %39, i32 %8, i32 3
138 %41 = icmp eq <4 x i32> %40, zeroinitializer
139 %42 = zext <4 x i1> %41 to <4 x i32>
140 %43 = xor <4 x i32> %3, %42
141 %44 = insertelement <4 x i32> poison, i32 %10, i32 0
142 %45 = insertelement <4 x i32> %44, i32 %11, i32 1
143 %46 = insertelement <4 x i32> %45, i32 %12, i32 2
144 %47 = insertelement <4 x i32> %46, i32 %13, i32 3
145 %48 = icmp eq <4 x i32> %47, zeroinitializer
146 %49 = zext <4 x i1> %48 to <4 x i32>
147 %50 = xor <4 x i32> %43, %49
148 %51 = insertelement <4 x i32> poison, i32 %15, i32 0
149 %52 = insertelement <4 x i32> %51, i32 %16, i32 1
150 %53 = insertelement <4 x i32> %52, i32 %17, i32 2
151 %54 = insertelement <4 x i32> %53, i32 %18, i32 3
152 %55 = icmp eq <4 x i32> %54, zeroinitializer
153 %56 = zext <4 x i1> %55 to <4 x i32>
154 %57 = xor <4 x i32> %50, %56
155 %58 = insertelement <4 x i32> poison, i32 %25, i32 0
156 %59 = insertelement <4 x i32> %58, i32 %26, i32 1
157 %60 = insertelement <4 x i32> %59, i32 %27, i32 2
158 %61 = insertelement <4 x i32> %60, i32 %28, i32 3
159 %62 = icmp eq <4 x i32> %61, zeroinitializer
160 %63 = zext <4 x i1> %62 to <4 x i32>
161 %64 = xor <4 x i32> %57, %63
162 %65 = insertelement <4 x i32> poison, i32 %33, i32 0
163 %66 = insertelement <4 x i32> %65, i32 %34, i32 1
164 %67 = insertelement <4 x i32> %66, i32 %35, i32 2
165 %68 = insertelement <4 x i32> %67, i32 %36, i32 3
166 %69 = icmp eq <4 x i32> %68, zeroinitializer
167 %70 = zext <4 x i1> %69 to <4 x i32>
168 %71 = xor <4 x i32> %64, %70