[RISCV][VLOPT] Add vector narrowing integer right shift instructions to isSupportedIn...
[llvm-project.git] / llvm / test / tools / llvm-mca / ARM / m4-ldr-str-w.s
blobcb4eeaff4b2a8347dc5ac83df16103511f297704
1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2 # RUN: llvm-mca -mtriple thumbv7m-none-eabi -mcpu=cortex-m4 < %s | FileCheck %s
3 str.w r1, [r0], #16
4 str.w r1, [r0, 16]!
5 strb.w r1, [r0], #16
6 strb.w r1, [r0, 16]!
7 strh.w r1, [r0], #16
8 strh.w r1, [r0, 16]!
9 ldr.w r1, [r0], #16
10 ldr.w r1, [r0, 16]!
11 ldrb.w r1, [r0], #16
12 ldrb.w r1, [r0, 16]!
13 ldrh.w r1, [r0], #16
14 ldrh.w r1, [r0, 16]!
15 ldrsb.w r1, [r0], #16
16 ldrsb.w r1, [r0, 16]!
17 ldrsh.w r1, [r0], #16
18 ldrsh.w r1, [r0, 16]!
20 # CHECK: Iterations: 100
21 # CHECK-NEXT: Instructions: 1600
22 # CHECK-NEXT: Total Cycles: 2601
23 # CHECK-NEXT: Total uOps: 1600
25 # CHECK: Dispatch Width: 1
26 # CHECK-NEXT: uOps Per Cycle: 0.62
27 # CHECK-NEXT: IPC: 0.62
28 # CHECK-NEXT: Block RThroughput: 16.0
30 # CHECK: Instruction Info:
31 # CHECK-NEXT: [1]: #uOps
32 # CHECK-NEXT: [2]: Latency
33 # CHECK-NEXT: [3]: RThroughput
34 # CHECK-NEXT: [4]: MayLoad
35 # CHECK-NEXT: [5]: MayStore
36 # CHECK-NEXT: [6]: HasSideEffects (U)
38 # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
39 # CHECK-NEXT: 1 1 1.00 * str r1, [r0], #16
40 # CHECK-NEXT: 1 1 1.00 * str r1, [r0, #16]!
41 # CHECK-NEXT: 1 1 1.00 * strb r1, [r0], #16
42 # CHECK-NEXT: 1 1 1.00 * strb r1, [r0, #16]!
43 # CHECK-NEXT: 1 1 1.00 * strh r1, [r0], #16
44 # CHECK-NEXT: 1 1 1.00 * strh r1, [r0, #16]!
45 # CHECK-NEXT: 1 2 1.00 * ldr r1, [r0], #16
46 # CHECK-NEXT: 1 2 1.00 * ldr r1, [r0, #16]!
47 # CHECK-NEXT: 1 2 1.00 * ldrb r1, [r0], #16
48 # CHECK-NEXT: 1 2 1.00 * ldrb r1, [r0, #16]!
49 # CHECK-NEXT: 1 2 1.00 * ldrh r1, [r0], #16
50 # CHECK-NEXT: 1 2 1.00 * ldrh r1, [r0, #16]!
51 # CHECK-NEXT: 1 2 1.00 * ldrsb r1, [r0], #16
52 # CHECK-NEXT: 1 2 1.00 * ldrsb r1, [r0, #16]!
53 # CHECK-NEXT: 1 2 1.00 * ldrsh r1, [r0], #16
54 # CHECK-NEXT: 1 2 1.00 * ldrsh r1, [r0, #16]!
56 # CHECK: Resources:
57 # CHECK-NEXT: [0] - M4Unit
59 # CHECK: Resource pressure per iteration:
60 # CHECK-NEXT: [0]
61 # CHECK-NEXT: 16.00
63 # CHECK: Resource pressure by instruction:
64 # CHECK-NEXT: [0] Instructions:
65 # CHECK-NEXT: 1.00 str r1, [r0], #16
66 # CHECK-NEXT: 1.00 str r1, [r0, #16]!
67 # CHECK-NEXT: 1.00 strb r1, [r0], #16
68 # CHECK-NEXT: 1.00 strb r1, [r0, #16]!
69 # CHECK-NEXT: 1.00 strh r1, [r0], #16
70 # CHECK-NEXT: 1.00 strh r1, [r0, #16]!
71 # CHECK-NEXT: 1.00 ldr r1, [r0], #16
72 # CHECK-NEXT: 1.00 ldr r1, [r0, #16]!
73 # CHECK-NEXT: 1.00 ldrb r1, [r0], #16
74 # CHECK-NEXT: 1.00 ldrb r1, [r0, #16]!
75 # CHECK-NEXT: 1.00 ldrh r1, [r0], #16
76 # CHECK-NEXT: 1.00 ldrh r1, [r0, #16]!
77 # CHECK-NEXT: 1.00 ldrsb r1, [r0], #16
78 # CHECK-NEXT: 1.00 ldrsb r1, [r0, #16]!
79 # CHECK-NEXT: 1.00 ldrsh r1, [r0], #16
80 # CHECK-NEXT: 1.00 ldrsh r1, [r0, #16]!