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[RISCV][VLOPT] Add vector narrowing integer right shift instructions to isSupportedIn...
[llvm-project.git] / llvm / unittests / CodeGen / GlobalISel / KnownBitsTest.cpp
blob34a36ba68d7c03c61dbdf41aa104ac04593f9ace
1 //===- KnownBitsTest.cpp -------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "GISelMITest.h"
10 #include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
11 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
12
13 TEST_F(AArch64GISelMITest, TestKnownBitsCst) {
14 StringRef MIRString = " %3:_(s8) = G_CONSTANT i8 1\n"
15 " %4:_(s8) = COPY %3\n";
16 setUp(MIRString);
17 if (!TM)
18 GTEST_SKIP();
19 unsigned CopyReg = Copies[Copies.size() - 1];
20 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
21 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
22 unsigned DstReg = FinalCopy->getOperand(0).getReg();
23 GISelKnownBits Info(*MF);
24 KnownBits Res = Info.getKnownBits(SrcReg);
25 EXPECT_EQ((uint64_t)1, Res.One.getZExtValue());
26 EXPECT_EQ((uint64_t)0xfe, Res.Zero.getZExtValue());
27
28 KnownBits Res2 = Info.getKnownBits(DstReg);
29 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
30 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
31 }
32
33 TEST_F(AArch64GISelMITest, TestKnownBitsCstWithClass) {
34 StringRef MIRString = " %10:gpr32 = MOVi32imm 1\n"
35 " %4:_(s32) = COPY %10\n";
36 setUp(MIRString);
37 if (!TM)
38 GTEST_SKIP();
39 unsigned CopyReg = Copies[Copies.size() - 1];
40 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
41 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
42 unsigned DstReg = FinalCopy->getOperand(0).getReg();
43 GISelKnownBits Info(*MF);
44 KnownBits Res = Info.getKnownBits(SrcReg);
45 // We can't analyze %3 due to the register class constraint. We will get a
46 // default-constructed KnownBits back.
47 EXPECT_EQ((uint64_t)1, Res.getBitWidth());
48 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
49 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue());
50
51 KnownBits Res2 = Info.getKnownBits(DstReg);
52 // We still don't know the values due to the register class constraint but %4
53 // did reveal the size of %3.
54 EXPECT_EQ((uint64_t)32, Res2.getBitWidth());
55 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
56 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
57 }
58
59 // Check that we are able to track bits through PHIs
60 // and get the intersections of everything we know on each operand.
61 TEST_F(AArch64GISelMITest, TestKnownBitsCstPHI) {
62 StringRef MIRString = " bb.10:\n"
63 " %10:_(s8) = G_CONSTANT i8 3\n"
64 " %11:_(s1) = G_IMPLICIT_DEF\n"
65 " G_BRCOND %11(s1), %bb.11\n"
66 " G_BR %bb.12\n"
67 "\n"
68 " bb.11:\n"
69 " %12:_(s8) = G_CONSTANT i8 2\n"
70 " G_BR %bb.12\n"
71 "\n"
72 " bb.12:\n"
73 " %13:_(s8) = PHI %10(s8), %bb.10, %12(s8), %bb.11\n"
74 " %14:_(s8) = COPY %13\n";
75 setUp(MIRString);
76 if (!TM)
77 GTEST_SKIP();
78 Register CopyReg = Copies[Copies.size() - 1];
79 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
80 Register SrcReg = FinalCopy->getOperand(1).getReg();
81 Register DstReg = FinalCopy->getOperand(0).getReg();
82 GISelKnownBits Info(*MF);
83 KnownBits Res = Info.getKnownBits(SrcReg);
84 EXPECT_EQ((uint64_t)2, Res.One.getZExtValue());
85 EXPECT_EQ((uint64_t)0xfc, Res.Zero.getZExtValue());
86
87 KnownBits Res2 = Info.getKnownBits(DstReg);
88 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
89 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
90 }
91
92 // Check that we report we know nothing when we hit a
93 // non-generic register.
94 // Note: this could be improved though!
95 TEST_F(AArch64GISelMITest, TestKnownBitsCstPHIToNonGenericReg) {
96 StringRef MIRString = " bb.10:\n"
97 " %10:gpr32 = MOVi32imm 3\n"
98 " %11:_(s1) = G_IMPLICIT_DEF\n"
99 " G_BRCOND %11(s1), %bb.11\n"
100 " G_BR %bb.12\n"
101 "\n"
102 " bb.11:\n"
103 " %12:_(s8) = G_CONSTANT i8 2\n"
104 " G_BR %bb.12\n"
105 "\n"
106 " bb.12:\n"
107 " %13:_(s8) = PHI %10, %bb.10, %12(s8), %bb.11\n"
108 " %14:_(s8) = COPY %13\n";
109 setUp(MIRString);
110 if (!TM)
111 GTEST_SKIP();
112 Register CopyReg = Copies[Copies.size() - 1];
113 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
114 Register SrcReg = FinalCopy->getOperand(1).getReg();
115 Register DstReg = FinalCopy->getOperand(0).getReg();
116 GISelKnownBits Info(*MF);
117 KnownBits Res = Info.getKnownBits(SrcReg);
118 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
119 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue());
120
121 KnownBits Res2 = Info.getKnownBits(DstReg);
122 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
123 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
124 }
125
126 // Check that we know nothing when at least one value of a PHI
127 // comes from something we cannot analysis.
128 // This test is not particularly interesting, it is just
129 // here to cover the code that stops the analysis of PHIs
130 // earlier. In that case, we would not even look at the
131 // second incoming value.
132 TEST_F(AArch64GISelMITest, TestKnownBitsUnknownPHI) {
133 StringRef MIRString =
134 " bb.10:\n"
135 " %10:_(s64) = COPY %0\n"
136 " %11:_(s1) = G_IMPLICIT_DEF\n"
137 " G_BRCOND %11(s1), %bb.11\n"
138 " G_BR %bb.12\n"
139 "\n"
140 " bb.11:\n"
141 " %12:_(s64) = G_CONSTANT i64 2\n"
142 " G_BR %bb.12\n"
143 "\n"
144 " bb.12:\n"
145 " %13:_(s64) = PHI %10(s64), %bb.10, %12(s64), %bb.11\n"
146 " %14:_(s64) = COPY %13\n";
147 setUp(MIRString);
148 if (!TM)
149 GTEST_SKIP();
150 Register CopyReg = Copies[Copies.size() - 1];
151 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
152 Register SrcReg = FinalCopy->getOperand(1).getReg();
153 Register DstReg = FinalCopy->getOperand(0).getReg();
154 GISelKnownBits Info(*MF);
155 KnownBits Res = Info.getKnownBits(SrcReg);
156 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
157 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue());
158
159 KnownBits Res2 = Info.getKnownBits(DstReg);
160 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
161 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
162 }
163
164 // Check that we manage to process PHIs that loop on themselves.
165 // For now, the analysis just stops and assumes it knows nothing,
166 // eventually we could teach it how to properly track phis that
167 // loop back.
168 TEST_F(AArch64GISelMITest, TestKnownBitsCstPHIWithLoop) {
169 StringRef MIRString =
170 " bb.10:\n"
171 " %10:_(s8) = G_CONSTANT i8 3\n"
172 " %11:_(s1) = G_IMPLICIT_DEF\n"
173 " G_BRCOND %11(s1), %bb.11\n"
174 " G_BR %bb.12\n"
175 "\n"
176 " bb.11:\n"
177 " %12:_(s8) = G_CONSTANT i8 2\n"
178 " G_BR %bb.12\n"
179 "\n"
180 " bb.12:\n"
181 " %13:_(s8) = PHI %10(s8), %bb.10, %12(s8), %bb.11, %14(s8), %bb.12\n"
182 " %14:_(s8) = COPY %13\n"
183 " G_BR %bb.12\n";
184 setUp(MIRString);
185 if (!TM)
186 GTEST_SKIP();
187 Register CopyReg = Copies[Copies.size() - 1];
188 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
189 Register SrcReg = FinalCopy->getOperand(1).getReg();
190 Register DstReg = FinalCopy->getOperand(0).getReg();
191 GISelKnownBits Info(*MF);
192 KnownBits Res = Info.getKnownBits(SrcReg);
193 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
194 EXPECT_EQ((uint64_t)0, Res.Zero.getZExtValue());
195
196 KnownBits Res2 = Info.getKnownBits(DstReg);
197 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
198 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
199 }
200
201 // Check that we don't try to analysis PHIs progression.
202 // Setting a deep enough max depth would allow to effectively simulate
203 // what happens in the loop.
204 // Thus, with a deep enough depth, we could actually figure out
205 // that %14's zero known bits are actually at least what we know
206 // for %10, right shifted by one.
207 // However, this process is super expensive compile-time wise and
208 // we don't want to reach that conclusion while playing with max depth.
209 // For now, the analysis just stops and assumes it knows nothing
210 // on PHIs, but eventually we could teach it how to properly track
211 // phis that loop back without relying on the luck effect of max
212 // depth.
213 TEST_F(AArch64GISelMITest, TestKnownBitsDecreasingCstPHIWithLoop) {
214 StringRef MIRString = " bb.10:\n"
215 " %10:_(s8) = G_CONSTANT i8 5\n"
216 " %11:_(s8) = G_CONSTANT i8 1\n"
217 "\n"
218 " bb.12:\n"
219 " %13:_(s8) = PHI %10(s8), %bb.10, %14(s8), %bb.12\n"
220 " %14:_(s8) = G_LSHR %13, %11\n"
221 " %15:_(s8) = COPY %14\n"
222 " G_BR %bb.12\n";
223 setUp(MIRString);
224 if (!TM)
225 GTEST_SKIP();
226 Register CopyReg = Copies[Copies.size() - 1];
227 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
228 Register SrcReg = FinalCopy->getOperand(1).getReg();
229 Register DstReg = FinalCopy->getOperand(0).getReg();
230 GISelKnownBits Info(*MF, /*MaxDepth=*/24);
231 KnownBits Res = Info.getKnownBits(SrcReg);
232 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
233 // A single iteration on the PHI (%13) gives:
234 // %10 has known zero of 0xFA
235 // %12 has known zero of 0x80 (we shift right by one so high bit is zero)
236 // Therefore, %14's known zero are 0x80 shifted by one 0xC0.
237 // If we had simulated the loop we could have more zero bits, basically
238 // up to 0xFC (count leading zero of 5, + 1).
239 EXPECT_EQ((uint64_t)0xC0, Res.Zero.getZExtValue());
240
241 KnownBits Res2 = Info.getKnownBits(DstReg);
242 EXPECT_EQ(Res.One.getZExtValue(), Res2.One.getZExtValue());
243 EXPECT_EQ(Res.Zero.getZExtValue(), Res2.Zero.getZExtValue());
244 }
245
246 TEST_F(AArch64GISelMITest, TestKnownBitsPtrToIntViceVersa) {
247 StringRef MIRString = " %3:_(s16) = G_CONSTANT i16 256\n"
248 " %4:_(p0) = G_INTTOPTR %3\n"
249 " %5:_(s32) = G_PTRTOINT %4\n"
250 " %6:_(s32) = COPY %5\n";
251 setUp(MIRString);
252 if (!TM)
253 GTEST_SKIP();
254 unsigned CopyReg = Copies[Copies.size() - 1];
255 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
256 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
257 GISelKnownBits Info(*MF);
258 KnownBits Res = Info.getKnownBits(SrcReg);
259 EXPECT_EQ(256u, Res.One.getZExtValue());
260 EXPECT_EQ(0xfffffeffu, Res.Zero.getZExtValue());
261 }
262
263 TEST_F(AArch64GISelMITest, TestKnownBitsAND) {
264 StringRef MIRString = R"(
265 %ptr:_(p0) = G_IMPLICIT_DEF
266 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
267 %mask0:_(s8) = G_CONSTANT i8 52
268 %mask1:_(s8) = G_CONSTANT i8 10
269 %tmp0:_(s8) = G_AND %unknown, %mask0
270 %val0:_(s8) = G_OR %tmp0, %mask1
271 %mask2:_(s8) = G_CONSTANT i8 32
272 %mask3:_(s8) = G_CONSTANT i8 24
273 %tmp1:_(s8) = G_AND %unknown, %mask2
274 %val1:_(s8) = G_OR %tmp1, %mask3
275 %and:_(s8) = G_AND %val0, %val1
276 %copy_and:_(s8) = COPY %and
277 )";
278
279 setUp(MIRString);
280 if (!TM)
281 GTEST_SKIP();
282
283 Register CopyReg = Copies[Copies.size() - 1];
284 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
285 Register SrcReg = FinalCopy->getOperand(1).getReg();
286 GISelKnownBits Info(*MF);
287 KnownBits Res = Info.getKnownBits(SrcReg);
288 // 00??1?10
289 // & 00?11000
290 // = 00??1000
291 EXPECT_EQ(0x08u, Res.One.getZExtValue());
292 EXPECT_EQ(0xC7u, Res.Zero.getZExtValue());
293 }
294
295 TEST_F(AArch64GISelMITest, TestKnownBitsOR) {
296 StringRef MIRString = R"(
297 %ptr:_(p0) = G_IMPLICIT_DEF
298 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
299 %mask0:_(s8) = G_CONSTANT i8 52
300 %mask1:_(s8) = G_CONSTANT i8 10
301 %tmp0:_(s8) = G_AND %unknown, %mask0
302 %val0:_(s8) = G_OR %tmp0, %mask1
303 %mask2:_(s8) = G_CONSTANT i8 32
304 %mask3:_(s8) = G_CONSTANT i8 24
305 %tmp1:_(s8) = G_AND %unknown, %mask2
306 %val1:_(s8) = G_OR %tmp1, %mask3
307 %or:_(s8) = G_OR %val0, %val1
308 %copy_or:_(s8) = COPY %or
309 )";
310
311 setUp(MIRString);
312 if (!TM)
313 GTEST_SKIP();
314
315 Register CopyReg = Copies[Copies.size() - 1];
316 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
317 Register SrcReg = FinalCopy->getOperand(1).getReg();
318 GISelKnownBits Info(*MF);
319 KnownBits Res = Info.getKnownBits(SrcReg);
320 // 00??1?10
321 // | 00?11000
322 // = 00?11?10
323 EXPECT_EQ(0x1Au, Res.One.getZExtValue());
324 EXPECT_EQ(0xC1u, Res.Zero.getZExtValue());
325 }
326
327 TEST_F(AArch64GISelMITest, TestKnownBitsXOR) {
328 StringRef MIRString = R"(
329 %ptr:_(p0) = G_IMPLICIT_DEF
330 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
331 %mask0:_(s8) = G_CONSTANT i8 52
332 %mask1:_(s8) = G_CONSTANT i8 10
333 %tmp0:_(s8) = G_AND %unknown, %mask0
334 %val0:_(s8) = G_OR %tmp0, %mask1
335 %mask2:_(s8) = G_CONSTANT i8 32
336 %mask3:_(s8) = G_CONSTANT i8 24
337 %tmp1:_(s8) = G_AND %unknown, %mask2
338 %val1:_(s8) = G_OR %tmp1, %mask3
339 %xor:_(s8) = G_XOR %val0, %val1
340 %copy_xor:_(s8) = COPY %xor
341 )";
342
343 setUp(MIRString);
344 if (!TM)
345 GTEST_SKIP();
346
347 Register CopyReg = Copies[Copies.size() - 1];
348 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
349 Register SrcReg = FinalCopy->getOperand(1).getReg();
350 GISelKnownBits Info(*MF);
351 KnownBits Res = Info.getKnownBits(SrcReg);
352 // Xor KnowBits does not track if we are doing xor of unknown bit with itself
353 // or negated itself.
354 // 00??1?10
355 // ^ 00?11000
356 // = 00??0?10
357 EXPECT_EQ(0x02u, Res.One.getZExtValue());
358 EXPECT_EQ(0xC9u, Res.Zero.getZExtValue());
359 }
360
361 TEST_F(AArch64GISelMITest, TestKnownBitsXORConstant) {
362 StringRef MIRString = " %3:_(s8) = G_CONSTANT i8 4\n"
363 " %4:_(s8) = G_CONSTANT i8 7\n"
364 " %5:_(s8) = G_XOR %3, %4\n"
365 " %6:_(s8) = COPY %5\n";
366 setUp(MIRString);
367 if (!TM)
368 GTEST_SKIP();
369 unsigned CopyReg = Copies[Copies.size() - 1];
370 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
371 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
372 GISelKnownBits Info(*MF);
373 KnownBits Res = Info.getKnownBits(SrcReg);
374 EXPECT_EQ(3u, Res.One.getZExtValue());
375 EXPECT_EQ(252u, Res.Zero.getZExtValue());
376 }
377
378 TEST_F(AArch64GISelMITest, TestKnownBitsASHR) {
379 StringRef MIRString = R"(
380 %ptr:_(p0) = G_IMPLICIT_DEF
381 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
382 %mask0:_(s8) = G_CONSTANT i8 38
383 %mask1:_(s8) = G_CONSTANT i8 202
384 %tmp0:_(s8) = G_AND %unknown, %mask0
385 %val0:_(s8) = G_OR %tmp0, %mask1
386 %cst0:_(s8) = G_CONSTANT i8 2
387 %ashr0:_(s8) = G_ASHR %val0, %cst0
388 %copy_ashr0:_(s8) = COPY %ashr0
389
390 %mask2:_(s8) = G_CONSTANT i8 204
391 %mask3:_(s8) = G_CONSTANT i8 18
392 %tmp1:_(s8) = G_AND %unknown, %mask2
393 %val1:_(s8) = G_OR %tmp1, %mask3
394 %ashr1:_(s8) = G_ASHR %val1, %cst0
395 %copy_ashr1:_(s8) = COPY %ashr1
396 )";
397
398 setUp(MIRString);
399 if (!TM)
400 GTEST_SKIP();
401
402 Register CopyReg0 = Copies[Copies.size() - 2];
403 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
404 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
405 GISelKnownBits Info(*MF);
406 KnownBits Res0 = Info.getKnownBits(SrcReg0);
407 // 11?01??0 >> 2
408 // = 1111?01?
409 EXPECT_EQ(0xF2u, Res0.One.getZExtValue());
410 EXPECT_EQ(0x04u, Res0.Zero.getZExtValue());
411
412 Register CopyReg1 = Copies[Copies.size() - 1];
413 MachineInstr *FinalCopy1 = MRI->getVRegDef(CopyReg1);
414 Register SrcReg1 = FinalCopy1->getOperand(1).getReg();
415 KnownBits Res1 = Info.getKnownBits(SrcReg1);
416 // ??01??10 >> 2
417 // = ????01??
418 EXPECT_EQ(0x04u, Res1.One.getZExtValue());
419 EXPECT_EQ(0x08u, Res1.Zero.getZExtValue());
420 }
421
422 TEST_F(AArch64GISelMITest, TestKnownBitsLSHR) {
423 StringRef MIRString = R"(
424 %ptr:_(p0) = G_IMPLICIT_DEF
425 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
426 %mask0:_(s8) = G_CONSTANT i8 38
427 %mask1:_(s8) = G_CONSTANT i8 202
428 %tmp0:_(s8) = G_AND %unknown, %mask0
429 %val0:_(s8) = G_OR %tmp0, %mask1
430 %cst0:_(s8) = G_CONSTANT i8 2
431 %lshr0:_(s8) = G_LSHR %val0, %cst0
432 %copy_lshr0:_(s8) = COPY %lshr0
433
434 %mask2:_(s8) = G_CONSTANT i8 204
435 %mask3:_(s8) = G_CONSTANT i8 18
436 %tmp1:_(s8) = G_AND %unknown, %mask2
437 %val1:_(s8) = G_OR %tmp1, %mask3
438 %lshr1:_(s8) = G_LSHR %val1, %cst0
439 %copy_lshr1:_(s8) = COPY %lshr1
440 )";
441
442 setUp(MIRString);
443 if (!TM)
444 GTEST_SKIP();
445
446 Register CopyReg0 = Copies[Copies.size() - 2];
447 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
448 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
449 GISelKnownBits Info(*MF);
450 KnownBits Res0 = Info.getKnownBits(SrcReg0);
451 // 11?01??0 >> 2
452 // = 0011?01?
453 EXPECT_EQ(0x32u, Res0.One.getZExtValue());
454 EXPECT_EQ(0xC4u, Res0.Zero.getZExtValue());
455
456 Register CopyReg1 = Copies[Copies.size() - 1];
457 MachineInstr *FinalCopy1 = MRI->getVRegDef(CopyReg1);
458 Register SrcReg1 = FinalCopy1->getOperand(1).getReg();
459 KnownBits Res1 = Info.getKnownBits(SrcReg1);
460 // ??01??10 >> 2
461 // = 00??01??
462 EXPECT_EQ(0x04u, Res1.One.getZExtValue());
463 EXPECT_EQ(0xC8u, Res1.Zero.getZExtValue());
464 }
465
466 TEST_F(AArch64GISelMITest, TestKnownBitsSHL) {
467 StringRef MIRString = R"(
468 %ptr:_(p0) = G_IMPLICIT_DEF
469 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
470 %mask0:_(s8) = G_CONSTANT i8 51
471 %mask1:_(s8) = G_CONSTANT i8 72
472 %tmp:_(s8) = G_AND %unknown, %mask0
473 %val:_(s8) = G_OR %tmp, %mask1
474 %cst:_(s8) = G_CONSTANT i8 3
475 %shl:_(s8) = G_SHL %val, %cst
476 %copy_shl:_(s8) = COPY %shl
477 )";
478
479 setUp(MIRString);
480 if (!TM)
481 GTEST_SKIP();
482
483 Register CopyReg = Copies[Copies.size() - 1];
484 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
485 Register SrcReg = FinalCopy->getOperand(1).getReg();
486 GISelKnownBits Info(*MF);
487 KnownBits Res = Info.getKnownBits(SrcReg);
488 // 01??10?? << 3
489 // = ?10??000
490 EXPECT_EQ(0x40u, Res.One.getZExtValue());
491 EXPECT_EQ(0x27u, Res.Zero.getZExtValue());
492 }
493
494 TEST_F(AArch64GISelMITest, TestKnownBitsADD) {
495 StringRef MIRString = R"(
496 %ptr:_(p0) = G_IMPLICIT_DEF
497 %unknown:_(s16) = G_LOAD %ptr(p0) :: (load (s16))
498 %mask0:_(s16) = G_CONSTANT i16 4642
499 %mask1:_(s16) = G_CONSTANT i16 9536
500 %tmp0:_(s16) = G_AND %unknown, %mask0
501 %val0:_(s16) = G_OR %tmp0, %mask1
502 %mask2:_(s16) = G_CONSTANT i16 4096
503 %mask3:_(s16) = G_CONSTANT i16 371
504 %tmp1:_(s16) = G_AND %unknown, %mask2
505 %val1:_(s16) = G_OR %tmp1, %mask3
506 %add:_(s16) = G_ADD %val0, %val1
507 %copy_add:_(s16) = COPY %add
508 )";
509
510 setUp(MIRString);
511 if (!TM)
512 GTEST_SKIP();
513
514 Register CopyReg = Copies[Copies.size() - 1];
515 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
516 Register SrcReg = FinalCopy->getOperand(1).getReg();
517 GISelKnownBits Info(*MF);
518 KnownBits Res = Info.getKnownBits(SrcReg);
519 // Add KnowBits works out known carry bits first and then calculates result.
520 // 001?01?101?000?0
521 // + 000?000101110011
522 // = 0??????01??10??1
523 EXPECT_EQ(0x0091u, Res.One.getZExtValue());
524 EXPECT_EQ(0x8108u, Res.Zero.getZExtValue());
525 }
526
527 TEST_F(AArch64GISelMITest, TestKnownBitsSUB) {
528 StringRef MIRString = R"(
529 %ptr:_(p0) = G_IMPLICIT_DEF
530 %unknown:_(s16) = G_LOAD %ptr(p0) :: (load (s16))
531 %mask0:_(s16) = G_CONSTANT i16 4642
532 %mask1:_(s16) = G_CONSTANT i16 9536
533 %tmp0:_(s16) = G_AND %unknown, %mask0
534 %val0:_(s16) = G_OR %tmp0, %mask1
535 %mask2:_(s16) = G_CONSTANT i16 4096
536 %mask3:_(s16) = G_CONSTANT i16 371
537 %tmp1:_(s16) = G_AND %unknown, %mask2
538 %val1:_(s16) = G_OR %tmp1, %mask3
539 %sub:_(s16) = G_SUB %val0, %val1
540 %copy_sub:_(s16) = COPY %sub
541 )";
542
543 setUp(MIRString);
544 if (!TM)
545 GTEST_SKIP();
546
547 Register CopyReg = Copies[Copies.size() - 1];
548 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
549 Register SrcReg = FinalCopy->getOperand(1).getReg();
550 GISelKnownBits Info(*MF);
551 KnownBits Res = Info.getKnownBits(SrcReg);
552 // Sub KnowBits for LHS - RHS use Add KnownBits for LHS + ~RHS + 1.
553 EXPECT_EQ(0x01CDu, Res.One.getZExtValue());
554 EXPECT_EQ(0xC810u, Res.Zero.getZExtValue());
555 }
556
557 TEST_F(AArch64GISelMITest, TestKnownBitsMUL) {
558 StringRef MIRString = R"(
559 %ptr0:_(p0) = G_IMPLICIT_DEF
560 %load0:_(s16) = G_LOAD %ptr0(p0) :: (load (s16))
561 %mask0:_(s16) = G_CONSTANT i16 4
562 %mask1:_(s16) = G_CONSTANT i16 18
563 %tmp:_(s16) = G_AND %load0, %mask0
564 %val0:_(s16) = G_OR %tmp, %mask1
565 %cst:_(s16) = G_CONSTANT i16 12
566 %mul:_(s16) = G_MUL %val0, %cst
567 %copy_mul:_(s16) = COPY %mul
568 )";
569
570 setUp(MIRString);
571 if (!TM)
572 GTEST_SKIP();
573
574 Register CopyReg = Copies[Copies.size() - 1];
575 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
576 Register SrcReg = FinalCopy->getOperand(1).getReg();
577 GISelKnownBits Info(*MF);
578 KnownBits Res = Info.getKnownBits(SrcReg);
579 // Mul KnowBits are conservatively correct, but not guaranteed to be precise.
580 // Precise for trailing bits up to the first unknown bit.
581 // 00010?10 * 00001100 =
582 // 00010?1000
583 // + 00010?10000
584 // = 0000000010??1000
585 // KB 0000000?????1000
586 EXPECT_EQ(0x0008u, Res.One.getZExtValue());
587 EXPECT_EQ(0xFE07u, Res.Zero.getZExtValue());
588 }
589
590 TEST_F(AArch64GISelMITest, TestKnownBitsICMP) {
591 StringRef MIRString = R"(
592 %cst0:_(s32) = G_CONSTANT i32 0
593 %cst1:_(s32) = G_CONSTANT i32 1
594 %icmp:_(s32) = G_ICMP intpred(ne), %cst0, %cst1
595 %copy_icmp:_(s32) = COPY %icmp
596 )";
597
598 setUp(MIRString);
599 if (!TM)
600 GTEST_SKIP();
601
602 Register CopyReg = Copies[Copies.size() - 1];
603 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
604 Register SrcReg = FinalCopy->getOperand(1).getReg();
605 GISelKnownBits Info(*MF);
606 KnownBits Res = Info.getKnownBits(SrcReg);
607 // For targets that use 0 or 1 as icmp result in large register set high bits
608 // to 0, does not analyze operands/compare predicate.
609 EXPECT_EQ(0x00000000u, Res.One.getZExtValue());
610 EXPECT_EQ(0xFFFFFFFEu, Res.Zero.getZExtValue());
611 }
612
613 TEST_F(AArch64GISelMITest, TestKnownBitsFCMP) {
614 StringRef MIRString = R"(
615 %cst0:_(s32) = G_FCONSTANT float 0.0
616 %cst1:_(s32) = G_FCONSTANT float 1.0
617 %fcmp:_(s32) = G_FCMP floatpred(one), %cst0, %cst1
618 %copy_fcmp:_(s32) = COPY %fcmp
619 )";
620
621 setUp(MIRString);
622 if (!TM)
623 GTEST_SKIP();
624
625 Register CopyReg = Copies[Copies.size() - 1];
626 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
627 Register SrcReg = FinalCopy->getOperand(1).getReg();
628 GISelKnownBits Info(*MF);
629 KnownBits Res = Info.getKnownBits(SrcReg);
630 // For targets that use 0 or 1 as fcmp result in large register set high bits
631 // to 0, does not analyze operands/compare predicate.
632 EXPECT_EQ(0x00000000u, Res.One.getZExtValue());
633 EXPECT_EQ(0xFFFFFFFEu, Res.Zero.getZExtValue());
634 }
635
636 TEST_F(AArch64GISelMITest, TestKnownBitsSelect) {
637 StringRef MIRString = R"(
638 %ptr:_(p0) = G_IMPLICIT_DEF
639 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
640 %mask0:_(s8) = G_CONSTANT i8 24
641 %mask1:_(s8) = G_CONSTANT i8 224
642 %tmp0:_(s8) = G_AND %unknown, %mask0
643 %val0:_(s8) = G_OR %tmp0, %mask1
644 %mask2:_(s8) = G_CONSTANT i8 146
645 %mask3:_(s8) = G_CONSTANT i8 36
646 %tmp1:_(s8) = G_AND %unknown, %mask2
647 %val1:_(s8) = G_OR %tmp1, %mask3
648 %cond:_(s1) = G_CONSTANT i1 false
649 %select:_(s8) = G_SELECT %cond, %val0, %val1
650 %copy_select:_(s8) = COPY %select
651 )";
652
653 setUp(MIRString);
654 if (!TM)
655 GTEST_SKIP();
656
657 Register CopyReg = Copies[Copies.size() - 1];
658 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
659 Register SrcReg = FinalCopy->getOperand(1).getReg();
660 GISelKnownBits Info(*MF);
661 KnownBits Res = Info.getKnownBits(SrcReg);
662 // Select KnownBits takes common bits of LHS and RHS, does not analyze
663 // condition operand.
664 // 111??000
665 // select ?01?01?0
666 // = ??1????0
667 EXPECT_EQ(0x20u, Res.One.getZExtValue());
668 EXPECT_EQ(0x01u, Res.Zero.getZExtValue());
669 }
670
671 TEST_F(AArch64GISelMITest, TestKnownBits) {
672
673 StringRef MIR = " %3:_(s32) = G_TRUNC %0\n"
674 " %4:_(s32) = G_TRUNC %1\n"
675 " %5:_(s32) = G_CONSTANT i32 5\n"
676 " %6:_(s32) = G_CONSTANT i32 24\n"
677 " %7:_(s32) = G_CONSTANT i32 28\n"
678 " %14:_(p0) = G_INTTOPTR %7\n"
679 " %16:_(s32) = G_PTRTOINT %14\n"
680 " %8:_(s32) = G_SHL %3, %5\n"
681 " %9:_(s32) = G_SHL %4, %5\n"
682 " %10:_(s32) = G_OR %8, %6\n"
683 " %11:_(s32) = G_OR %9, %16\n"
684 " %12:_(s32) = G_MUL %10, %11\n"
685 " %13:_(s32) = COPY %12\n";
686 setUp(MIR);
687 if (!TM)
688 GTEST_SKIP();
689 unsigned CopyReg = Copies[Copies.size() - 1];
690 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
691 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
692 GISelKnownBits Info(*MF);
693 KnownBits Known = Info.getKnownBits(SrcReg);
694 EXPECT_FALSE(Known.hasConflict());
695 EXPECT_EQ(32u, Known.One.getZExtValue());
696 EXPECT_EQ(95u, Known.Zero.getZExtValue());
697 APInt Zeroes = Info.getKnownZeroes(SrcReg);
698 EXPECT_EQ(Known.Zero, Zeroes);
699 }
700
701 TEST_F(AArch64GISelMITest, TestSignBitIsZero) {
702 setUp();
703 if (!TM)
704 GTEST_SKIP();
705
706 const LLT S32 = LLT::scalar(32);
707 auto SignBit = B.buildConstant(S32, 0x80000000);
708 auto Zero = B.buildConstant(S32, 0);
709
710 GISelKnownBits KnownBits(*MF);
711
712 EXPECT_TRUE(KnownBits.signBitIsZero(Zero.getReg(0)));
713 EXPECT_FALSE(KnownBits.signBitIsZero(SignBit.getReg(0)));
714 }
715
716 TEST_F(AArch64GISelMITest, TestNumSignBitsConstant) {
717 StringRef MIRString = " %3:_(s8) = G_CONSTANT i8 1\n"
718 " %4:_(s8) = COPY %3\n"
719
720 " %5:_(s8) = G_CONSTANT i8 -1\n"
721 " %6:_(s8) = COPY %5\n"
722
723 " %7:_(s8) = G_CONSTANT i8 127\n"
724 " %8:_(s8) = COPY %7\n"
725
726 " %9:_(s8) = G_CONSTANT i8 32\n"
727 " %10:_(s8) = COPY %9\n"
728
729 " %11:_(s8) = G_CONSTANT i8 -32\n"
730 " %12:_(s8) = COPY %11\n";
731 setUp(MIRString);
732 if (!TM)
733 GTEST_SKIP();
734 Register CopyReg1 = Copies[Copies.size() - 5];
735 Register CopyRegNeg1 = Copies[Copies.size() - 4];
736 Register CopyReg127 = Copies[Copies.size() - 3];
737 Register CopyReg32 = Copies[Copies.size() - 2];
738 Register CopyRegNeg32 = Copies[Copies.size() - 1];
739
740 GISelKnownBits Info(*MF);
741 EXPECT_EQ(7u, Info.computeNumSignBits(CopyReg1));
742 EXPECT_EQ(8u, Info.computeNumSignBits(CopyRegNeg1));
743 EXPECT_EQ(1u, Info.computeNumSignBits(CopyReg127));
744 EXPECT_EQ(2u, Info.computeNumSignBits(CopyReg32));
745 EXPECT_EQ(3u, Info.computeNumSignBits(CopyRegNeg32));
746 }
747
748 TEST_F(AArch64GISelMITest, TestNumSignBitsXOR) {
749 StringRef MIRString = " %c1:_(s8) = G_CONSTANT i8 1\n"
750 " %cn1:_(s8) = G_CONSTANT i8 -1\n"
751 " %c127:_(s8) = G_CONSTANT i8 127\n"
752 " %c32:_(s8) = G_CONSTANT i8 32\n"
753 " %cn32:_(s8) = G_CONSTANT i8 -32\n"
754
755 " %xor1:_(s8) = G_XOR %c1, %cn1\n"
756 " %Copy1:_(s8) = COPY %xor1\n"
757
758 " %xor2:_(s8) = G_XOR %c1, %c32\n"
759 " %Copy2:_(s8) = COPY %xor2\n"
760
761 " %xor3:_(s8) = G_XOR %c32, %c127\n"
762 " %Copy3:_(s8) = COPY %xor3\n"
763
764 " %xor4:_(s8) = G_XOR %cn32, %c127\n"
765 " %Copy4:_(s8) = COPY %xor4\n"
766
767 " %xor5:_(s8) = G_XOR %c127, %cn32\n"
768 " %Copy5:_(s8) = COPY %xor5\n";
769 setUp(MIRString);
770 if (!TM)
771 GTEST_SKIP();
772 Register Copy1 = Copies[Copies.size() - 5];
773 Register Copy2 = Copies[Copies.size() - 4];
774 Register Copy3 = Copies[Copies.size() - 3];
775 Register Copy4 = Copies[Copies.size() - 2];
776 Register Copy5 = Copies[Copies.size() - 1];
777
778 GISelKnownBits Info(*MF);
779 EXPECT_EQ(7u, Info.computeNumSignBits(Copy1));
780 EXPECT_EQ(2u, Info.computeNumSignBits(Copy2));
781 EXPECT_EQ(1u, Info.computeNumSignBits(Copy3));
782 EXPECT_EQ(1u, Info.computeNumSignBits(Copy4));
783 EXPECT_EQ(1u, Info.computeNumSignBits(Copy5));
784 }
785
786 TEST_F(AArch64GISelMITest, TestNumSignBitsOR) {
787 StringRef MIRString = " %c1:_(s8) = G_CONSTANT i8 1\n"
788 " %cn1:_(s8) = G_CONSTANT i8 -1\n"
789 " %c127:_(s8) = G_CONSTANT i8 127\n"
790 " %c32:_(s8) = G_CONSTANT i8 32\n"
791 " %cn32:_(s8) = G_CONSTANT i8 -32\n"
792
793 " %or1:_(s8) = G_OR %c1, %cn1\n"
794 " %Copy1:_(s8) = COPY %or1\n"
795
796 " %or2:_(s8) = G_OR %c1, %c32\n"
797 " %Copy2:_(s8) = COPY %or2\n"
798
799 " %or3:_(s8) = G_OR %c32, %c127\n"
800 " %Copy3:_(s8) = COPY %or3\n"
801
802 " %or4:_(s8) = G_OR %cn32, %c127\n"
803 " %Copy4:_(s8) = COPY %or4\n"
804
805 " %or5:_(s8) = G_OR %c127, %cn32\n"
806 " %Copy5:_(s8) = COPY %or5\n";
807 setUp(MIRString);
808 if (!TM)
809 GTEST_SKIP();
810 Register Copy1 = Copies[Copies.size() - 5];
811 Register Copy2 = Copies[Copies.size() - 4];
812 Register Copy3 = Copies[Copies.size() - 3];
813 Register Copy4 = Copies[Copies.size() - 2];
814 Register Copy5 = Copies[Copies.size() - 1];
815
816 GISelKnownBits Info(*MF);
817 EXPECT_EQ(8u, Info.computeNumSignBits(Copy1));
818 EXPECT_EQ(2u, Info.computeNumSignBits(Copy2));
819 EXPECT_EQ(1u, Info.computeNumSignBits(Copy3));
820 EXPECT_EQ(8u, Info.computeNumSignBits(Copy4));
821 EXPECT_EQ(8u, Info.computeNumSignBits(Copy5));
822 }
823
824 TEST_F(AArch64GISelMITest, TestNumSignBitsAND) {
825 StringRef MIRString = " %c1:_(s8) = G_CONSTANT i8 1\n"
826 " %cn1:_(s8) = G_CONSTANT i8 -1\n"
827 " %c127:_(s8) = G_CONSTANT i8 127\n"
828 " %c32:_(s8) = G_CONSTANT i8 32\n"
829 " %cn32:_(s8) = G_CONSTANT i8 -32\n"
830
831 " %and1:_(s8) = G_AND %c1, %cn1\n"
832 " %Copy1:_(s8) = COPY %and1\n"
833
834 " %and2:_(s8) = G_AND %c1, %c32\n"
835 " %Copy2:_(s8) = COPY %and2\n"
836
837 " %and3:_(s8) = G_AND %c32, %c127\n"
838 " %Copy3:_(s8) = COPY %and3\n"
839
840 " %and4:_(s8) = G_AND %cn32, %c127\n"
841 " %Copy4:_(s8) = COPY %and4\n"
842
843 " %and5:_(s8) = G_AND %c127, %cn32\n"
844 " %Copy5:_(s8) = COPY %and5\n";
845 setUp(MIRString);
846 if (!TM)
847 GTEST_SKIP();
848 Register Copy1 = Copies[Copies.size() - 5];
849 Register Copy2 = Copies[Copies.size() - 4];
850 Register Copy3 = Copies[Copies.size() - 3];
851 Register Copy4 = Copies[Copies.size() - 2];
852 Register Copy5 = Copies[Copies.size() - 1];
853
854 GISelKnownBits Info(*MF);
855 EXPECT_EQ(7u, Info.computeNumSignBits(Copy1));
856 EXPECT_EQ(8u, Info.computeNumSignBits(Copy2));
857 EXPECT_EQ(2u, Info.computeNumSignBits(Copy3));
858 EXPECT_EQ(1u, Info.computeNumSignBits(Copy4));
859 EXPECT_EQ(1u, Info.computeNumSignBits(Copy5));
860 }
861
862 TEST_F(AArch64GISelMITest, TestNumSignBitsSext) {
863 StringRef MIRString = " %3:_(p0) = G_IMPLICIT_DEF\n"
864 " %4:_(s8) = G_LOAD %3 :: (load (s8))\n"
865 " %5:_(s32) = G_SEXT %4\n"
866 " %6:_(s32) = COPY %5\n"
867
868 " %7:_(s8) = G_CONSTANT i8 -1\n"
869 " %8:_(s32) = G_SEXT %7\n"
870 " %9:_(s32) = COPY %8\n";
871 setUp(MIRString);
872 if (!TM)
873 GTEST_SKIP();
874 Register CopySextLoad = Copies[Copies.size() - 2];
875 Register CopySextNeg1 = Copies[Copies.size() - 1];
876
877 GISelKnownBits Info(*MF);
878 EXPECT_EQ(25u, Info.computeNumSignBits(CopySextLoad));
879 EXPECT_EQ(32u, Info.computeNumSignBits(CopySextNeg1));
880 }
881
882 TEST_F(AArch64GISelMITest, TestNumSignBitsSextInReg) {
883 StringRef MIRString = R"(
884 %ptr:_(p0) = G_IMPLICIT_DEF
885 %load4:_(s32) = G_LOAD %ptr :: (load (s32))
886
887 %inreg7:_(s32) = G_SEXT_INREG %load4, 7
888 %copy_inreg7:_(s32) = COPY %inreg7
889
890 %inreg8:_(s32) = G_SEXT_INREG %load4, 8
891 %copy_inreg8:_(s32) = COPY %inreg8
892
893 %inreg9:_(s32) = G_SEXT_INREG %load4, 9
894 %copy_inreg9:_(s32) = COPY %inreg9
895
896 %inreg31:_(s32) = G_SEXT_INREG %load4, 31
897 %copy_inreg31:_(s32) = COPY %inreg31
898
899 %load1:_(s8) = G_LOAD %ptr :: (load (s8))
900 %sext_load1:_(s32) = G_SEXT %load1
901
902 %inreg6_sext:_(s32) = G_SEXT_INREG %sext_load1, 6
903 %copy_inreg6_sext:_(s32) = COPY %inreg6_sext
904
905 %inreg7_sext:_(s32) = G_SEXT_INREG %sext_load1, 7
906 %copy_inreg7_sext:_(s32) = COPY %inreg7_sext
907
908 %inreg8_sext:_(s32) = G_SEXT_INREG %sext_load1, 8
909 %copy_inreg8_sext:_(s32) = COPY %inreg8_sext
910
911 %inreg9_sext:_(s32) = G_SEXT_INREG %sext_load1, 9
912 %copy_inreg9_sext:_(s32) = COPY %inreg9_sext
913
914 %inreg31_sext:_(s32) = G_SEXT_INREG %sext_load1, 31
915 %copy_inreg31_sext:_(s32) = COPY %inreg31_sext
916 )";
917
918 setUp(MIRString);
919 if (!TM)
920 GTEST_SKIP();
921
922 Register CopyInReg7 = Copies[Copies.size() - 9];
923 Register CopyInReg8 = Copies[Copies.size() - 8];
924 Register CopyInReg9 = Copies[Copies.size() - 7];
925 Register CopyInReg31 = Copies[Copies.size() - 6];
926
927 Register CopyInReg6Sext = Copies[Copies.size() - 5];
928 Register CopyInReg7Sext = Copies[Copies.size() - 4];
929 Register CopyInReg8Sext = Copies[Copies.size() - 3];
930 Register CopyInReg9Sext = Copies[Copies.size() - 2];
931 Register CopyInReg31Sext = Copies[Copies.size() - 1];
932
933 GISelKnownBits Info(*MF);
934 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7));
935 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8));
936 EXPECT_EQ(24u, Info.computeNumSignBits(CopyInReg9));
937 EXPECT_EQ(2u, Info.computeNumSignBits(CopyInReg31));
938
939 EXPECT_EQ(27u, Info.computeNumSignBits(CopyInReg6Sext));
940 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7Sext));
941 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8Sext));
942 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg9Sext));
943 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg31Sext));
944 }
945
946 TEST_F(AArch64GISelMITest, TestNumSignBitsAssertSext) {
947 StringRef MIRString = R"(
948 %ptr:_(p0) = G_IMPLICIT_DEF
949 %load4:_(s32) = G_LOAD %ptr :: (load (s32))
950
951 %assert_sext1:_(s32) = G_ASSERT_SEXT %load4, 1
952 %copy_assert_sext1:_(s32) = COPY %assert_sext1
953
954 %assert_sext7:_(s32) = G_ASSERT_SEXT %load4, 7
955 %copy_assert_sext7:_(s32) = COPY %assert_sext7
956
957 %assert_sext8:_(s32) = G_ASSERT_SEXT %load4, 8
958 %copy_assert_sext8:_(s32) = COPY %assert_sext8
959
960 %assert_sext9:_(s32) = G_ASSERT_SEXT %load4, 9
961 %copy_assert_sext9:_(s32) = COPY %assert_sext9
962
963 %assert_sext31:_(s32) = G_ASSERT_SEXT %load4, 31
964 %copy_assert_sext31:_(s32) = COPY %assert_sext31
965
966 %load1:_(s8) = G_LOAD %ptr :: (load (s8))
967 %sext_load1:_(s32) = G_SEXT %load1
968
969 %assert_sext6_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 6
970 %copy_assert_sext6_sext:_(s32) = COPY %assert_sext6_sext
971
972 %assert_sext7_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 7
973 %copy_assert_sext7_sext:_(s32) = COPY %assert_sext7_sext
974
975 %assert_sext8_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 8
976 %copy_assert_sext8_sext:_(s32) = COPY %assert_sext8_sext
977
978 %assert_sext9_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 9
979 %copy_assert_sext9_sext:_(s32) = COPY %assert_sext9_sext
980
981 %assert_sext31_sext:_(s32) = G_ASSERT_SEXT %sext_load1, 31
982 %copy_assert_sext31_sext:_(s32) = COPY %assert_sext31_sext
983 )";
984
985 setUp(MIRString);
986 if (!TM)
987 GTEST_SKIP();
988
989 Register CopyInReg1 = Copies[Copies.size() - 10];
990 Register CopyInReg7 = Copies[Copies.size() - 9];
991 Register CopyInReg8 = Copies[Copies.size() - 8];
992 Register CopyInReg9 = Copies[Copies.size() - 7];
993 Register CopyInReg31 = Copies[Copies.size() - 6];
994
995 Register CopyInReg6Sext = Copies[Copies.size() - 5];
996 Register CopyInReg7Sext = Copies[Copies.size() - 4];
997 Register CopyInReg8Sext = Copies[Copies.size() - 3];
998 Register CopyInReg9Sext = Copies[Copies.size() - 2];
999 Register CopyInReg31Sext = Copies[Copies.size() - 1];
1000
1001 GISelKnownBits Info(*MF);
1002 EXPECT_EQ(32u, Info.computeNumSignBits(CopyInReg1));
1003 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7));
1004 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8));
1005 EXPECT_EQ(24u, Info.computeNumSignBits(CopyInReg9));
1006 EXPECT_EQ(2u, Info.computeNumSignBits(CopyInReg31));
1007
1008 EXPECT_EQ(27u, Info.computeNumSignBits(CopyInReg6Sext));
1009 EXPECT_EQ(26u, Info.computeNumSignBits(CopyInReg7Sext));
1010 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg8Sext));
1011 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg9Sext));
1012 EXPECT_EQ(25u, Info.computeNumSignBits(CopyInReg31Sext));
1013 }
1014
1015 TEST_F(AArch64GISelMITest, TestNumSignBitsTrunc) {
1016 StringRef MIRString = " %3:_(p0) = G_IMPLICIT_DEF\n"
1017 " %4:_(s32) = G_LOAD %3 :: (load (s32))\n"
1018 " %5:_(s8) = G_TRUNC %4\n"
1019 " %6:_(s8) = COPY %5\n"
1020
1021 " %7:_(s32) = G_CONSTANT i32 -1\n"
1022 " %8:_(s8) = G_TRUNC %7\n"
1023 " %9:_(s8) = COPY %8\n"
1024
1025 " %10:_(s32) = G_CONSTANT i32 7\n"
1026 " %11:_(s8) = G_TRUNC %10\n"
1027 " %12:_(s8) = COPY %11\n";
1028 setUp(MIRString);
1029 if (!TM)
1030 GTEST_SKIP();
1031 Register CopyTruncLoad = Copies[Copies.size() - 3];
1032 Register CopyTruncNeg1 = Copies[Copies.size() - 2];
1033 Register CopyTrunc7 = Copies[Copies.size() - 1];
1034
1035 GISelKnownBits Info(*MF);
1036 EXPECT_EQ(1u, Info.computeNumSignBits(CopyTruncLoad));
1037 EXPECT_EQ(8u, Info.computeNumSignBits(CopyTruncNeg1));
1038 EXPECT_EQ(5u, Info.computeNumSignBits(CopyTrunc7));
1039 }
1040
1041 TEST_F(AArch64GISelMITest, TestNumSignBitsCmp) {
1042 StringRef MIRString =
1043 " %v1:_(<4 x s32>) = G_IMPLICIT_DEF\n"
1044 " %v2:_(<4 x s32>) = G_IMPLICIT_DEF\n"
1045 " %s1:_(s64) = G_IMPLICIT_DEF\n"
1046 " %s2:_(s64) = G_IMPLICIT_DEF\n"
1047 " %cmp:_(<4 x s32>) = G_FCMP floatpred(ogt), %v1, %v2\n"
1048 " %cpy1:_(<4 x s32>) = COPY %cmp\n"
1049 " %cmp2:_(<4 x s32>) = G_ICMP intpred(eq), %v1, %v2\n"
1050 " %cpy2:_(<4 x s32>) = COPY %cmp2\n"
1051 " %cmp3:_(s32) = G_FCMP floatpred(ogt), %s1, %s2\n"
1052 " %cpy3:_(s32) = COPY %cmp3\n"
1053 " %cmp4:_(s32) = G_ICMP intpred(eq), %s1, %s2\n"
1054 " %cpy4:_(s32) = COPY %cmp4\n";
1055
1056 setUp(MIRString);
1057 if (!TM)
1058 GTEST_SKIP();
1059 Register CopyVecFCMP = Copies[Copies.size() - 4];
1060 Register CopyVecICMP = Copies[Copies.size() - 3];
1061 Register CopyScalarFCMP = Copies[Copies.size() - 2];
1062 Register CopyScalarICMP = Copies[Copies.size() - 1];
1063
1064 GISelKnownBits Info(*MF);
1065 EXPECT_EQ(32u, Info.computeNumSignBits(CopyVecFCMP));
1066 EXPECT_EQ(32u, Info.computeNumSignBits(CopyVecICMP));
1067 EXPECT_EQ(31u, Info.computeNumSignBits(CopyScalarFCMP));
1068 EXPECT_EQ(31u, Info.computeNumSignBits(CopyScalarICMP));
1069 }
1070
1071 TEST_F(AMDGPUGISelMITest, TestNumSignBitsTrunc) {
1072 StringRef MIRString =
1073 " %3:_(<4 x s32>) = G_IMPLICIT_DEF\n"
1074 " %4:_(s32) = G_IMPLICIT_DEF\n"
1075 " %5:_(s32) = G_AMDGPU_BUFFER_LOAD_UBYTE %3, %4, %4, %4, 0, 0, 0 :: (load (s8))\n"
1076 " %6:_(s32) = COPY %5\n"
1077
1078 " %7:_(s32) = G_AMDGPU_BUFFER_LOAD_SBYTE %3, %4, %4, %4, 0, 0, 0 :: (load (s8))\n"
1079 " %8:_(s32) = COPY %7\n"
1080
1081 " %9:_(s32) = G_AMDGPU_BUFFER_LOAD_USHORT %3, %4, %4, %4, 0, 0, 0 :: (load (s16))\n"
1082 " %10:_(s32) = COPY %9\n"
1083
1084 " %11:_(s32) = G_AMDGPU_BUFFER_LOAD_SSHORT %3, %4, %4, %4, 0, 0, 0 :: (load (s16))\n"
1085 " %12:_(s32) = COPY %11\n";
1086
1087 setUp(MIRString);
1088 if (!TM)
1089 GTEST_SKIP();
1090
1091 Register CopyLoadUByte = Copies[Copies.size() - 4];
1092 Register CopyLoadSByte = Copies[Copies.size() - 3];
1093 Register CopyLoadUShort = Copies[Copies.size() - 2];
1094 Register CopyLoadSShort = Copies[Copies.size() - 1];
1095
1096 GISelKnownBits Info(*MF);
1097
1098 EXPECT_EQ(24u, Info.computeNumSignBits(CopyLoadUByte));
1099 EXPECT_EQ(25u, Info.computeNumSignBits(CopyLoadSByte));
1100 EXPECT_EQ(16u, Info.computeNumSignBits(CopyLoadUShort));
1101 EXPECT_EQ(17u, Info.computeNumSignBits(CopyLoadSShort));
1102 }
1103
1104 TEST_F(AMDGPUGISelMITest, TestTargetKnownAlign) {
1105 StringRef MIRString =
1106 " %5:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.dispatch.ptr)\n"
1107 " %6:_(p4) = COPY %5\n"
1108 " %7:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.queue.ptr)\n"
1109 " %8:_(p4) = COPY %7\n"
1110 " %9:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)\n"
1111 " %10:_(p4) = COPY %9\n"
1112 " %11:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.implicitarg.ptr)\n"
1113 " %12:_(p4) = COPY %11\n"
1114 " %13:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.implicit.buffer.ptr)\n"
1115 " %14:_(p4) = COPY %13\n";
1116
1117 setUp(MIRString);
1118 if (!TM)
1119 GTEST_SKIP();
1120
1121 Register CopyDispatchPtr = Copies[Copies.size() - 5];
1122 Register CopyQueuePtr = Copies[Copies.size() - 4];
1123 Register CopyKernargSegmentPtr = Copies[Copies.size() - 3];
1124 Register CopyImplicitArgPtr = Copies[Copies.size() - 2];
1125 Register CopyImplicitBufferPtr = Copies[Copies.size() - 1];
1126
1127 GISelKnownBits Info(*MF);
1128
1129 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyDispatchPtr));
1130 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyQueuePtr));
1131 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyKernargSegmentPtr));
1132 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyImplicitArgPtr));
1133 EXPECT_EQ(Align(4), Info.computeKnownAlignment(CopyImplicitBufferPtr));
1134 }
1135
1136 TEST_F(AMDGPUGISelMITest, TestIsKnownToBeAPowerOfTwo) {
1137
1138 StringRef MIRString = R"MIR(
1139 %zero:_(s32) = G_CONSTANT i32 0
1140 %one:_(s32) = G_CONSTANT i32 1
1141 %two:_(s32) = G_CONSTANT i32 2
1142 %three:_(s32) = G_CONSTANT i32 3
1143 %five:_(s32) = G_CONSTANT i32 5
1144 %copy_zero:_(s32) = COPY %zero
1145 %copy_one:_(s32) = COPY %one
1146 %copy_two:_(s32) = COPY %two
1147 %copy_three:_(s32) = COPY %three
1148
1149 %trunc_two:_(s1) = G_TRUNC %two
1150 %trunc_three:_(s1) = G_TRUNC %three
1151 %trunc_five:_(s1) = G_TRUNC %five
1152
1153 %copy_trunc_two:_(s1) = COPY %trunc_two
1154 %copy_trunc_three:_(s1) = COPY %trunc_three
1155 %copy_trunc_five:_(s1) = COPY %trunc_five
1156
1157 %ptr:_(p1) = G_IMPLICIT_DEF
1158 %shift_amt:_(s32) = G_LOAD %ptr :: (load (s32), addrspace 1)
1159
1160 %shl_1:_(s32) = G_SHL %one, %shift_amt
1161 %copy_shl_1:_(s32) = COPY %shl_1
1162
1163 %shl_2:_(s32) = G_SHL %two, %shift_amt
1164 %copy_shl_2:_(s32) = COPY %shl_2
1165
1166 %not_sign_mask:_(s32) = G_LOAD %ptr :: (load (s32), addrspace 1)
1167 %sign_mask:_(s32) = G_CONSTANT i32 -2147483648
1168
1169 %lshr_not_sign_mask:_(s32) = G_LSHR %not_sign_mask, %shift_amt
1170 %copy_lshr_not_sign_mask:_(s32) = COPY %lshr_not_sign_mask
1171
1172 %lshr_sign_mask:_(s32) = G_LSHR %sign_mask, %shift_amt
1173 %copy_lshr_sign_mask:_(s32) = COPY %lshr_sign_mask
1174
1175 %or_pow2:_(s32) = G_OR %zero, %two
1176 %copy_or_pow2:_(s32) = COPY %or_pow2
1177
1178 )MIR";
1179 setUp(MIRString);
1180 if (!TM)
1181 GTEST_SKIP();
1182
1183 GISelKnownBits KB(*MF);
1184
1185 Register CopyZero = Copies[Copies.size() - 12];
1186 Register CopyOne = Copies[Copies.size() - 11];
1187 Register CopyTwo = Copies[Copies.size() - 10];
1188 Register CopyThree = Copies[Copies.size() - 9];
1189 Register CopyTruncTwo = Copies[Copies.size() - 8];
1190 Register CopyTruncThree = Copies[Copies.size() - 7];
1191 Register CopyTruncFive = Copies[Copies.size() - 6];
1192
1193 Register CopyShl1 = Copies[Copies.size() - 5];
1194 Register CopyShl2 = Copies[Copies.size() - 4];
1195
1196 Register CopyLShrNotSignMask = Copies[Copies.size() - 3];
1197 Register CopyLShrSignMask = Copies[Copies.size() - 2];
1198 Register CopyOrPow2 = Copies[Copies.size() - 1];
1199
1200 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyZero, *MRI, &KB));
1201 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyOne, *MRI, &KB));
1202 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTwo, *MRI, &KB));
1203 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyThree, *MRI, &KB));
1204
1205 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyTruncTwo, *MRI, &KB));
1206 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTruncThree, *MRI, &KB));
1207 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyTruncFive, *MRI, &KB));
1208
1209 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyShl1, *MRI, &KB));
1210 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyShl2, *MRI, &KB));
1211
1212 EXPECT_FALSE(isKnownToBeAPowerOfTwo(CopyLShrNotSignMask, *MRI, &KB));
1213 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyLShrSignMask, *MRI, &KB));
1214 EXPECT_TRUE(isKnownToBeAPowerOfTwo(CopyOrPow2, *MRI, &KB));
1215 }
1216
1217 static void AddRangeMetadata(LLVMContext &Context, MachineInstr *Load) {
1218 IntegerType *Int8Ty = Type::getInt8Ty(Context);
1219
1220 // Value must be in [0, 2)
1221 Metadata *LowAndHigh[] = {
1222 ConstantAsMetadata::get(ConstantInt::get(Int8Ty, 0)),
1223 ConstantAsMetadata::get(ConstantInt::get(Int8Ty, 2))};
1224 auto NewMDNode = MDNode::get(Context, LowAndHigh);
1225 const MachineMemOperand *OldMMO = *Load->memoperands_begin();
1226 MachineMemOperand *NewMMO =
1227 Load->getParent()->getParent()->getMachineMemOperand(
1228 OldMMO->getPointerInfo(), OldMMO->getFlags(), OldMMO->getMemoryType(),
1229 OldMMO->getAlign(), OldMMO->getAAInfo(), NewMDNode);
1230 MachineIRBuilder MIB(*Load);
1231 MIB.buildLoadInstr(Load->getOpcode(), Load->getOperand(0),
1232 Load->getOperand(1), *NewMMO);
1233 Load->eraseFromParent();
1234 }
1235
1236 TEST_F(AArch64GISelMITest, TestMetadata) {
1237 StringRef MIRString = " %imp:_(p0) = G_IMPLICIT_DEF\n"
1238 " %load:_(s8) = G_LOAD %imp(p0) :: (load (s8))\n"
1239 " %ext:_(s32) = G_ZEXT %load(s8)\n"
1240 " %cst:_(s32) = G_CONSTANT i32 1\n"
1241 " %and:_(s32) = G_AND %ext, %cst\n"
1242 " %copy:_(s32) = COPY %and(s32)\n";
1243 setUp(MIRString);
1244 if (!TM)
1245 GTEST_SKIP();
1246
1247 Register CopyReg = Copies[Copies.size() - 1];
1248 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
1249 Register SrcReg = FinalCopy->getOperand(1).getReg();
1250
1251 // We need a load with a metadata range for this to break. Fudge the load in
1252 // the string and replace it with something we can work with.
1253 MachineInstr *And = MRI->getVRegDef(SrcReg);
1254 MachineInstr *Ext = MRI->getVRegDef(And->getOperand(1).getReg());
1255 MachineInstr *Load = MRI->getVRegDef(Ext->getOperand(1).getReg());
1256 AddRangeMetadata(Context, Load);
1257
1258 GISelKnownBits Info(*MF);
1259 KnownBits Res = Info.getKnownBits(And->getOperand(1).getReg());
1260
1261 // We don't know what the result of the load is, so we don't know any ones.
1262 EXPECT_TRUE(Res.One.isZero());
1263
1264 // We know that the value is in [0, 2). So, we don't know if the first bit
1265 // is 0 or not. However, we do know that every other bit must be 0.
1266 APInt Mask(Res.getBitWidth(), 1);
1267 Mask.flipAllBits();
1268 EXPECT_EQ(Mask.getZExtValue(), Res.Zero.getZExtValue());
1269 }
1270
1271 TEST_F(AArch64GISelMITest, TestMetadataExt) {
1272 StringRef MIRString = " %imp:_(p0) = G_IMPLICIT_DEF\n"
1273 " %load:_(s32) = G_LOAD %imp(p0) :: (load (s8))\n"
1274 " %copy:_(s32) = COPY %load(s32)\n";
1275 setUp(MIRString);
1276 if (!TM)
1277 GTEST_SKIP();
1278
1279 Register CopyReg = Copies[Copies.size() - 1];
1280 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
1281 Register SrcReg = FinalCopy->getOperand(1).getReg();
1282 MachineInstr *Load = MRI->getVRegDef(SrcReg);
1283 AddRangeMetadata(Context, Load);
1284
1285 GISelKnownBits Info(*MF);
1286 KnownBits Res = Info.getKnownBits(SrcReg);
1287 EXPECT_TRUE(Res.One.isZero());
1288 EXPECT_EQ(Res.Zero.getZExtValue(), 0xfeu);
1289 }
1290
1291 TEST_F(AArch64GISelMITest, TestMetadataZExt) {
1292 StringRef MIRString = " %imp:_(p0) = G_IMPLICIT_DEF\n"
1293 " %load:_(s32) = G_ZEXTLOAD %imp(p0) :: (load (s8))\n"
1294 " %copy:_(s32) = COPY %load(s32)\n";
1295 setUp(MIRString);
1296 if (!TM)
1297 GTEST_SKIP();
1298
1299 Register CopyReg = Copies[Copies.size() - 1];
1300 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
1301 Register SrcReg = FinalCopy->getOperand(1).getReg();
1302 MachineInstr *Load = MRI->getVRegDef(SrcReg);
1303 AddRangeMetadata(Context, Load);
1304
1305 GISelKnownBits Info(*MF);
1306 KnownBits Res = Info.getKnownBits(SrcReg);
1307 EXPECT_TRUE(Res.One.isZero());
1308 EXPECT_EQ(Res.Zero.getZExtValue(), 0xfffffffe);
1309 }
1310
1311 TEST_F(AArch64GISelMITest, TestMetadataSExt) {
1312 StringRef MIRString = " %imp:_(p0) = G_IMPLICIT_DEF\n"
1313 " %load:_(s32) = G_SEXTLOAD %imp(p0) :: (load (s8))\n"
1314 " %copy:_(s32) = COPY %load(s32)\n";
1315 setUp(MIRString);
1316 if (!TM)
1317 GTEST_SKIP();
1318
1319 Register CopyReg = Copies[Copies.size() - 1];
1320 MachineInstr *FinalCopy = MRI->getVRegDef(CopyReg);
1321 Register SrcReg = FinalCopy->getOperand(1).getReg();
1322 MachineInstr *Load = MRI->getVRegDef(SrcReg);
1323 AddRangeMetadata(Context, Load);
1324
1325 GISelKnownBits Info(*MF);
1326 KnownBits Res = Info.getKnownBits(SrcReg);
1327 EXPECT_TRUE(Res.One.isZero());
1328 EXPECT_EQ(Res.Zero.getZExtValue(), 0xfffffffe);
1329 }
1330
1331 TEST_F(AArch64GISelMITest, TestKnownBitsExt) {
1332 StringRef MIRString = " %c1:_(s16) = G_CONSTANT i16 1\n"
1333 " %x:_(s16) = G_IMPLICIT_DEF\n"
1334 " %y:_(s16) = G_AND %x, %c1\n"
1335 " %anyext:_(s32) = G_ANYEXT %y(s16)\n"
1336 " %r1:_(s32) = COPY %anyext\n"
1337 " %zext:_(s32) = G_ZEXT %y(s16)\n"
1338 " %r2:_(s32) = COPY %zext\n"
1339 " %sext:_(s32) = G_SEXT %y(s16)\n"
1340 " %r3:_(s32) = COPY %sext\n";
1341 setUp(MIRString);
1342 if (!TM)
1343 GTEST_SKIP();
1344 Register CopyRegAny = Copies[Copies.size() - 3];
1345 Register CopyRegZ = Copies[Copies.size() - 2];
1346 Register CopyRegS = Copies[Copies.size() - 1];
1347
1348 GISelKnownBits Info(*MF);
1349 MachineInstr *Copy;
1350 Register SrcReg;
1351 KnownBits Res;
1352
1353 Copy = MRI->getVRegDef(CopyRegAny);
1354 SrcReg = Copy->getOperand(1).getReg();
1355 Res = Info.getKnownBits(SrcReg);
1356 EXPECT_EQ((uint64_t)32, Res.getBitWidth());
1357 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
1358 EXPECT_EQ((uint64_t)0x0000fffe, Res.Zero.getZExtValue());
1359
1360 Copy = MRI->getVRegDef(CopyRegZ);
1361 SrcReg = Copy->getOperand(1).getReg();
1362 Res = Info.getKnownBits(SrcReg);
1363 EXPECT_EQ((uint64_t)32, Res.getBitWidth());
1364 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
1365 EXPECT_EQ((uint64_t)0xfffffffe, Res.Zero.getZExtValue());
1366
1367 Copy = MRI->getVRegDef(CopyRegS);
1368 SrcReg = Copy->getOperand(1).getReg();
1369 Res = Info.getKnownBits(SrcReg);
1370 EXPECT_EQ((uint64_t)32, Res.getBitWidth());
1371 EXPECT_EQ((uint64_t)0, Res.One.getZExtValue());
1372 EXPECT_EQ((uint64_t)0xfffffffe, Res.Zero.getZExtValue());
1373 }
1374
1375 TEST_F(AArch64GISelMITest, TestKnownBitsSextInReg) {
1376 StringRef MIRString = R"(
1377 ; 000...0001
1378 %one:_(s32) = G_CONSTANT i32 1
1379
1380 ; 000...0010
1381 %two:_(s32) = G_CONSTANT i32 2
1382
1383 ; 000...1010
1384 %ten:_(s32) = G_CONSTANT i32 10
1385
1386 ; ???...????
1387 %w0:_(s32) = COPY $w0
1388
1389 ; ???...?1?
1390 %or:_(s32) = G_OR %w0, %two
1391
1392 ; All bits are known.
1393 %inreg1:_(s32) = G_SEXT_INREG %one, 1
1394 %copy_inreg1:_(s32) = COPY %inreg1
1395
1396 ; All bits unknown
1397 %inreg2:_(s32) = G_SEXT_INREG %or, 1
1398 %copy_inreg2:_(s32) = COPY %inreg2
1399
1400 ; Extending from the only (known) set bit
1401 ; 111...11?
1402 %inreg3:_(s32) = G_SEXT_INREG %or, 2
1403 %copy_inreg3:_(s32) = COPY %inreg3
1404
1405 ; Extending from a known set bit, overwriting all of the high set bits.
1406 ; 111...1110
1407 %inreg4:_(s32) = G_SEXT_INREG %ten, 2
1408 %copy_inreg4:_(s32) = COPY %inreg4
1409
1410 )";
1411 setUp(MIRString);
1412 if (!TM)
1413 GTEST_SKIP();
1414 GISelKnownBits Info(*MF);
1415 KnownBits Res;
1416 auto GetKB = [&](unsigned Idx) {
1417 Register CopyReg = Copies[Idx];
1418 auto *Copy = MRI->getVRegDef(CopyReg);
1419 return Info.getKnownBits(Copy->getOperand(1).getReg());
1420 };
1421
1422 // Every bit is known to be a 1.
1423 Res = GetKB(Copies.size() - 4);
1424 EXPECT_EQ(32u, Res.getBitWidth());
1425 EXPECT_TRUE(Res.isAllOnes());
1426
1427 // All bits are unknown
1428 Res = GetKB(Copies.size() - 3);
1429 EXPECT_EQ(32u, Res.getBitWidth());
1430 EXPECT_TRUE(Res.isUnknown());
1431
1432 // Extending from the only known set bit
1433 // 111...11?
1434 Res = GetKB(Copies.size() - 2);
1435 EXPECT_EQ(32u, Res.getBitWidth());
1436 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());
1437 EXPECT_EQ(0u, Res.Zero.getZExtValue());
1438
1439 // Extending from a known set bit, overwriting all of the high set bits.
1440 // 111...1110
1441 Res = GetKB(Copies.size() - 1);
1442 EXPECT_EQ(32u, Res.getBitWidth());
1443 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());
1444 EXPECT_EQ(1u, Res.Zero.getZExtValue());
1445 }
1446
1447 TEST_F(AArch64GISelMITest, TestKnownBitsAssertSext) {
1448 StringRef MIRString = R"(
1449 ; 000...0001
1450 %one:_(s32) = G_CONSTANT i32 1
1451
1452 ; 000...0010
1453 %two:_(s32) = G_CONSTANT i32 2
1454
1455 ; 000...1010
1456 %ten:_(s32) = G_CONSTANT i32 10
1457
1458 ; ???...????
1459 %w0:_(s32) = COPY $w0
1460
1461 ; ???...?1?
1462 %or:_(s32) = G_OR %w0, %two
1463
1464 ; All bits are known.
1465 %assert_sext1:_(s32) = G_ASSERT_SEXT %one, 1
1466 %copy_assert_sext1:_(s32) = COPY %assert_sext1
1467
1468 ; All bits unknown
1469 %assert_sext2:_(s32) = G_ASSERT_SEXT %or, 1
1470 %copy_assert_sext2:_(s32) = COPY %assert_sext2
1471
1472 ; Extending from the only (known) set bit
1473 ; 111...11?
1474 %assert_sext3:_(s32) = G_ASSERT_SEXT %or, 2
1475 %copy_assert_sext3:_(s32) = COPY %assert_sext3
1476
1477 ; Extending from a known set bit, overwriting all of the high set bits.
1478 ; 111...1110
1479 %assert_sext4:_(s32) = G_ASSERT_SEXT %ten, 2
1480 %copy_assert_sext4:_(s32) = COPY %assert_sext4
1481 )";
1482 setUp(MIRString);
1483 if (!TM)
1484 GTEST_SKIP();
1485 GISelKnownBits Info(*MF);
1486 KnownBits Res;
1487 auto GetKB = [&](unsigned Idx) {
1488 Register CopyReg = Copies[Idx];
1489 auto *Copy = MRI->getVRegDef(CopyReg);
1490 return Info.getKnownBits(Copy->getOperand(1).getReg());
1491 };
1492
1493 // Every bit is known to be a 1.
1494 Res = GetKB(Copies.size() - 4);
1495 EXPECT_EQ(32u, Res.getBitWidth());
1496 EXPECT_TRUE(Res.isAllOnes());
1497
1498 // All bits are unknown
1499 Res = GetKB(Copies.size() - 3);
1500 EXPECT_EQ(32u, Res.getBitWidth());
1501 EXPECT_TRUE(Res.isUnknown());
1502
1503 // Extending from the only known set bit
1504 // 111...11?
1505 Res = GetKB(Copies.size() - 2);
1506 EXPECT_EQ(32u, Res.getBitWidth());
1507 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());
1508 EXPECT_EQ(0u, Res.Zero.getZExtValue());
1509
1510 // Extending from a known set bit, overwriting all of the high set bits.
1511 // 111...1110
1512 Res = GetKB(Copies.size() - 1);
1513 EXPECT_EQ(32u, Res.getBitWidth());
1514 EXPECT_EQ(0xFFFFFFFEu, Res.One.getZExtValue());
1515 EXPECT_EQ(1u, Res.Zero.getZExtValue());
1516 }
1517
1518 TEST_F(AArch64GISelMITest, TestKnownBitsMergeValues) {
1519 StringRef MIRString = R"(
1520 %val0:_(s16) = G_CONSTANT i16 35224
1521 %val1:_(s16) = G_CONSTANT i16 17494
1522 %val2:_(s16) = G_CONSTANT i16 4659
1523 %val3:_(s16) = G_CONSTANT i16 43981
1524 %merge:_(s64) = G_MERGE_VALUES %val0, %val1, %val2, %val3
1525 %mergecopy:_(s64) = COPY %merge
1526 )";
1527 setUp(MIRString);
1528 if (!TM)
1529 GTEST_SKIP();
1530
1531 const uint64_t TestVal = UINT64_C(0xabcd123344568998);
1532 Register CopyMerge = Copies[Copies.size() - 1];
1533
1534 GISelKnownBits Info(*MF);
1535 KnownBits Res = Info.getKnownBits(CopyMerge);
1536 EXPECT_EQ(64u, Res.getBitWidth());
1537 EXPECT_EQ(TestVal, Res.One.getZExtValue());
1538 EXPECT_EQ(~TestVal, Res.Zero.getZExtValue());
1539 }
1540
1541 TEST_F(AArch64GISelMITest, TestKnownBitsUnmergeValues) {
1542 StringRef MIRString = R"(
1543 %val:_(s64) = G_CONSTANT i64 12379570962110515608
1544 %val0:_(s16), %val1:_(s16), %val2:_(s16), %val3:_(s16) = G_UNMERGE_VALUES %val
1545 %part0:_(s16) = COPY %val0
1546 %part1:_(s16) = COPY %val1
1547 %part2:_(s16) = COPY %val2
1548 %part3:_(s16) = COPY %val3
1549
1550 )";
1551 setUp(MIRString);
1552 if (!TM)
1553 GTEST_SKIP();
1554
1555 const uint64_t TestVal = UINT64_C(0xabcd123344568998);
1556 GISelKnownBits Info(*MF);
1557
1558 int Offset = -4;
1559 for (unsigned BitOffset = 0; BitOffset != 64; BitOffset += 16, ++Offset) {
1560 Register Part = Copies[Copies.size() + Offset];
1561 KnownBits PartKnown = Info.getKnownBits(Part);
1562 EXPECT_EQ(16u, PartKnown.getBitWidth());
1563
1564 uint16_t PartTestVal = static_cast<uint16_t>(TestVal >> BitOffset);
1565 EXPECT_EQ(PartTestVal, PartKnown.One.getZExtValue());
1566 EXPECT_EQ(static_cast<uint16_t>(~PartTestVal), PartKnown.Zero.getZExtValue());
1567 }
1568 }
1569
1570 TEST_F(AArch64GISelMITest, TestKnownBitsBSwapBitReverse) {
1571 StringRef MIRString = R"(
1572 %const:_(s32) = G_CONSTANT i32 287454020
1573 %bswap:_(s32) = G_BSWAP %const
1574 %bitreverse:_(s32) = G_BITREVERSE %const
1575 %copy_bswap:_(s32) = COPY %bswap
1576 %copy_bitreverse:_(s32) = COPY %bitreverse
1577 )";
1578 setUp(MIRString);
1579 if (!TM)
1580 GTEST_SKIP();
1581
1582 const uint32_t ByteSwappedVal = 0x44332211;
1583 const uint32_t BitSwappedVal = 0x22cc4488;
1584
1585 Register CopyBSwap = Copies[Copies.size() - 2];
1586 Register CopyBitReverse = Copies[Copies.size() - 1];
1587
1588 GISelKnownBits Info(*MF);
1589
1590 KnownBits BSwapKnown = Info.getKnownBits(CopyBSwap);
1591 EXPECT_EQ(32u, BSwapKnown.getBitWidth());
1592 EXPECT_EQ(ByteSwappedVal, BSwapKnown.One.getZExtValue());
1593 EXPECT_EQ(~ByteSwappedVal, BSwapKnown.Zero.getZExtValue());
1594
1595 KnownBits BitReverseKnown = Info.getKnownBits(CopyBitReverse);
1596 EXPECT_EQ(32u, BitReverseKnown.getBitWidth());
1597 EXPECT_EQ(BitSwappedVal, BitReverseKnown.One.getZExtValue());
1598 EXPECT_EQ(~BitSwappedVal, BitReverseKnown.Zero.getZExtValue());
1599 }
1600
1601 TEST_F(AArch64GISelMITest, TestKnownBitsUMAX) {
1602 StringRef MIRString = R"(
1603 %ptr:_(p0) = G_IMPLICIT_DEF
1604 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
1605 %mask0:_(s8) = G_CONSTANT i8 10
1606 %mask1:_(s8) = G_CONSTANT i8 1
1607 %tmp0:_(s8) = G_AND %unknown, %mask0
1608 %val0:_(s8) = G_OR %tmp0, %mask1
1609 %mask2:_(s8) = G_CONSTANT i8 3
1610 %mask3:_(s8) = G_CONSTANT i8 12
1611 %tmp1:_(s8) = G_AND %unknown, %mask2
1612 %val1:_(s8) = G_OR %tmp1, %mask3
1613 %umax0:_(s8) = G_UMAX %val0, %val1
1614 %copy_umax0:_(s8) = COPY %umax0
1615
1616 %mask4:_(s8) = G_CONSTANT i8 14
1617 %mask5:_(s8) = G_CONSTANT i8 2
1618 %tmp3:_(s8) = G_AND %unknown, %mask4
1619 %val3:_(s8) = G_OR %tmp3, %mask5
1620 %mask6:_(s8) = G_CONSTANT i8 4
1621 %mask7:_(s8) = G_CONSTANT i8 11
1622 %tmp4:_(s8) = G_AND %unknown, %mask6
1623 %val4:_(s8) = G_OR %tmp4, %mask7
1624 %umax1:_(s8) = G_UMAX %val3, %val4
1625 %copy_umax1:_(s8) = COPY %umax1
1626 )";
1627
1628 setUp(MIRString);
1629 if (!TM)
1630 GTEST_SKIP();
1631
1632 Register CopyReg0 = Copies[Copies.size() - 2];
1633 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
1634 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
1635 GISelKnownBits Info(*MF);
1636 // Compares min/max of LHS and RHS, min uses 0 for unknown bits, max uses 1.
1637 // If min(LHS) >= max(RHS) returns KnownBits for LHS, similar for RHS. If this
1638 // fails tries to calculate individual bits: common bits for both operands and
1639 // a few leading bits in some cases.
1640 // 0000?0?1
1641 // umax 000011??
1642 // = 000011??
1643 KnownBits Res0 = Info.getKnownBits(SrcReg0);
1644 EXPECT_EQ(0x0Cu, Res0.One.getZExtValue());
1645 EXPECT_EQ(0xF0u, Res0.Zero.getZExtValue());
1646
1647 Register CopyReg1 = Copies[Copies.size() - 1];
1648 MachineInstr *FinalCopy1 = MRI->getVRegDef(CopyReg1);
1649 Register SrcReg1 = FinalCopy1->getOperand(1).getReg();
1650 KnownBits Res1 = Info.getKnownBits(SrcReg1);
1651 // 0000??10
1652 // umax 00001?11
1653 // = 00001?1?
1654 EXPECT_EQ(0x0Au, Res1.One.getZExtValue());
1655 EXPECT_EQ(0xF0u, Res1.Zero.getZExtValue());
1656 }
1657
1658 TEST_F(AArch64GISelMITest, TestKnownBitsUMax) {
1659 StringRef MIRString = R"(
1660 %val:_(s32) = COPY $w0
1661 %zext:_(s64) = G_ZEXT %val
1662 %const:_(s64) = G_CONSTANT i64 -256
1663 %umax:_(s64) = G_UMAX %zext, %const
1664 %copy_umax:_(s64) = COPY %umax
1665 )";
1666 setUp(MIRString);
1667 if (!TM)
1668 GTEST_SKIP();
1669
1670 Register CopyUMax = Copies[Copies.size() - 1];
1671 GISelKnownBits Info(*MF);
1672
1673 KnownBits KnownUmax = Info.getKnownBits(CopyUMax);
1674 EXPECT_EQ(64u, KnownUmax.getBitWidth());
1675 EXPECT_EQ(0xffu, KnownUmax.Zero.getZExtValue());
1676 EXPECT_EQ(0xffffffffffffff00, KnownUmax.One.getZExtValue());
1677
1678 EXPECT_EQ(0xffu, KnownUmax.Zero.getZExtValue());
1679 EXPECT_EQ(0xffffffffffffff00, KnownUmax.One.getZExtValue());
1680 }
1681
1682 TEST_F(AArch64GISelMITest, TestKnownBitsUMIN) {
1683 StringRef MIRString = R"(
1684 %ptr:_(p0) = G_IMPLICIT_DEF
1685 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
1686 %mask0:_(s8) = G_CONSTANT i8 10
1687 %mask1:_(s8) = G_CONSTANT i8 1
1688 %tmp0:_(s8) = G_AND %unknown, %mask0
1689 %val0:_(s8) = G_OR %tmp0, %mask1
1690 %mask2:_(s8) = G_CONSTANT i8 3
1691 %mask3:_(s8) = G_CONSTANT i8 12
1692 %tmp1:_(s8) = G_AND %unknown, %mask2
1693 %val1:_(s8) = G_OR %tmp1, %mask3
1694 %umin:_(s8) = G_UMIN %val0, %val1
1695 %copy_umin:_(s8) = COPY %umin
1696 )";
1697
1698 setUp(MIRString);
1699 if (!TM)
1700 GTEST_SKIP();
1701
1702 Register CopyReg0 = Copies[Copies.size() - 1];
1703 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
1704 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
1705 GISelKnownBits Info(*MF);
1706 KnownBits Res0 = Info.getKnownBits(SrcReg0);
1707 // Flips the range of operands: [0, 0xFFFFFFFF] <-> [0xFFFFFFFF, 0],
1708 // uses umax and flips result back.
1709 // 0000?0?1
1710 // umin 000011??
1711 // = 0000?0?1
1712 EXPECT_EQ(0x01u, Res0.One.getZExtValue());
1713 EXPECT_EQ(0xF4u, Res0.Zero.getZExtValue());
1714 }
1715
1716 TEST_F(AArch64GISelMITest, TestKnownBitsSMAX) {
1717 StringRef MIRString = R"(
1718 %ptr:_(p0) = G_IMPLICIT_DEF
1719 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
1720 %mask0:_(s8) = G_CONSTANT i8 128
1721 %mask1:_(s8) = G_CONSTANT i8 64
1722 %tmp0:_(s8) = G_AND %unknown, %mask0
1723 %val0:_(s8) = G_OR %tmp0, %mask1
1724 %mask2:_(s8) = G_CONSTANT i8 1
1725 %mask3:_(s8) = G_CONSTANT i8 128
1726 %tmp1:_(s8) = G_AND %unknown, %mask2
1727 %val1:_(s8) = G_OR %tmp1, %mask3
1728 %smax:_(s8) = G_SMAX %val0, %val1
1729 %copy_smax:_(s8) = COPY %smax
1730 )";
1731
1732 setUp(MIRString);
1733 if (!TM)
1734 GTEST_SKIP();
1735
1736 Register CopyReg0 = Copies[Copies.size() - 1];
1737 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
1738 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
1739 GISelKnownBits Info(*MF);
1740 KnownBits Res0 = Info.getKnownBits(SrcReg0);
1741 // Flips the range of operands: [-0x80000000, 0x7FFFFFFF] <-> [0, 0xFFFFFFFF],
1742 // uses umax and flips result back.
1743 // RHS is negative, LHS is either positive or negative with smaller abs value.
1744 // ?1000000
1745 // smax 1000000?
1746 // = ?1000000
1747 EXPECT_EQ(0x40u, Res0.One.getZExtValue());
1748 EXPECT_EQ(0x3Fu, Res0.Zero.getZExtValue());
1749 }
1750
1751 TEST_F(AArch64GISelMITest, TestKnownBitsSMIN) {
1752 StringRef MIRString = R"(
1753 %ptr:_(p0) = G_IMPLICIT_DEF
1754 %unknown:_(s8) = G_LOAD %ptr(p0) :: (load (s8))
1755 %mask0:_(s8) = G_CONSTANT i8 128
1756 %mask1:_(s8) = G_CONSTANT i8 64
1757 %tmp0:_(s8) = G_AND %unknown, %mask0
1758 %val0:_(s8) = G_OR %tmp0, %mask1
1759 %mask2:_(s8) = G_CONSTANT i8 1
1760 %mask3:_(s8) = G_CONSTANT i8 128
1761 %tmp1:_(s8) = G_AND %unknown, %mask2
1762 %val1:_(s8) = G_OR %tmp1, %mask3
1763 %smin:_(s8) = G_SMIN %val0, %val1
1764 %copy_smin:_(s8) = COPY %smin
1765 )";
1766
1767 setUp(MIRString);
1768 if (!TM)
1769 GTEST_SKIP();
1770
1771 Register CopyReg0 = Copies[Copies.size() - 1];
1772 MachineInstr *FinalCopy0 = MRI->getVRegDef(CopyReg0);
1773 Register SrcReg0 = FinalCopy0->getOperand(1).getReg();
1774 GISelKnownBits Info(*MF);
1775 KnownBits Res0 = Info.getKnownBits(SrcReg0);
1776 // Flips the range of operands: [-0x80000000, 0x7FFFFFFF] <-> [0xFFFFFFFF, 0],
1777 // uses umax and flips result back.
1778 // RHS is negative, LHS is either positive or negative with smaller abs value.
1779 // ?1000000
1780 // smin 1000000?
1781 // = 1000000?
1782 EXPECT_EQ(0x80u, Res0.One.getZExtValue());
1783 EXPECT_EQ(0x7Eu, Res0.Zero.getZExtValue());
1784 }
1785
1786 TEST_F(AArch64GISelMITest, TestInvalidQueries) {
1787 StringRef MIRString = R"(
1788 %src:_(s32) = COPY $w0
1789 %thirty2:_(s32) = G_CONSTANT i32 32
1790 %equalSized:_(s32) = G_SHL %src, %thirty2
1791 %copy1:_(s32) = COPY %equalSized
1792 %thirty3:_(s32) = G_CONSTANT i32 33
1793 %biggerSized:_(s32) = G_SHL %src, %thirty3
1794 %copy2:_(s32) = COPY %biggerSized
1795 )";
1796 setUp(MIRString);
1797 if (!TM)
1798 GTEST_SKIP();
1799
1800 Register EqSizedCopyReg = Copies[Copies.size() - 2];
1801 MachineInstr *EqSizedCopy = MRI->getVRegDef(EqSizedCopyReg);
1802 Register EqSizedShl = EqSizedCopy->getOperand(1).getReg();
1803
1804 Register BiggerSizedCopyReg = Copies[Copies.size() - 1];
1805 MachineInstr *BiggerSizedCopy = MRI->getVRegDef(BiggerSizedCopyReg);
1806 Register BiggerSizedShl = BiggerSizedCopy->getOperand(1).getReg();
1807
1808 GISelKnownBits Info(*MF);
1809 KnownBits EqSizeRes = Info.getKnownBits(EqSizedShl);
1810 KnownBits BiggerSizeRes = Info.getKnownBits(BiggerSizedShl);
1811
1812
1813 // Result can be anything, but we should not crash.
1814 EXPECT_TRUE(EqSizeRes.One.isZero());
1815 EXPECT_TRUE(EqSizeRes.Zero.isAllOnes());
1816
1817 EXPECT_TRUE(BiggerSizeRes.One.isZero());
1818 EXPECT_TRUE(BiggerSizeRes.Zero.isAllOnes());
1819 }
1820
1821 TEST_F(AArch64GISelMITest, TestKnownBitsAssertZext) {
1822 StringRef MIRString = R"(
1823 %copy:_(s64) = COPY $x0
1824
1825 %assert8:_(s64) = G_ASSERT_ZEXT %copy, 8
1826 %copy_assert8:_(s64) = COPY %assert8
1827
1828 %assert1:_(s64) = G_ASSERT_ZEXT %copy, 1
1829 %copy_assert1:_(s64) = COPY %assert1
1830
1831 %assert63:_(s64) = G_ASSERT_ZEXT %copy, 63
1832 %copy_assert63:_(s64) = COPY %assert63
1833
1834 %assert3:_(s64) = G_ASSERT_ZEXT %copy, 3
1835 %copy_assert3:_(s64) = COPY %assert3
1836 )";
1837
1838 setUp(MIRString);
1839 if (!TM)
1840 GTEST_SKIP();
1841
1842 Register CopyAssert8 = Copies[Copies.size() - 4];
1843 Register CopyAssert1 = Copies[Copies.size() - 3];
1844 Register CopyAssert63 = Copies[Copies.size() - 2];
1845 Register CopyAssert3 = Copies[Copies.size() - 1];
1846
1847 GISelKnownBits Info(*MF);
1848 MachineInstr *Copy;
1849 Register SrcReg;
1850 KnownBits Res;
1851
1852 // Assert zero-extension from an 8-bit value.
1853 Copy = MRI->getVRegDef(CopyAssert8);
1854 SrcReg = Copy->getOperand(1).getReg();
1855 Res = Info.getKnownBits(SrcReg);
1856 EXPECT_EQ(64u, Res.getBitWidth());
1857 EXPECT_EQ(0u, Res.One.getZExtValue());
1858 EXPECT_EQ(0xFFFFFFFFFFFFFF00u, Res.Zero.getZExtValue());
1859
1860 // Assert zero-extension from a 1-bit value.
1861 Copy = MRI->getVRegDef(CopyAssert1);
1862 SrcReg = Copy->getOperand(1).getReg();
1863 Res = Info.getKnownBits(SrcReg);
1864 EXPECT_EQ(64u, Res.getBitWidth());
1865 EXPECT_EQ(0u, Res.One.getZExtValue());
1866 EXPECT_EQ(0xFFFFFFFFFFFFFFFE, Res.Zero.getZExtValue());
1867
1868 // Assert zero-extension from a 63-bit value.
1869 Copy = MRI->getVRegDef(CopyAssert63);
1870 SrcReg = Copy->getOperand(1).getReg();
1871 Res = Info.getKnownBits(SrcReg);
1872 EXPECT_EQ(64u, Res.getBitWidth());
1873 EXPECT_EQ(0u, Res.One.getZExtValue());
1874 EXPECT_EQ(0x8000000000000000u, Res.Zero.getZExtValue());
1875
1876 // Assert zero-extension from a 3-bit value.
1877 Copy = MRI->getVRegDef(CopyAssert3);
1878 SrcReg = Copy->getOperand(1).getReg();
1879 Res = Info.getKnownBits(SrcReg);
1880 EXPECT_EQ(64u, Res.getBitWidth());
1881 EXPECT_EQ(0u, Res.One.getZExtValue());
1882 EXPECT_EQ(0xFFFFFFFFFFFFFFF8u, Res.Zero.getZExtValue());
1883 }
1884
1885 TEST_F(AArch64GISelMITest, TestKnownBitsCTPOP) {
1886 StringRef MIRString = R"(
1887 %src:_(s32) = COPY $w0
1888 %unknown:_(s32) = G_CTPOP %src
1889 %unknown_copy:_(s32) = COPY %unknown
1890 %constant_4294967295:_(s32) = G_CONSTANT i32 4294967295
1891 %thirtytwo:_(s32) = G_CTPOP %constant_4294967295
1892 %thirtytwo_copy:_(s32) = COPY %thirtytwo
1893 %constant_15:_(s32) = G_CONSTANT i32 15
1894 %four:_(s32) = G_CTPOP %constant_15
1895 %four_copy:_(s32) = COPY %four
1896 %constant_1:_(s32) = G_CONSTANT i32 1
1897 %one:_(s32) = G_CTPOP %constant_1
1898 %one_copy:_(s32) = COPY %one
1899 )";
1900 setUp(MIRString);
1901 if (!TM)
1902 GTEST_SKIP();
1903
1904 Register UnknownCopy = Copies[Copies.size() - 4];
1905 Register ThirtytwoCopy = Copies[Copies.size() - 3];
1906 Register FourCopy = Copies[Copies.size() - 2];
1907 Register OneCopy = Copies[Copies.size() - 1];
1908
1909 GISelKnownBits Info(*MF);
1910 MachineInstr *Copy;
1911 Register SrcReg;
1912 KnownBits Res;
1913
1914 Copy = MRI->getVRegDef(UnknownCopy);
1915 SrcReg = Copy->getOperand(1).getReg();
1916 Res = Info.getKnownBits(SrcReg);
1917 EXPECT_EQ(32u, Res.getBitWidth());
1918 EXPECT_EQ(0u, Res.One.getZExtValue());
1919 EXPECT_EQ(0xFFFFFFC0u, Res.Zero.getZExtValue());
1920
1921 Copy = MRI->getVRegDef(ThirtytwoCopy);
1922 SrcReg = Copy->getOperand(1).getReg();
1923 Res = Info.getKnownBits(SrcReg);
1924 EXPECT_EQ(32u, Res.getBitWidth());
1925 EXPECT_EQ(0u, Res.One.getZExtValue());
1926 EXPECT_EQ(0xFFFFFFC0u, Res.Zero.getZExtValue());
1927
1928 Copy = MRI->getVRegDef(FourCopy);
1929 SrcReg = Copy->getOperand(1).getReg();
1930 Res = Info.getKnownBits(SrcReg);
1931 EXPECT_EQ(32u, Res.getBitWidth());
1932 EXPECT_EQ(0u, Res.One.getZExtValue());
1933 EXPECT_EQ(0xFFFFFFF8u, Res.Zero.getZExtValue());
1934
1935 Copy = MRI->getVRegDef(OneCopy);
1936 SrcReg = Copy->getOperand(1).getReg();
1937 Res = Info.getKnownBits(SrcReg);
1938 EXPECT_EQ(32u, Res.getBitWidth());
1939 EXPECT_EQ(0u, Res.One.getZExtValue());
1940 EXPECT_EQ(0xFFFFFFFEu, Res.Zero.getZExtValue());
1941 }
1942
1943 TEST_F(AMDGPUGISelMITest, TestKnownBitsUBFX) {
1944 StringRef MIRString = " %3:_(s32) = G_IMPLICIT_DEF\n"
1945 " %4:_(s32) = G_CONSTANT i32 12\n"
1946 " %5:_(s32) = G_CONSTANT i32 8\n"
1947 " %6:_(s32) = G_UBFX %3, %4(s32), %5\n"
1948 " %ubfx_copy:_(s32) = COPY %6\n"
1949 " %7:_(s32) = G_CONSTANT i32 28672\n"
1950 " %8:_(s32) = G_UBFX %7, %4(s32), %5\n"
1951 " %ubfx_copy_val:_(s32) = COPY %8\n"
1952 " %9:_(s32) = G_IMPLICIT_DEF\n"
1953 " %10:_(s32) = G_IMPLICIT_DEF\n"
1954 " %11:_(s32) = G_UBFX %3, %9(s32), %10\n"
1955 " %ubfx_copy_unk:_(s32) = COPY %11\n"
1956 " %12:_(s32) = G_UBFX %3, %9(s32), %5\n"
1957 " %ubfx_copy_unk_off:_(s32) = COPY %12\n"
1958 " %13:_(s32) = G_UBFX %3, %4(s32), %10\n"
1959 " %ubfx_copy_unk_width:_(s32) = COPY %13\n";
1960 setUp(MIRString);
1961 if (!TM)
1962 GTEST_SKIP();
1963 Register CopyBfxReg = Copies[Copies.size() - 5];
1964 Register CopyValBfxReg = Copies[Copies.size() - 4];
1965 Register CopyUnkBfxReg = Copies[Copies.size() - 3];
1966 Register CopyUnkOffBfxReg = Copies[Copies.size() - 2];
1967 Register CopyUnkWidthBfxReg = Copies[Copies.size() - 1];
1968
1969 MachineInstr *CopyBfx = MRI->getVRegDef(CopyBfxReg);
1970 Register SrcReg = CopyBfx->getOperand(1).getReg();
1971 MachineInstr *CopyValBfx = MRI->getVRegDef(CopyValBfxReg);
1972 Register ValSrcReg = CopyValBfx->getOperand(1).getReg();
1973 MachineInstr *CopyUnkBfx = MRI->getVRegDef(CopyUnkBfxReg);
1974 Register UnkSrcReg = CopyUnkBfx->getOperand(1).getReg();
1975 MachineInstr *CopyUnkOffBfx = MRI->getVRegDef(CopyUnkOffBfxReg);
1976 Register UnkOffSrcReg = CopyUnkOffBfx->getOperand(1).getReg();
1977 MachineInstr *CopyUnkWidthBfx = MRI->getVRegDef(CopyUnkWidthBfxReg);
1978 Register UnkWidthSrcReg = CopyUnkWidthBfx->getOperand(1).getReg();
1979
1980 GISelKnownBits Info(*MF);
1981
1982 KnownBits Res1 = Info.getKnownBits(SrcReg);
1983 EXPECT_EQ(0u, Res1.One.getZExtValue());
1984 EXPECT_EQ(0xffffff00u, Res1.Zero.getZExtValue());
1985
1986 KnownBits Res2 = Info.getKnownBits(ValSrcReg);
1987 EXPECT_EQ(7u, Res2.One.getZExtValue());
1988 EXPECT_EQ(0xfffffff8u, Res2.Zero.getZExtValue());
1989
1990 KnownBits Res3 = Info.getKnownBits(UnkSrcReg);
1991 EXPECT_EQ(0u, Res3.One.getZExtValue());
1992 EXPECT_EQ(0u, Res3.Zero.getZExtValue());
1993
1994 KnownBits Res4 = Info.getKnownBits(UnkOffSrcReg);
1995 EXPECT_EQ(0u, Res4.One.getZExtValue());
1996 EXPECT_EQ(0xffffff00u, Res4.Zero.getZExtValue());
1997
1998 KnownBits Res5 = Info.getKnownBits(UnkWidthSrcReg);
1999 EXPECT_EQ(0u, Res5.One.getZExtValue());
2000 EXPECT_EQ(0xfff00000u, Res5.Zero.getZExtValue());
2001 }
2002
2003 TEST_F(AMDGPUGISelMITest, TestKnownBitsSBFX) {
2004 StringRef MIRString = " %3:_(s32) = G_IMPLICIT_DEF\n"
2005 " %4:_(s32) = G_CONSTANT i32 8\n"
2006 " %5:_(s32) = G_CONSTANT i32 4\n"
2007 " %6:_(s32) = G_SBFX %3, %4(s32), %5\n"
2008 " %sbfx_copy:_(s32) = COPY %6\n"
2009 " %7:_(s32) = G_CONSTANT i32 2047\n"
2010 " %8:_(s32) = G_SBFX %7, %4(s32), %5\n"
2011 " %sbfx_copy_val:_(s32) = COPY %8\n"
2012 " %9:_(s32) = G_CONSTANT i32 2048\n"
2013 " %10:_(s32) = G_SBFX %9, %4(s32), %5\n"
2014 " %sbfx_copy_neg_val:_(s32) = COPY %10\n"
2015 " %11:_(s32) = G_IMPLICIT_DEF\n"
2016 " %12:_(s32) = G_SBFX %7, %11(s32), %5\n"
2017 " %sbfx_copy_unk_off:_(s32) = COPY %12\n"
2018 " %13:_(s32) = G_SBFX %9, %4(s32), %11\n"
2019 " %sbfx_copy_unk_width:_(s32) = COPY %13\n";
2020 setUp(MIRString);
2021 if (!TM)
2022 GTEST_SKIP();
2023 Register CopyBfxReg = Copies[Copies.size() - 5];
2024 Register CopyValBfxReg = Copies[Copies.size() - 4];
2025 Register CopyNegValBfxReg = Copies[Copies.size() - 3];
2026 Register CopyUnkOffBfxReg = Copies[Copies.size() - 2];
2027 Register CopyUnkWidthBfxReg = Copies[Copies.size() - 1];
2028
2029 MachineInstr *CopyBfx = MRI->getVRegDef(CopyBfxReg);
2030 Register SrcReg = CopyBfx->getOperand(1).getReg();
2031 MachineInstr *CopyValBfx = MRI->getVRegDef(CopyValBfxReg);
2032 Register ValSrcReg = CopyValBfx->getOperand(1).getReg();
2033 MachineInstr *CopyNegValBfx = MRI->getVRegDef(CopyNegValBfxReg);
2034 Register NegValSrcReg = CopyNegValBfx->getOperand(1).getReg();
2035 MachineInstr *CopyUnkOffBfx = MRI->getVRegDef(CopyUnkOffBfxReg);
2036 Register UnkOffSrcReg = CopyUnkOffBfx->getOperand(1).getReg();
2037 MachineInstr *CopyUnkWidthBfx = MRI->getVRegDef(CopyUnkWidthBfxReg);
2038 Register UnkWidthSrcReg = CopyUnkWidthBfx->getOperand(1).getReg();
2039
2040 GISelKnownBits Info(*MF);
2041
2042 KnownBits Res1 = Info.getKnownBits(SrcReg);
2043 EXPECT_EQ(0u, Res1.One.getZExtValue());
2044 EXPECT_EQ(0u, Res1.Zero.getZExtValue());
2045
2046 KnownBits Res2 = Info.getKnownBits(ValSrcReg);
2047 EXPECT_EQ(7u, Res2.One.getZExtValue());
2048 EXPECT_EQ(0xfffffff8u, Res2.Zero.getZExtValue());
2049
2050 KnownBits Res3 = Info.getKnownBits(NegValSrcReg);
2051 EXPECT_EQ(0xfffffff8u, Res3.One.getZExtValue());
2052 EXPECT_EQ(7u, Res3.Zero.getZExtValue());
2053
2054 KnownBits Res4 = Info.getKnownBits(UnkOffSrcReg);
2055 EXPECT_EQ(0u, Res4.One.getZExtValue());
2056 EXPECT_EQ(0u, Res4.Zero.getZExtValue());
2057
2058 KnownBits Res5 = Info.getKnownBits(UnkWidthSrcReg);
2059 EXPECT_EQ(0u, Res5.One.getZExtValue());
2060 EXPECT_EQ(0u, Res5.Zero.getZExtValue());
2061 }
2062
2063 TEST_F(AMDGPUGISelMITest, TestNumSignBitsUBFX) {
2064 StringRef MIRString = " %3:_(s32) = G_IMPLICIT_DEF\n"
2065 " %4:_(s32) = G_CONSTANT i32 12\n"
2066 " %5:_(s32) = G_CONSTANT i32 8\n"
2067 " %6:_(s32) = G_UBFX %3, %4(s32), %5\n"
2068 " %ubfx_copy_unk:_(s32) = COPY %6\n"
2069 " %7:_(s32) = G_CONSTANT i32 28672\n"
2070 " %8:_(s32) = G_UBFX %7, %4(s32), %5\n"
2071 " %ubfx_copy_pos:_(s32) = COPY %8\n"
2072 " %9:_(s32) = G_CONSTANT i32 -1\n"
2073 " %10:_(s32) = G_UBFX %9, %4(s32), %5\n"
2074 " %ubfx_copy_neg:_(s32) = COPY %10\n"
2075 " %11:_(s32) = G_IMPLICIT_DEF\n"
2076 " %12:_(s32) = G_UBFX %7, %11(s32), %5\n"
2077 " %ubfx_copy_unk_off:_(s32) = COPY %12\n"
2078 " %13:_(s32) = G_UBFX %7, %4(s32), %11\n"
2079 " %ubfx_copy_unk_width:_(s32) = COPY %13\n";
2080 setUp(MIRString);
2081 if (!TM)
2082 GTEST_SKIP();
2083 Register CopyUnkBfxReg = Copies[Copies.size() - 5];
2084 Register CopyPosBfxReg = Copies[Copies.size() - 4];
2085 Register CopyNegBfxReg = Copies[Copies.size() - 3];
2086 Register CopyUnkOffBfxReg = Copies[Copies.size() - 2];
2087 Register CopyUnkWidthBfxReg = Copies[Copies.size() - 1];
2088
2089 GISelKnownBits Info(*MF);
2090 EXPECT_EQ(24u, Info.computeNumSignBits(CopyUnkBfxReg));
2091 EXPECT_EQ(29u, Info.computeNumSignBits(CopyPosBfxReg));
2092 EXPECT_EQ(24u, Info.computeNumSignBits(CopyNegBfxReg));
2093 EXPECT_EQ(24u, Info.computeNumSignBits(CopyUnkOffBfxReg));
2094 EXPECT_EQ(29u, Info.computeNumSignBits(CopyUnkWidthBfxReg));
2095 }
2096
2097 TEST_F(AMDGPUGISelMITest, TestNumSignBitsSBFX) {
2098 StringRef MIRString = " %3:_(s32) = G_CONSTANT i32 -1\n"
2099 " %4:_(s32) = G_CONSTANT i32 8\n"
2100 " %5:_(s32) = G_CONSTANT i32 4\n"
2101 " %6:_(s32) = G_SBFX %3, %4(s32), %5\n"
2102 " %sbfx_copy_neg:_(s32) = COPY %6\n"
2103 " %7:_(s32) = G_CONSTANT i32 2047\n"
2104 " %8:_(s32) = G_SBFX %7, %4(s32), %5\n"
2105 " %sbfx_copy_pos:_(s32) = COPY %8\n"
2106 " %9:_(s32) = G_CONSTANT i32 2048\n"
2107 " %10:_(s32) = G_SBFX %9, %4(s32), %5\n"
2108 " %sbfx_copy_hiset:_(s32) = COPY %10\n"
2109 " %11:_(s32) = G_IMPLICIT_DEF\n"
2110 " %12:_(s32) = G_SBFX %11, %4(s32), %5\n"
2111 " %sbfx_copy_unk:_(s32) = COPY %12\n"
2112 " %13:_(s32) = G_SBFX %3, %11(s32), %5\n"
2113 " %sbfx_copy_unk_off:_(s32) = COPY %13\n";
2114 setUp(MIRString);
2115 if (!TM)
2116 GTEST_SKIP();
2117 Register CopyNegBfxReg = Copies[Copies.size() - 5];
2118 Register CopyPosBfxReg = Copies[Copies.size() - 4];
2119 Register CopyHiSetBfxReg = Copies[Copies.size() - 3];
2120 Register CopyUnkValBfxReg = Copies[Copies.size() - 2];
2121 Register CopyUnkOffBfxReg = Copies[Copies.size() - 1];
2122
2123 GISelKnownBits Info(*MF);
2124 EXPECT_EQ(32u, Info.computeNumSignBits(CopyNegBfxReg));
2125 EXPECT_EQ(29u, Info.computeNumSignBits(CopyPosBfxReg));
2126 EXPECT_EQ(29u, Info.computeNumSignBits(CopyHiSetBfxReg));
2127 EXPECT_EQ(1u, Info.computeNumSignBits(CopyUnkValBfxReg));
2128 EXPECT_EQ(1u, Info.computeNumSignBits(CopyUnkOffBfxReg));
2129 }
2130
2131 TEST_F(AMDGPUGISelMITest, TestKnownBitsAssertAlign) {
2132 StringRef MIRString = R"MIR(
2133 %val:_(s64) = COPY $vgpr0_vgpr1
2134 %ptrval:_(p1) = COPY $vgpr0_vgpr1
2135
2136 %assert_align1:_(s64) = G_ASSERT_ALIGN %val, 1
2137 %copy_assert_align1:_(s64) = COPY %assert_align1
2138
2139 %assert_align2:_(s64) = G_ASSERT_ALIGN %val, 2
2140 %copy_assert_align2:_(s64) = COPY %assert_align2
2141
2142 %assert_align4:_(s64) = G_ASSERT_ALIGN %val, 4
2143 %copy_assert_align4:_(s64) = COPY %assert_align4
2144
2145 %assert_align8:_(s64) = G_ASSERT_ALIGN %val, 8
2146 %copy_assert_align8:_(s64) = COPY %assert_align8
2147
2148 %assert_align16:_(s64) = G_ASSERT_ALIGN %val, 16
2149 %copy_assert_maxalign:_(s64) = COPY %assert_align16
2150 )MIR";
2151 setUp(MIRString);
2152 if (!TM)
2153 GTEST_SKIP();
2154 GISelKnownBits Info(*MF);
2155
2156 KnownBits Res;
2157 auto GetKB = [&](unsigned Idx) {
2158 Register CopyReg = Copies[Idx];
2159 auto *Copy = MRI->getVRegDef(CopyReg);
2160 return Info.getKnownBits(Copy->getOperand(1).getReg());
2161 };
2162
2163 auto CheckBits = [&](unsigned NumBits, unsigned Idx) {
2164 Res = GetKB(Idx);
2165 EXPECT_EQ(64u, Res.getBitWidth());
2166 EXPECT_EQ(NumBits - 1, Res.Zero.countr_one());
2167 EXPECT_EQ(64u, Res.One.countr_zero());
2168 EXPECT_EQ(Align(1ull << (NumBits - 1)), Info.computeKnownAlignment(Copies[Idx]));
2169 };
2170
2171 const unsigned NumSetupCopies = 5;
2172 CheckBits(1, NumSetupCopies);
2173 CheckBits(2, NumSetupCopies + 1);
2174 CheckBits(3, NumSetupCopies + 2);
2175 CheckBits(4, NumSetupCopies + 3);
2176 CheckBits(5, NumSetupCopies + 4);
2177 }
2178
2179 TEST_F(AArch64GISelMITest, TestKnownBitsUADDO) {
2180 StringRef MIRString = R"(
2181 %ptr:_(p0) = G_IMPLICIT_DEF
2182 %ld0:_(s32) = G_LOAD %ptr(p0) :: (load (s16))
2183 %ld1:_(s32) = G_LOAD %ptr(p0) :: (load (s16))
2184
2185 %add:_(s32), %overflow:_(s32) = G_UADDO %ld0, %ld1
2186 %copy_overflow:_(s32) = COPY %overflow
2187 )";
2188
2189 setUp(MIRString);
2190 if (!TM)
2191 GTEST_SKIP();
2192
2193 Register CopyOverflow = Copies[Copies.size() - 1];
2194 GISelKnownBits Info(*MF);
2195 KnownBits Res = Info.getKnownBits(CopyOverflow);
2196 EXPECT_EQ(0u, Res.One.getZExtValue());
2197 EXPECT_EQ(31u, Res.Zero.countl_one());
2198 }
LLVM monorepo