llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td

   1 //==- RISCVSchedSiFiveP400.td - SiFiveP400 Scheduling Defs ---*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 //===----------------------------------------------------------------------===//
  10
  11 def SiFiveP400Model : SchedMachineModel {
  12   let IssueWidth = 3;         // 3 micro-ops are dispatched per cycle.
  13   let MicroOpBufferSize = 56; // Max micro-ops that can be buffered.
  14   let LoadLatency = 4;        // Cycles for loads to access the cache.
  15   let MispredictPenalty = 9;  // Extra cycles for a mispredicted branch.
  16   let PostRAScheduler = true;
  17   let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
  18                              HasStdExtZcmt, HasStdExtZknd, HasStdExtZkne,
  19                              HasStdExtZknh, HasStdExtZksed, HasStdExtZksh,
  20                              HasStdExtZkr];
  21   let CompleteModel = false;
  22 }
  23
  24 // The SiFiveP400 microarchitecure has 6 pipelines:
  25 // Three pipelines for integer operations.
  26 // One pipeline for FPU operations.
  27 // One pipeline for Load operations.
  28 // One pipeline for Store operations.
  29 let SchedModel = SiFiveP400Model in {
  30
  31 def SiFiveP400IEXQ0       : ProcResource<1>;
  32 def SiFiveP400IEXQ1       : ProcResource<1>;
  33 def SiFiveP400IEXQ2       : ProcResource<1>;
  34 def SiFiveP400FEXQ0       : ProcResource<1>;
  35 def SiFiveP400Load        : ProcResource<1>;
  36 def SiFiveP400Store       : ProcResource<1>;
  37
  38 def SiFiveP400IntArith    : ProcResGroup<[SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2]>;
  39 defvar SiFiveP400Branch   = SiFiveP400IEXQ0;
  40 defvar SiFiveP400SYS      = SiFiveP400IEXQ1;
  41 defvar SiFiveP400MulDiv   = SiFiveP400IEXQ2;
  42 defvar SiFiveP400I2F      = SiFiveP400IEXQ2;
  43 def SiFiveP400Div         : ProcResource<1>;
  44
  45 defvar SiFiveP400FloatArith  = SiFiveP400FEXQ0;
  46 defvar SiFiveP400F2I      = SiFiveP400FEXQ0;
  47 def SiFiveP400FloatDiv    : ProcResource<1>;
  48
  49 let Latency = 1 in {
  50 // Integer arithmetic and logic
  51 def : WriteRes<WriteIALU, [SiFiveP400IntArith]>;
  52 def : WriteRes<WriteIALU32, [SiFiveP400IntArith]>;
  53 def : WriteRes<WriteShiftImm, [SiFiveP400IntArith]>;
  54 def : WriteRes<WriteShiftImm32, [SiFiveP400IntArith]>;
  55 def : WriteRes<WriteShiftReg, [SiFiveP400IntArith]>;
  56 def : WriteRes<WriteShiftReg32, [SiFiveP400IntArith]>;
  57 // Branching
  58 def : WriteRes<WriteJmp, [SiFiveP400Branch]>;
  59 def : WriteRes<WriteJal, [SiFiveP400Branch]>;
  60 def : WriteRes<WriteJalr, [SiFiveP400Branch]>;
  61 }
  62
  63 // CMOV
  64 def P400WriteCMOV : SchedWriteRes<[SiFiveP400Branch, SiFiveP400IEXQ1]> {
  65   let Latency = 2;
  66   let NumMicroOps = 2;
  67 }
  68 def : InstRW<[P400WriteCMOV], (instrs PseudoCCMOVGPRNoX0)>;
  69
  70 let Latency = 3 in {
  71 // Integer multiplication
  72 def : WriteRes<WriteIMul, [SiFiveP400MulDiv]>;
  73 def : WriteRes<WriteIMul32, [SiFiveP400MulDiv]>;
  74 // cpop[w] look exactly like multiply.
  75 def : WriteRes<WriteCPOP, [SiFiveP400MulDiv]>;
  76 def : WriteRes<WriteCPOP32, [SiFiveP400MulDiv]>;
  77 }
  78
  79 // Integer division
  80 def : WriteRes<WriteIDiv, [SiFiveP400MulDiv, SiFiveP400Div]> {
  81   let Latency = 35;
  82   let ReleaseAtCycles = [1, 34];
  83 }
  84 def : WriteRes<WriteIDiv32, [SiFiveP400MulDiv, SiFiveP400Div]> {
  85   let Latency = 20;
  86   let ReleaseAtCycles = [1, 19];
  87 }
  88
  89 let Latency = 1 in {
  90 // Bitmanip
  91 def : WriteRes<WriteRotateImm, [SiFiveP400IntArith]>;
  92 def : WriteRes<WriteRotateImm32, [SiFiveP400IntArith]>;
  93 def : WriteRes<WriteRotateReg, [SiFiveP400IntArith]>;
  94 def : WriteRes<WriteRotateReg32, [SiFiveP400IntArith]>;
  95
  96 def : WriteRes<WriteCLZ, [SiFiveP400IntArith]>;
  97 def : WriteRes<WriteCLZ32, [SiFiveP400IntArith]>;
  98 def : WriteRes<WriteCTZ, [SiFiveP400IntArith]>;
  99 def : WriteRes<WriteCTZ32, [SiFiveP400IntArith]>;
 100
 101 def : WriteRes<WriteORCB, [SiFiveP400IntArith]>;
 102
 103 def : WriteRes<WriteREV8, [SiFiveP400IntArith]>;
 104
 105 def : WriteRes<WriteSHXADD, [SiFiveP400IntArith]>;
 106 def : WriteRes<WriteSHXADD32, [SiFiveP400IntArith]>;
 107
 108 def : WriteRes<WriteSingleBit, [SiFiveP400IntArith]>;
 109 def : WriteRes<WriteSingleBitImm, [SiFiveP400IntArith]>;
 110 def : WriteRes<WriteBEXT, [SiFiveP400IntArith]>;
 111 def : WriteRes<WriteBEXTI, [SiFiveP400IntArith]>;
 112 }
 113
 114 // Memory
 115 let Latency = 1 in {
 116 def : WriteRes<WriteSTB, [SiFiveP400Store]>;
 117 def : WriteRes<WriteSTH, [SiFiveP400Store]>;
 118 def : WriteRes<WriteSTW, [SiFiveP400Store]>;
 119 def : WriteRes<WriteSTD, [SiFiveP400Store]>;
 120 def : WriteRes<WriteFST16, [SiFiveP400Store]>;
 121 def : WriteRes<WriteFST32, [SiFiveP400Store]>;
 122 def : WriteRes<WriteFST64, [SiFiveP400Store]>;
 123 }
 124 let Latency = 4 in {
 125 def : WriteRes<WriteLDB, [SiFiveP400Load]>;
 126 def : WriteRes<WriteLDH, [SiFiveP400Load]>;
 127 }
 128 let Latency = 4 in {
 129 def : WriteRes<WriteLDW, [SiFiveP400Load]>;
 130 def : WriteRes<WriteLDD, [SiFiveP400Load]>;
 131 }
 132
 133 let Latency = 6 in {
 134 def : WriteRes<WriteFLD16, [SiFiveP400Load]>;
 135 def : WriteRes<WriteFLD32, [SiFiveP400Load]>;
 136 def : WriteRes<WriteFLD64, [SiFiveP400Load]>;
 137 }
 138
 139 // Atomic memory
 140 let Latency = 3 in {
 141 def : WriteRes<WriteAtomicSTW, [SiFiveP400Store]>;
 142 def : WriteRes<WriteAtomicSTD, [SiFiveP400Store]>;
 143 def : WriteRes<WriteAtomicW, [SiFiveP400Load]>;
 144 def : WriteRes<WriteAtomicD, [SiFiveP400Load]>;
 145 def : WriteRes<WriteAtomicLDW, [SiFiveP400Load]>;
 146 def : WriteRes<WriteAtomicLDD, [SiFiveP400Load]>;
 147 }
 148
 149 // Floating point
 150 let Latency = 4 in {
 151 def : WriteRes<WriteFAdd16, [SiFiveP400FloatArith]>;
 152 def : WriteRes<WriteFAdd32, [SiFiveP400FloatArith]>;
 153 def : WriteRes<WriteFAdd64, [SiFiveP400FloatArith]>;
 154
 155 def : WriteRes<WriteFMul16, [SiFiveP400FloatArith]>;
 156 def : WriteRes<WriteFMul32, [SiFiveP400FloatArith]>;
 157 def : WriteRes<WriteFMul64, [SiFiveP400FloatArith]>;
 158
 159 def : WriteRes<WriteFMA16, [SiFiveP400FloatArith]>;
 160 def : WriteRes<WriteFMA32, [SiFiveP400FloatArith]>;
 161 def : WriteRes<WriteFMA64, [SiFiveP400FloatArith]>;
 162 }
 163
 164 let Latency = 2 in {
 165 def : WriteRes<WriteFSGNJ16, [SiFiveP400FloatArith]>;
 166 def : WriteRes<WriteFSGNJ32, [SiFiveP400FloatArith]>;
 167 def : WriteRes<WriteFSGNJ64, [SiFiveP400FloatArith]>;
 168
 169 def : WriteRes<WriteFMinMax16, [SiFiveP400FloatArith]>;
 170 def : WriteRes<WriteFMinMax32, [SiFiveP400FloatArith]>;
 171 def : WriteRes<WriteFMinMax64, [SiFiveP400FloatArith]>;
 172 }
 173
 174 // Half precision.
 175 def : WriteRes<WriteFDiv16, [SiFiveP400FEXQ0, SiFiveP400FloatDiv]> {
 176   let Latency = 19;
 177   let ReleaseAtCycles = [1, 18];
 178 }
 179 def : WriteRes<WriteFSqrt16, [SiFiveP400FEXQ0, SiFiveP400FloatDiv]> {
 180   let Latency = 18;
 181   let ReleaseAtCycles = [1, 17];
 182 }
 183
 184 // Single precision.
 185 def : WriteRes<WriteFDiv32, [SiFiveP400FEXQ0, SiFiveP400FloatDiv]> {
 186   let Latency = 19;
 187   let ReleaseAtCycles = [1, 18];
 188 }
 189 def : WriteRes<WriteFSqrt32, [SiFiveP400FEXQ0, SiFiveP400FloatDiv]> {
 190   let Latency = 18;
 191   let ReleaseAtCycles = [1, 17];
 192 }
 193
 194 // Double precision
 195 def : WriteRes<WriteFDiv64, [SiFiveP400FEXQ0, SiFiveP400FloatDiv]> {
 196   let Latency = 33;
 197   let ReleaseAtCycles = [1, 32];
 198 }
 199 def : WriteRes<WriteFSqrt64, [SiFiveP400FEXQ0, SiFiveP400FloatDiv]> {
 200   let Latency = 33;
 201   let ReleaseAtCycles = [1, 32];
 202 }
 203
 204 // Conversions
 205 let Latency = 2 in {
 206 def : WriteRes<WriteFCvtI32ToF16, [SiFiveP400I2F]>;
 207 def : WriteRes<WriteFCvtI32ToF32, [SiFiveP400I2F]>;
 208 def : WriteRes<WriteFCvtI32ToF64, [SiFiveP400I2F]>;
 209 def : WriteRes<WriteFCvtI64ToF16, [SiFiveP400I2F]>;
 210 def : WriteRes<WriteFCvtI64ToF32, [SiFiveP400I2F]>;
 211 def : WriteRes<WriteFCvtI64ToF64, [SiFiveP400I2F]>;
 212 def : WriteRes<WriteFCvtF16ToI32, [SiFiveP400F2I]>;
 213 def : WriteRes<WriteFCvtF16ToI64, [SiFiveP400F2I]>;
 214 def : WriteRes<WriteFCvtF16ToF32, [SiFiveP400FloatArith]>;
 215 def : WriteRes<WriteFCvtF16ToF64, [SiFiveP400FloatArith]>;
 216 def : WriteRes<WriteFCvtF32ToI32, [SiFiveP400F2I]>;
 217 def : WriteRes<WriteFCvtF32ToI64, [SiFiveP400F2I]>;
 218 def : WriteRes<WriteFCvtF32ToF16, [SiFiveP400FloatArith]>;
 219 def : WriteRes<WriteFCvtF32ToF64, [SiFiveP400FloatArith]>;
 220 def : WriteRes<WriteFCvtF64ToI32, [SiFiveP400F2I]>;
 221 def : WriteRes<WriteFCvtF64ToI64, [SiFiveP400F2I]>;
 222 def : WriteRes<WriteFCvtF64ToF16, [SiFiveP400FloatArith]>;
 223 def : WriteRes<WriteFCvtF64ToF32, [SiFiveP400FloatArith]>;
 224
 225 def : WriteRes<WriteFClass16, [SiFiveP400F2I]>;
 226 def : WriteRes<WriteFClass32, [SiFiveP400F2I]>;
 227 def : WriteRes<WriteFClass64, [SiFiveP400F2I]>;
 228 def : WriteRes<WriteFCmp16, [SiFiveP400F2I]>;
 229 def : WriteRes<WriteFCmp32, [SiFiveP400F2I]>;
 230 def : WriteRes<WriteFCmp64, [SiFiveP400F2I]>;
 231 def : WriteRes<WriteFMovI16ToF16, [SiFiveP400I2F]>;
 232 def : WriteRes<WriteFMovF16ToI16, [SiFiveP400F2I]>;
 233 def : WriteRes<WriteFMovI32ToF32, [SiFiveP400I2F]>;
 234 def : WriteRes<WriteFMovF32ToI32, [SiFiveP400F2I]>;
 235 def : WriteRes<WriteFMovI64ToF64, [SiFiveP400I2F]>;
 236 def : WriteRes<WriteFMovF64ToI64, [SiFiveP400F2I]>;
 237 }
 238
 239 // Others
 240 def : WriteRes<WriteCSR, [SiFiveP400SYS]>;
 241 def : WriteRes<WriteNop, []>;
 242
 243 // FIXME: This could be better modeled by looking at the regclasses of the operands.
 244 def : InstRW<[WriteIALU, ReadIALU], (instrs COPY)>;
 245
 246 //===----------------------------------------------------------------------===//
 247 // Bypass and advance
 248 def : ReadAdvance<ReadJmp, 0>;
 249 def : ReadAdvance<ReadJalr, 0>;
 250 def : ReadAdvance<ReadCSR, 0>;
 251 def : ReadAdvance<ReadStoreData, 0>;
 252 def : ReadAdvance<ReadMemBase, 0>;
 253 def : ReadAdvance<ReadIALU, 0>;
 254 def : ReadAdvance<ReadIALU32, 0>;
 255 def : ReadAdvance<ReadShiftImm, 0>;
 256 def : ReadAdvance<ReadShiftImm32, 0>;
 257 def : ReadAdvance<ReadShiftReg, 0>;
 258 def : ReadAdvance<ReadShiftReg32, 0>;
 259 def : ReadAdvance<ReadIDiv, 0>;
 260 def : ReadAdvance<ReadIDiv32, 0>;
 261 def : ReadAdvance<ReadIMul, 0>;
 262 def : ReadAdvance<ReadIMul32, 0>;
 263 def : ReadAdvance<ReadAtomicWA, 0>;
 264 def : ReadAdvance<ReadAtomicWD, 0>;
 265 def : ReadAdvance<ReadAtomicDA, 0>;
 266 def : ReadAdvance<ReadAtomicDD, 0>;
 267 def : ReadAdvance<ReadAtomicLDW, 0>;
 268 def : ReadAdvance<ReadAtomicLDD, 0>;
 269 def : ReadAdvance<ReadAtomicSTW, 0>;
 270 def : ReadAdvance<ReadAtomicSTD, 0>;
 271 def : ReadAdvance<ReadFStoreData, 0>;
 272 def : ReadAdvance<ReadFMemBase, 0>;
 273 def : ReadAdvance<ReadFAdd16, 0>;
 274 def : ReadAdvance<ReadFAdd32, 0>;
 275 def : ReadAdvance<ReadFAdd64, 0>;
 276 def : ReadAdvance<ReadFMul16, 0>;
 277 def : ReadAdvance<ReadFMA16, 0>;
 278 def : ReadAdvance<ReadFMA16Addend, 0>;
 279 def : ReadAdvance<ReadFMul32, 0>;
 280 def : ReadAdvance<ReadFMA32, 0>;
 281 def : ReadAdvance<ReadFMA32Addend, 0>;
 282 def : ReadAdvance<ReadFMul64, 0>;
 283 def : ReadAdvance<ReadFMA64, 0>;
 284 def : ReadAdvance<ReadFMA64Addend, 0>;
 285 def : ReadAdvance<ReadFDiv16, 0>;
 286 def : ReadAdvance<ReadFDiv32, 0>;
 287 def : ReadAdvance<ReadFDiv64, 0>;
 288 def : ReadAdvance<ReadFSqrt16, 0>;
 289 def : ReadAdvance<ReadFSqrt32, 0>;
 290 def : ReadAdvance<ReadFSqrt64, 0>;
 291 def : ReadAdvance<ReadFCmp16, 0>;
 292 def : ReadAdvance<ReadFCmp32, 0>;
 293 def : ReadAdvance<ReadFCmp64, 0>;
 294 def : ReadAdvance<ReadFSGNJ16, 0>;
 295 def : ReadAdvance<ReadFSGNJ32, 0>;
 296 def : ReadAdvance<ReadFSGNJ64, 0>;
 297 def : ReadAdvance<ReadFMinMax16, 0>;
 298 def : ReadAdvance<ReadFMinMax32, 0>;
 299 def : ReadAdvance<ReadFMinMax64, 0>;
 300 def : ReadAdvance<ReadFCvtF16ToI32, 0>;
 301 def : ReadAdvance<ReadFCvtF16ToI64, 0>;
 302 def : ReadAdvance<ReadFCvtF32ToI32, 0>;
 303 def : ReadAdvance<ReadFCvtF32ToI64, 0>;
 304 def : ReadAdvance<ReadFCvtF64ToI32, 0>;
 305 def : ReadAdvance<ReadFCvtF64ToI64, 0>;
 306 def : ReadAdvance<ReadFCvtI32ToF16, 0>;
 307 def : ReadAdvance<ReadFCvtI32ToF32, 0>;
 308 def : ReadAdvance<ReadFCvtI32ToF64, 0>;
 309 def : ReadAdvance<ReadFCvtI64ToF16, 0>;
 310 def : ReadAdvance<ReadFCvtI64ToF32, 0>;
 311 def : ReadAdvance<ReadFCvtI64ToF64, 0>;
 312 def : ReadAdvance<ReadFCvtF32ToF64, 0>;
 313 def : ReadAdvance<ReadFCvtF64ToF32, 0>;
 314 def : ReadAdvance<ReadFCvtF16ToF32, 0>;
 315 def : ReadAdvance<ReadFCvtF32ToF16, 0>;
 316 def : ReadAdvance<ReadFCvtF16ToF64, 0>;
 317 def : ReadAdvance<ReadFCvtF64ToF16, 0>;
 318 def : ReadAdvance<ReadFMovF16ToI16, 0>;
 319 def : ReadAdvance<ReadFMovI16ToF16, 0>;
 320 def : ReadAdvance<ReadFMovF32ToI32, 0>;
 321 def : ReadAdvance<ReadFMovI32ToF32, 0>;
 322 def : ReadAdvance<ReadFMovF64ToI64, 0>;
 323 def : ReadAdvance<ReadFMovI64ToF64, 0>;
 324 def : ReadAdvance<ReadFClass16, 0>;
 325 def : ReadAdvance<ReadFClass32, 0>;
 326 def : ReadAdvance<ReadFClass64, 0>;
 327
 328 // Bitmanip
 329 def : ReadAdvance<ReadRotateImm, 0>;
 330 def : ReadAdvance<ReadRotateImm32, 0>;
 331 def : ReadAdvance<ReadRotateReg, 0>;
 332 def : ReadAdvance<ReadRotateReg32, 0>;
 333 def : ReadAdvance<ReadCLZ, 0>;
 334 def : ReadAdvance<ReadCLZ32, 0>;
 335 def : ReadAdvance<ReadCTZ, 0>;
 336 def : ReadAdvance<ReadCTZ32, 0>;
 337 def : ReadAdvance<ReadCPOP, 0>;
 338 def : ReadAdvance<ReadCPOP32, 0>;
 339 def : ReadAdvance<ReadORCB, 0>;
 340 def : ReadAdvance<ReadREV8, 0>;
 341 def : ReadAdvance<ReadSHXADD, 0>;
 342 def : ReadAdvance<ReadSHXADD32, 0>;
 343 def : ReadAdvance<ReadSingleBit, 0>;
 344 def : ReadAdvance<ReadSingleBitImm, 0>;
 345
 346 //===----------------------------------------------------------------------===//
 347 // Unsupported extensions
 348 defm : UnsupportedSchedZbc;
 349 defm : UnsupportedSchedZbkb;
 350 defm : UnsupportedSchedZbkx;
 351 defm : UnsupportedSchedSFB;
 352 defm : UnsupportedSchedZfa;
 353 defm : UnsupportedSchedV;
 354 }