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1 //===- RISCVScheduleV.td - RISC-V Scheduling Definitions V -*- tablegen -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
10 /// Define scheduler resources associated with def operands.
12 defvar SchedMxList = ["MF8", "MF4", "MF2", "M1", "M2", "M4", "M8"];
13 // Used for widening and narrowing instructions as it doesn't contain M8.
14 defvar SchedMxListW = !listremove(SchedMxList, ["M8"]);
15 // Used for widening reductions, which does contain M8.
16 defvar SchedMxListWRed = SchedMxList;
17 defvar SchedMxListFW = !listremove(SchedMxList, ["M8", "MF8"]);
18 // Used for floating-point as it doesn't contain MF8.
19 defvar SchedMxListF = !listremove(SchedMxList, ["MF8"]);
20 // Used for widening floating-point Reduction as it doesn't contain MF8.
21 defvar SchedMxListFWRed = SchedMxListF;
23 class SchedSEWSet<string mx, bit isF = 0, bit isWidening = 0> {
24 assert !or(!not(isF), !ne(mx, "MF8")), "LMUL shouldn't be MF8 for floating-point";
25 defvar t = !cond(!eq(mx, "M1"): [8, 16, 32, 64],
26 !eq(mx, "M2"): [8, 16, 32, 64],
27 !eq(mx, "M4"): [8, 16, 32, 64],
28 !eq(mx, "M8"): [8, 16, 32, 64],
29 !eq(mx, "MF2"): [8, 16, 32],
30 !eq(mx, "MF4"): [8, 16],
31 !eq(mx, "MF8"): [8]);
32 // For floating-point instructions, SEW won't be 8.
33 defvar remove8 = !if(isF, !listremove(t, [8]), t);
34 // For widening instructions, SEW will not be 64.
35 defvar remove64 = !if(isWidening, !listremove(remove8, [64]), remove8);
36 list<int> val = remove64;
37 }
39 // Helper function to get the largest LMUL from MxList
40 // Precondition: MxList is sorted in ascending LMUL order.
41 class LargestLMUL<list<string> MxList> {
42 // MX list is sorted from smallest to largest
43 string r = !foldl(!head(MxList), MxList, last, curr, curr);
44 }
45 // Helper function to get the smallest SEW that can be used with LMUL mx
46 // Precondition: MxList is sorted in ascending LMUL order and SchedSEWSet<mx>
47 class SmallestSEW<string mx, bit isF = 0> {
48 int r = !head(SchedSEWSet<mx, isF>.val);
49 }
51 // Creates WriteRes for (name, mx, resources) tuple
52 multiclass LMULWriteResMX<string name, list<ProcResourceKind> resources,
53 string mx, bit IsWorstCase> {
54 def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources>;
55 if IsWorstCase then
56 def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
57 }
58 multiclass LMULSEWWriteResMXSEW<string name, list<ProcResourceKind> resources,
59 string mx, int sew, bit IsWorstCase> {
60 def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources>;
61 if IsWorstCase then
62 def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
63 }
65 // Define a SchedAlias for the SchedWrite associated with (name, mx) whose
66 // behavior is aliased to a Variant. The Variant has Latency predLad and
67 // ReleaseAtCycles predCycles if the SchedPredicate Pred is true, otherwise has
68 // Latency noPredLat and ReleaseAtCycles noPredCycles. The WorstCase SchedWrite
69 // is created similiarly if IsWorstCase is true.
70 multiclass LMULWriteResMXVariant<string name, SchedPredicateBase Pred,
71 list<ProcResourceKind> resources,
72 int predLat, list<int> predAcquireCycles,
73 list<int> predReleaseCycles, int noPredLat,
74 list<int> noPredAcquireCycles,
75 list<int> noPredReleaseCycles,
76 string mx, bit IsWorstCase> {
77 defvar nameMX = name # "_" # mx;
79 // Define the different behaviors
80 def nameMX # "_Pred" : SchedWriteRes<resources>{
81 let Latency = predLat;
82 let AcquireAtCycles = predAcquireCycles;
83 let ReleaseAtCycles = predReleaseCycles;
84 }
85 def nameMX # "_NoPred" : SchedWriteRes<resources> {
86 let Latency = noPredLat;
87 let AcquireAtCycles = noPredAcquireCycles;
88 let ReleaseAtCycles = noPredReleaseCycles;
89 }
91 // Tie behavior to predicate
92 def NAME # nameMX # "_Variant" : SchedWriteVariant<[
93 SchedVar<Pred, [!cast<SchedWriteRes>(NAME # nameMX # "_Pred")]>,
94 SchedVar<NoSchedPred, [!cast<SchedWriteRes>(NAME # nameMX # "_NoPred")]>
95 ]>;
96 def : SchedAlias<
97 !cast<SchedReadWrite>(nameMX),
98 !cast<SchedReadWrite>(NAME # nameMX # "_Variant")>;
100 if IsWorstCase then {
101 def NAME # name # "_WorstCase_Variant" : SchedWriteVariant<[
102 SchedVar<Pred, [!cast<SchedWriteRes>(NAME # nameMX # "_Pred")]>,
103 SchedVar<NoSchedPred, [!cast<SchedWriteRes>(NAME # nameMX # "_NoPred")]>
104 ]>;
105 def : SchedAlias<
106 !cast<SchedReadWrite>(name # "_WorstCase"),
107 !cast<SchedReadWrite>(NAME # name # "_WorstCase_Variant")>;
108 }
109 }
111 // Define multiclasses to define SchedWrite, SchedRead, WriteRes, and
112 // ReadAdvance for each (name, LMUL) pair and for each LMUL in each of the
113 // SchedMxList variants above. Each multiclass is responsible for defining
114 // a record that represents the WorseCase behavior for name.
115 multiclass LMULSchedWritesImpl<string name, list<string> MxList> {
116 def name # "_WorstCase" : SchedWrite;
117 foreach mx = MxList in {
118 def name # "_" # mx : SchedWrite;
119 }
120 }
121 multiclass LMULSchedReadsImpl<string name, list<string> MxList> {
122 def name # "_WorstCase" : SchedRead;
123 foreach mx = MxList in {
124 def name # "_" # mx : SchedRead;
125 }
126 }
127 multiclass LMULWriteResImpl<string name, list<ProcResourceKind> resources> {
128 if !exists<SchedWrite>(name # "_WorstCase") then
129 def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
130 foreach mx = SchedMxList in {
131 if !exists<SchedWrite>(name # "_" # mx) then
132 def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources>;
133 }
134 }
135 multiclass LMULReadAdvanceImpl<string name, int val,
136 list<SchedWrite> writes = []> {
137 if !exists<SchedRead>(name # "_WorstCase") then
138 def : ReadAdvance<!cast<SchedRead>(name # "_WorstCase"), val, writes>;
139 foreach mx = SchedMxList in {
140 if !exists<SchedRead>(name # "_" # mx) then
141 def : ReadAdvance<!cast<SchedRead>(name # "_" # mx), val, writes>;
142 }
143 }
145 // Define multiclasses to define SchedWrite, SchedRead, WriteRes, and
146 // ReadAdvance for each (name, LMUL, SEW) tuple for each LMUL in each of the
147 // SchedMxList variants above. Each multiclass is responsible for defining
148 // a record that represents the WorseCase behavior for name.
149 multiclass LMULSEWSchedWritesImpl<string name, list<string> MxList, bit isF = 0,
150 bit isWidening = 0> {
151 def name # "_WorstCase" : SchedWrite;
152 foreach mx = MxList in {
153 foreach sew = SchedSEWSet<mx, isF, isWidening>.val in
154 def name # "_" # mx # "_E" # sew : SchedWrite;
155 }
156 }
157 multiclass LMULSEWSchedReadsImpl<string name, list<string> MxList, bit isF = 0,
158 bit isWidening = 0> {
159 def name # "_WorstCase" : SchedRead;
160 foreach mx = MxList in {
161 foreach sew = SchedSEWSet<mx, isF, isWidening>.val in
162 def name # "_" # mx # "_E" # sew : SchedRead;
163 }
164 }
165 multiclass LMULSEWWriteResImpl<string name, list<ProcResourceKind> resources,
166 list<string> MxList, bit isF = 0,
167 bit isWidening = 0> {
168 if !exists<SchedWrite>(name # "_WorstCase") then
169 def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
170 foreach mx = MxList in {
171 foreach sew = SchedSEWSet<mx, isF, isWidening>.val in
172 if !exists<SchedWrite>(name # "_" # mx # "_E" # sew) then
173 def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources>;
174 }
175 }
176 multiclass LMULSEWReadAdvanceImpl<string name, int val, list<SchedWrite> writes = [],
177 list<string> MxList, bit isF = 0,
178 bit isWidening = 0> {
179 if !exists<SchedRead>(name # "_WorstCase") then
180 def : ReadAdvance<!cast<SchedRead>(name # "_WorstCase"), val, writes>;
181 foreach mx = MxList in {
182 foreach sew = SchedSEWSet<mx, isF, isWidening>.val in
183 if !exists<SchedRead>(name # "_" # mx # "_E" # sew) then
184 def : ReadAdvance<!cast<SchedRead>(name # "_" # mx # "_E" # sew), val, writes>;
185 }
186 }
187 // Define classes to define list containing all SchedWrites for each (name, LMUL)
188 // pair for each LMUL in each of the SchedMxList variants above and name in
189 // argument `names`. These classes can be used to construct a list of existing
190 // definitions of writes corresponding to each (name, LMUL) pair, that are needed
191 // by the ReadAdvance. For example:
192 // ```
193 // defm "" : LMULReadAdvance<"ReadVIALUX", 1,
194 // LMULSchedWriteList<["WriteVIMovVX"]>.value>;
195 // ```
196 class LMULSchedWriteListImpl<list<string> names, list<string> MxList> {
197 list<SchedWrite> value = !foldl([]<SchedWrite>,
198 !foreach(name, names,
199 !foreach(mx, MxList, !cast<SchedWrite>(name # "_" # mx))),
200 all, writes, !listconcat(all, writes));
201 }
203 multiclass LMULSchedWrites<string name> : LMULSchedWritesImpl<name, SchedMxList>;
204 multiclass LMULSchedReads<string name> : LMULSchedReadsImpl<name, SchedMxList>;
205 multiclass LMULWriteRes<string name, list<ProcResourceKind> resources>
206 : LMULWriteResImpl<name, resources>;
207 multiclass LMULReadAdvance<string name, int val, list<SchedWrite> writes = []>
208 : LMULReadAdvanceImpl<name, val, writes>;
209 class LMULSchedWriteList<list<string> names> : LMULSchedWriteListImpl<names, SchedMxList>;
211 multiclass LMULSEWSchedWrites<string name> : LMULSEWSchedWritesImpl<name, SchedMxList>;
212 multiclass LMULSEWSchedReads<string name> : LMULSEWSchedReadsImpl<name, SchedMxList>;
213 multiclass LMULSEWWriteRes<string name, list<ProcResourceKind> resources>
214 : LMULSEWWriteResImpl<name, resources, SchedMxList>;
215 multiclass LMULSEWReadAdvance<string name, int val, list<SchedWrite> writes = []>
216 : LMULSEWReadAdvanceImpl<name, val, writes, SchedMxList>;
218 multiclass LMULSEWSchedWritesWRed<string name>
219 : LMULSEWSchedWritesImpl<name, SchedMxListWRed, isWidening=1>;
220 multiclass LMULSEWWriteResWRed<string name, list<ProcResourceKind> resources>
221 : LMULSEWWriteResImpl<name, resources, SchedMxListWRed, isWidening=1>;
223 multiclass LMULSEWSchedWritesFWRed<string name>
224 : LMULSEWSchedWritesImpl<name, SchedMxListFWRed, isF=1, isWidening=1>;
225 multiclass LMULSEWWriteResFWRed<string name, list<ProcResourceKind> resources>
226 : LMULSEWWriteResImpl<name, resources, SchedMxListFWRed, isF=1, isWidening=1>;
228 multiclass LMULSEWSchedWritesF<string name> : LMULSEWSchedWritesImpl<name, SchedMxListF, isF=1>;
229 multiclass LMULSEWSchedReadsF<string name> : LMULSEWSchedReadsImpl<name, SchedMxListF, isF=1>;
230 multiclass LMULSEWWriteResF<string name, list<ProcResourceKind> resources>
231 : LMULSEWWriteResImpl<name, resources, SchedMxListF, isF=1>;
232 multiclass LMULSEWReadAdvanceF<string name, int val, list<SchedWrite> writes = []>
233 : LMULSEWReadAdvanceImpl<name, val, writes, SchedMxListF, isF=1>;
235 multiclass LMULSchedWritesW<string name> : LMULSchedWritesImpl<name, SchedMxListW>;
236 multiclass LMULSchedReadsW<string name> : LMULSchedReadsImpl<name, SchedMxListW>;
237 multiclass LMULWriteResW<string name, list<ProcResourceKind> resources>
238 : LMULWriteResImpl<name, resources>;
239 multiclass LMULReadAdvanceW<string name, int val, list<SchedWrite> writes = []>
240 : LMULReadAdvanceImpl<name, val, writes>;
241 class LMULSchedWriteListW<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListW>;
243 multiclass LMULSchedWritesFW<string name> : LMULSchedWritesImpl<name, SchedMxListFW>;
244 multiclass LMULSchedReadsFW<string name> : LMULSchedReadsImpl<name, SchedMxListFW>;
245 multiclass LMULWriteResFW<string name, list<ProcResourceKind> resources>
246 : LMULWriteResImpl<name, resources>;
247 multiclass LMULReadAdvanceFW<string name, int val, list<SchedWrite> writes = []>
248 : LMULReadAdvanceImpl<name, val, writes>;
249 class LMULSchedWriteListFW<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListFW>;
251 // 3.6 Vector Byte Length vlenb
252 def WriteRdVLENB : SchedWrite;
254 // 6. Configuration-Setting Instructions
255 def WriteVSETVLI : SchedWrite;
256 def WriteVSETIVLI : SchedWrite;
257 def WriteVSETVL : SchedWrite;
259 // 7. Vector Loads and Stores
260 // 7.4. Vector Unit-Stride Instructions
261 defm "" : LMULSchedWrites<"WriteVLDE">;
262 defm "" : LMULSchedWrites<"WriteVSTE">;
263 // 7.4.1. Vector Unit-Strided Mask
264 defm "" : LMULSchedWrites<"WriteVLDM">;
265 defm "" : LMULSchedWrites<"WriteVSTM">;
266 // 7.5. Vector Strided Instructions
267 defm "" : LMULSchedWrites<"WriteVLDS8">;
268 defm "" : LMULSchedWrites<"WriteVLDS16">;
269 defm "" : LMULSchedWrites<"WriteVLDS32">;
270 defm "" : LMULSchedWrites<"WriteVLDS64">;
271 defm "" : LMULSchedWrites<"WriteVSTS8">;
272 defm "" : LMULSchedWrites<"WriteVSTS16">;
273 defm "" : LMULSchedWrites<"WriteVSTS32">;
274 defm "" : LMULSchedWrites<"WriteVSTS64">;
275 // 7.6. Vector Indexed Instructions
276 defm "" : LMULSchedWrites<"WriteVLDUX8">;
277 defm "" : LMULSchedWrites<"WriteVLDUX16">;
278 defm "" : LMULSchedWrites<"WriteVLDUX32">;
279 defm "" : LMULSchedWrites<"WriteVLDUX64">;
280 defm "" : LMULSchedWrites<"WriteVLDOX8">;
281 defm "" : LMULSchedWrites<"WriteVLDOX16">;
282 defm "" : LMULSchedWrites<"WriteVLDOX32">;
283 defm "" : LMULSchedWrites<"WriteVLDOX64">;
284 defm "" : LMULSchedWrites<"WriteVSTUX8">;
285 defm "" : LMULSchedWrites<"WriteVSTUX16">;
286 defm "" : LMULSchedWrites<"WriteVSTUX32">;
287 defm "" : LMULSchedWrites<"WriteVSTUX64">;
288 defm "" : LMULSchedWrites<"WriteVSTOX8">;
289 defm "" : LMULSchedWrites<"WriteVSTOX16">;
290 defm "" : LMULSchedWrites<"WriteVSTOX32">;
291 defm "" : LMULSchedWrites<"WriteVSTOX64">;
292 // 7.7. Vector Unit-stride Fault-Only-First Loads
293 defm "" : LMULSchedWrites<"WriteVLDFF">;
294 // 7.8. Vector Segment Instructions
295 foreach nf=2-8 in {
296 foreach eew = [8, 16, 32, 64] in {
297 defm "" : LMULSchedWrites<"WriteVLSEG" # nf # e # eew>;
298 defm "" : LMULSchedWrites<"WriteVSSEG" # nf # e # eew>;
299 defm "" : LMULSchedWrites<"WriteVLSEGFF" # nf # e # eew>;
300 defm "" : LMULSchedWrites<"WriteVLSSEG" # nf # e # eew>;
301 defm "" : LMULSchedWrites<"WriteVSSSEG" # nf # e # eew>;
302 defm "" : LMULSchedWrites<"WriteVLUXSEG" # nf # e # eew>;
303 defm "" : LMULSchedWrites<"WriteVLOXSEG" # nf # e # eew>;
304 defm "" : LMULSchedWrites<"WriteVSUXSEG" # nf # e # eew>;
305 defm "" : LMULSchedWrites<"WriteVSOXSEG" # nf # e # eew>;
306 }
307 }
308 // 7.9. Vector Whole Register Instructions
309 def WriteVLD1R : SchedWrite;
310 def WriteVLD2R : SchedWrite;
311 def WriteVLD4R : SchedWrite;
312 def WriteVLD8R : SchedWrite;
313 def WriteVST1R : SchedWrite;
314 def WriteVST2R : SchedWrite;
315 def WriteVST4R : SchedWrite;
316 def WriteVST8R : SchedWrite;
318 // 11. Vector Integer Arithmetic Instructions
319 // 11.1. Vector Single-Width Integer Add and Subtract
320 // 11.5. Vector Bitwise Logical Instructions
321 defm "" : LMULSchedWrites<"WriteVIALUV">;
322 defm "" : LMULSchedWrites<"WriteVIALUX">;
323 defm "" : LMULSchedWrites<"WriteVIALUI">;
324 // 11.2. Vector Widening Integer Add/Subtract
325 defm "" : LMULSchedWritesW<"WriteVIWALUV">;
326 defm "" : LMULSchedWritesW<"WriteVIWALUX">;
327 defm "" : LMULSchedWritesW<"WriteVIWALUI">;
328 // 11.3. Vector Integer Extension
329 defm "" : LMULSchedWrites<"WriteVExtV">;
330 // 11.4. Vector Integer Arithmetic with Carry or Borrow Instructions
331 defm "" : LMULSchedWrites<"WriteVICALUV">;
332 defm "" : LMULSchedWrites<"WriteVICALUX">;
333 defm "" : LMULSchedWrites<"WriteVICALUI">;
334 // 11.6. Vector Single-Width Bit Shift Instructions
335 defm "" : LMULSchedWrites<"WriteVShiftV">;
336 defm "" : LMULSchedWrites<"WriteVShiftX">;
337 defm "" : LMULSchedWrites<"WriteVShiftI">;
338 // 11.7. Vector Narrowing Integer Right Shift Instructions
339 defm "" : LMULSchedWritesW<"WriteVNShiftV">;
340 defm "" : LMULSchedWritesW<"WriteVNShiftX">;
341 defm "" : LMULSchedWritesW<"WriteVNShiftI">;
342 // 11.8. Vector Integer Comparison Instructions
343 defm "" : LMULSchedWrites<"WriteVICmpV">;
344 defm "" : LMULSchedWrites<"WriteVICmpX">;
345 defm "" : LMULSchedWrites<"WriteVICmpI">;
346 // 11.9. Vector Integer Min/Max Instructions
347 defm "" : LMULSchedWrites<"WriteVIMinMaxV">;
348 defm "" : LMULSchedWrites<"WriteVIMinMaxX">;
349 // 11.10. Vector Single-Width Integer Multiply Instructions
350 defm "" : LMULSchedWrites<"WriteVIMulV">;
351 defm "" : LMULSchedWrites<"WriteVIMulX">;
352 // 11.11. Vector Integer Divide Instructions
353 defm "" : LMULSEWSchedWrites<"WriteVIDivV">;
354 defm "" : LMULSEWSchedWrites<"WriteVIDivX">;
355 // 11.12. Vector Widening Integer Multiply Instructions
356 defm "" : LMULSchedWritesW<"WriteVIWMulV">;
357 defm "" : LMULSchedWritesW<"WriteVIWMulX">;
358 // 11.13. Vector Single-Width Integer Multiply-Add Instructions
359 defm "" : LMULSchedWrites<"WriteVIMulAddV">;
360 defm "" : LMULSchedWrites<"WriteVIMulAddX">;
361 // 11.14. Vector Widening Integer Multiply-Add Instructions
362 defm "" : LMULSchedWritesW<"WriteVIWMulAddV">;
363 defm "" : LMULSchedWritesW<"WriteVIWMulAddX">;
364 // 11.15. Vector Integer Merge Instructions
365 defm "" : LMULSchedWrites<"WriteVIMergeV">;
366 defm "" : LMULSchedWrites<"WriteVIMergeX">;
367 defm "" : LMULSchedWrites<"WriteVIMergeI">;
368 // 11.16. Vector Integer Move Instructions
369 defm "" : LMULSchedWrites<"WriteVIMovV">;
370 defm "" : LMULSchedWrites<"WriteVIMovX">;
371 defm "" : LMULSchedWrites<"WriteVIMovI">;
373 // 12. Vector Fixed-Point Arithmetic Instructions
374 // 12.1. Vector Single-Width Saturating Add and Subtract
375 defm "" : LMULSchedWrites<"WriteVSALUV">;
376 defm "" : LMULSchedWrites<"WriteVSALUX">;
377 defm "" : LMULSchedWrites<"WriteVSALUI">;
378 // 12.2. Vector Single-Width Averaging Add and Subtract
379 defm "" : LMULSchedWrites<"WriteVAALUV">;
380 defm "" : LMULSchedWrites<"WriteVAALUX">;
381 // 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
382 defm "" : LMULSchedWrites<"WriteVSMulV">;
383 defm "" : LMULSchedWrites<"WriteVSMulX">;
384 // 12.4. Vector Single-Width Scaling Shift Instructions
385 defm "" : LMULSchedWrites<"WriteVSShiftV">;
386 defm "" : LMULSchedWrites<"WriteVSShiftX">;
387 defm "" : LMULSchedWrites<"WriteVSShiftI">;
388 // 12.5. Vector Narrowing Fixed-Point Clip Instructions
389 defm "" : LMULSchedWritesW<"WriteVNClipV">;
390 defm "" : LMULSchedWritesW<"WriteVNClipX">;
391 defm "" : LMULSchedWritesW<"WriteVNClipI">;
393 // 13. Vector Floating-Point Instructions
394 // 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
395 defm "" : LMULSchedWrites<"WriteVFALUV">;
396 defm "" : LMULSchedWrites<"WriteVFALUF">;
397 // 13.3. Vector Widening Floating-Point Add/Subtract Instructions
398 defm "" : LMULSchedWritesFW<"WriteVFWALUV">;
399 defm "" : LMULSchedWritesFW<"WriteVFWALUF">;
400 // 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
401 defm "" : LMULSchedWrites<"WriteVFMulV">;
402 defm "" : LMULSchedWrites<"WriteVFMulF">;
403 defm "" : LMULSEWSchedWritesF<"WriteVFDivV">;
404 defm "" : LMULSEWSchedWritesF<"WriteVFDivF">;
405 // 13.5. Vector Widening Floating-Point Multiply
406 defm "" : LMULSchedWritesFW<"WriteVFWMulV">;
407 defm "" : LMULSchedWritesFW<"WriteVFWMulF">;
408 // 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
409 defm "" : LMULSchedWrites<"WriteVFMulAddV">;
410 defm "" : LMULSchedWrites<"WriteVFMulAddF">;
411 // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
412 defm "" : LMULSchedWritesFW<"WriteVFWMulAddV">;
413 defm "" : LMULSchedWritesFW<"WriteVFWMulAddF">;
414 // 13.8. Vector Floating-Point Square-Root Instruction
415 defm "" : LMULSEWSchedWritesF<"WriteVFSqrtV">;
416 // 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
417 // 13.10. Vector Floating-Point Reciprocal Estimate Instruction
418 defm "" : LMULSchedWrites<"WriteVFRecpV">;
419 // 13.11. Vector Floating-Point MIN/MAX Instructions
420 defm "" : LMULSchedWrites<"WriteVFMinMaxV">;
421 defm "" : LMULSchedWrites<"WriteVFMinMaxF">;
422 // 13.12. Vector Floating-Point Sign-Injection Instructions
423 defm "" : LMULSchedWrites<"WriteVFSgnjV">;
424 defm "" : LMULSchedWrites<"WriteVFSgnjF">;
425 // 13.13. Vector Floating-Point Compare Instructions
426 defm "" : LMULSchedWrites<"WriteVFCmpV">;
427 defm "" : LMULSchedWrites<"WriteVFCmpF">;
428 // 13.14. Vector Floating-Point Classify Instruction
429 defm "" : LMULSchedWrites<"WriteVFClassV">;
430 // 13.15. Vector Floating-Point Merge Instruction
431 defm "" : LMULSchedWrites<"WriteVFMergeV">;
432 // 13.16. Vector Floating-Point Move Instruction
433 defm "" : LMULSchedWrites<"WriteVFMovV">;
434 // 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions
435 defm "" : LMULSchedWrites<"WriteVFCvtIToFV">;
436 defm "" : LMULSchedWrites<"WriteVFCvtFToIV">;
437 // 13.18. Widening Floating-Point/Integer Type-Convert Instructions
438 defm "" : LMULSchedWritesW<"WriteVFWCvtIToFV">;
439 defm "" : LMULSchedWritesFW<"WriteVFWCvtFToIV">;
440 defm "" : LMULSchedWritesFW<"WriteVFWCvtFToFV">;
441 // 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
442 defm "" : LMULSchedWritesFW<"WriteVFNCvtIToFV">;
443 defm "" : LMULSchedWritesW<"WriteVFNCvtFToIV">;
444 defm "" : LMULSchedWritesFW<"WriteVFNCvtFToFV">;
446 // 14. Vector Reduction Operations
447 // The latency of reduction is determined by the size of the read resource.
448 // The LMUL range of read resource(VS2) for reduction operantion is between
449 // MF8 and M8. Use the _From suffix to indicate the number of the
450 // LMUL from VS2.
451 // 14.1. Vector Single-Width Integer Reduction Instructions
452 defm "" : LMULSEWSchedWrites<"WriteVIRedV_From">;
453 defm "" : LMULSEWSchedWrites<"WriteVIRedMinMaxV_From">;
454 // 14.2. Vector Widening Integer Reduction Instructions
455 defm "" : LMULSEWSchedWritesWRed<"WriteVIWRedV_From">;
456 // 14.3. Vector Single-Width Floating-Point Reduction Instructions
457 defm "" : LMULSEWSchedWritesF<"WriteVFRedV_From">;
458 defm "" : LMULSEWSchedWritesF<"WriteVFRedOV_From">;
459 defm "" : LMULSEWSchedWritesF<"WriteVFRedMinMaxV_From">;
460 // 14.4. Vector Widening Floating-Point Reduction Instructions
461 defm "" : LMULSEWSchedWritesFWRed<"WriteVFWRedV_From">;
462 defm "" : LMULSEWSchedWritesFWRed<"WriteVFWRedOV_From">;
464 // 15. Vector Mask Instructions
465 // 15.1. Vector Mask-Register Logical Instructions
466 defm "" : LMULSchedWrites<"WriteVMALUV">;
467 // 15.2. Vector Mask Population Count
468 defm "" : LMULSchedWrites<"WriteVMPopV">;
469 // 15.3. Vector Find-First-Set Mask Bit
470 defm "" : LMULSchedWrites<"WriteVMFFSV">;
471 // 15.4. Vector Set-Before-First Mask Bit
472 // 15.5. Vector Set-Including-First Mask Bit
473 // 15.6. Vector Set-only-First Mask Bit
474 defm "" : LMULSchedWrites<"WriteVMSFSV">;
475 // 15.8. Vector Iota Instruction
476 defm "" : LMULSchedWrites<"WriteVMIotV">;
477 // 15.9. Vector Element Index Instruction
478 defm "" : LMULSchedWrites<"WriteVMIdxV">;
480 // 16. Vector Permutation Instructions
481 // 16.1. Integer Scalar Move Instructions
482 def WriteVIMovVX : SchedWrite;
483 def WriteVIMovXV : SchedWrite;
484 // 16.2. Floating-Point Scalar Move Instructions
485 def WriteVFMovVF : SchedWrite;
486 def WriteVFMovFV : SchedWrite;
487 // 16.3. Vector Slide Instructions
488 defm "" : LMULSchedWrites<"WriteVISlideX">;
489 defm "" : LMULSchedWrites<"WriteVISlideI">;
490 defm "" : LMULSchedWrites<"WriteVISlide1X">;
491 defm "" : LMULSchedWrites<"WriteVFSlide1F">;
492 // 16.4. Vector Register Gather Instructions
493 defm "" : LMULSEWSchedWrites<"WriteVRGatherVV">;
494 defm "" : LMULSchedWrites<"WriteVRGatherVX">;
495 defm "" : LMULSchedWrites<"WriteVRGatherVI">;
496 // 16.5. Vector Compress Instruction
497 defm "" : LMULSEWSchedWrites<"WriteVCompressV">;
498 // 16.6. Whole Vector Register Move
499 // These are already LMUL aware
500 def WriteVMov1V : SchedWrite;
501 def WriteVMov2V : SchedWrite;
502 def WriteVMov4V : SchedWrite;
503 def WriteVMov8V : SchedWrite;
505 //===----------------------------------------------------------------------===//
506 /// Define scheduler resources associated with use operands.
508 // 6. Configuration-Setting Instructions
509 def ReadVSETVLI : SchedRead;
510 def ReadVSETVL : SchedRead;
512 // 7. Vector Loads and Stores
513 def ReadVLDX : SchedRead;
514 def ReadVSTX : SchedRead;
515 // 7.4. Vector Unit-Stride Instructions
516 defm "" : LMULSchedReads<"ReadVSTEV">;
517 // 7.4.1. Vector Unit-Strided Mask
518 defm "" : LMULSchedReads<"ReadVSTM">;
519 // 7.5. Vector Strided Instructions
520 def ReadVLDSX : SchedRead;
521 def ReadVSTSX : SchedRead;
522 defm "" : LMULSchedReads<"ReadVSTS8V">;
523 defm "" : LMULSchedReads<"ReadVSTS16V">;
524 defm "" : LMULSchedReads<"ReadVSTS32V">;
525 defm "" : LMULSchedReads<"ReadVSTS64V">;
526 // 7.6. Vector Indexed Instructions
527 defm "" : LMULSchedReads<"ReadVLDUXV">;
528 defm "" : LMULSchedReads<"ReadVLDOXV">;
529 defm "" : LMULSchedReads<"ReadVSTUX8">;
530 defm "" : LMULSchedReads<"ReadVSTUX16">;
531 defm "" : LMULSchedReads<"ReadVSTUX32">;
532 defm "" : LMULSchedReads<"ReadVSTUX64">;
533 defm "" : LMULSchedReads<"ReadVSTUXV">;
534 defm "" : LMULSchedReads<"ReadVSTUX8V">;
535 defm "" : LMULSchedReads<"ReadVSTUX16V">;
536 defm "" : LMULSchedReads<"ReadVSTUX32V">;
537 defm "" : LMULSchedReads<"ReadVSTUX64V">;
538 defm "" : LMULSchedReads<"ReadVSTOX8">;
539 defm "" : LMULSchedReads<"ReadVSTOX16">;
540 defm "" : LMULSchedReads<"ReadVSTOX32">;
541 defm "" : LMULSchedReads<"ReadVSTOX64">;
542 defm "" : LMULSchedReads<"ReadVSTOXV">;
543 defm "" : LMULSchedReads<"ReadVSTOX8V">;
544 defm "" : LMULSchedReads<"ReadVSTOX16V">;
545 defm "" : LMULSchedReads<"ReadVSTOX32V">;
546 defm "" : LMULSchedReads<"ReadVSTOX64V">;
547 // 7.9. Vector Whole Register Instructions
548 // These are already LMUL aware
549 def ReadVST1R : SchedRead;
550 def ReadVST2R : SchedRead;
551 def ReadVST4R : SchedRead;
552 def ReadVST8R : SchedRead;
554 // 11. Vector Integer Arithmetic Instructions
555 // 11.1. Vector Single-Width Integer Add and Subtract
556 // 11.5. Vector Bitwise Logical Instructions
557 defm "" : LMULSchedReads<"ReadVIALUV">;
558 defm "" : LMULSchedReads<"ReadVIALUX">;
559 // 11.2. Vector Widening Integer Add/Subtract
560 defm "" : LMULSchedReadsW<"ReadVIWALUV">;
561 defm "" : LMULSchedReadsW<"ReadVIWALUX">;
562 // 11.3. Vector Integer Extension
563 defm "" : LMULSchedReads<"ReadVExtV">;
564 // 11.4. Vector Integer Arithmetic with Carry or Borrow Instructions
565 defm "" : LMULSchedReads<"ReadVICALUV">;
566 defm "" : LMULSchedReads<"ReadVICALUX">;
567 // 11.6. Vector Single-Width Bit Shift Instructions
568 defm "" : LMULSchedReads<"ReadVShiftV">;
569 defm "" : LMULSchedReads<"ReadVShiftX">;
570 // 11.7. Vector Narrowing Integer Right Shift Instructions
571 defm "" : LMULSchedReadsW<"ReadVNShiftV">;
572 defm "" : LMULSchedReadsW<"ReadVNShiftX">;
573 // 11.8. Vector Integer Comparison Instructions
574 defm "" : LMULSchedReads<"ReadVICmpV">;
575 defm "" : LMULSchedReads<"ReadVICmpX">;
576 // 11.9. Vector Integer Min/Max Instructions
577 defm "" : LMULSchedReads<"ReadVIMinMaxV">;
578 defm "" : LMULSchedReads<"ReadVIMinMaxX">;
579 // 11.10. Vector Single-Width Integer Multiply Instructions
580 defm "" : LMULSchedReads<"ReadVIMulV">;
581 defm "" : LMULSchedReads<"ReadVIMulX">;
582 // 11.11. Vector Integer Divide Instructions
583 defm "" : LMULSEWSchedReads<"ReadVIDivV">;
584 defm "" : LMULSEWSchedReads<"ReadVIDivX">;
585 // 11.12. Vector Widening Integer Multiply Instructions
586 defm "" : LMULSchedReadsW<"ReadVIWMulV">;
587 defm "" : LMULSchedReadsW<"ReadVIWMulX">;
588 // 11.13. Vector Single-Width Integer Multiply-Add Instructions
589 defm "" : LMULSchedReads<"ReadVIMulAddV">;
590 defm "" : LMULSchedReads<"ReadVIMulAddX">;
591 // 11.14. Vector Widening Integer Multiply-Add Instructions
592 defm "" : LMULSchedReadsW<"ReadVIWMulAddV">;
593 defm "" : LMULSchedReadsW<"ReadVIWMulAddX">;
594 // 11.15. Vector Integer Merge Instructions
595 defm "" : LMULSchedReads<"ReadVIMergeV">;
596 defm "" : LMULSchedReads<"ReadVIMergeX">;
597 // 11.16. Vector Integer Move Instructions
598 defm "" : LMULSchedReads<"ReadVIMovV">;
599 defm "" : LMULSchedReads<"ReadVIMovX">;
601 // 12. Vector Fixed-Point Arithmetic Instructions
602 // 12.1. Vector Single-Width Saturating Add and Subtract
603 defm "" : LMULSchedReads<"ReadVSALUV">;
604 defm "" : LMULSchedReads<"ReadVSALUX">;
605 // 12.2. Vector Single-Width Averaging Add and Subtract
606 defm "" : LMULSchedReads<"ReadVAALUV">;
607 defm "" : LMULSchedReads<"ReadVAALUX">;
608 // 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
609 defm "" : LMULSchedReads<"ReadVSMulV">;
610 defm "" : LMULSchedReads<"ReadVSMulX">;
611 // 12.4. Vector Single-Width Scaling Shift Instructions
612 defm "" : LMULSchedReads<"ReadVSShiftV">;
613 defm "" : LMULSchedReads<"ReadVSShiftX">;
614 // 12.5. Vector Narrowing Fixed-Point Clip Instructions
615 defm "" : LMULSchedReadsW<"ReadVNClipV">;
616 defm "" : LMULSchedReadsW<"ReadVNClipX">;
618 // 13. Vector Floating-Point Instructions
619 // 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
620 defm "" : LMULSchedReads<"ReadVFALUV">;
621 defm "" : LMULSchedReads<"ReadVFALUF">;
622 // 13.3. Vector Widening Floating-Point Add/Subtract Instructions
623 defm "" : LMULSchedReadsFW<"ReadVFWALUV">;
624 defm "" : LMULSchedReadsFW<"ReadVFWALUF">;
625 // 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
626 defm "" : LMULSchedReads<"ReadVFMulV">;
627 defm "" : LMULSchedReads<"ReadVFMulF">;
628 defm "" : LMULSEWSchedReadsF<"ReadVFDivV">;
629 defm "" : LMULSEWSchedReadsF<"ReadVFDivF">;
630 // 13.5. Vector Widening Floating-Point Multiply
631 defm "" : LMULSchedReadsFW<"ReadVFWMulV">;
632 defm "" : LMULSchedReadsFW<"ReadVFWMulF">;
633 // 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
634 defm "" : LMULSchedReads<"ReadVFMulAddV">;
635 defm "" : LMULSchedReads<"ReadVFMulAddF">;
636 // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
637 defm "" : LMULSchedReadsFW<"ReadVFWMulAddV">;
638 defm "" : LMULSchedReadsFW<"ReadVFWMulAddF">;
639 // 13.8. Vector Floating-Point Square-Root Instruction
640 defm "" : LMULSEWSchedReadsF<"ReadVFSqrtV">;
641 // 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
642 // 13.10. Vector Floating-Point Reciprocal Estimate Instruction
643 defm "" : LMULSchedReads<"ReadVFRecpV">;
644 // 13.11. Vector Floating-Point MIN/MAX Instructions
645 defm "" : LMULSchedReads<"ReadVFMinMaxV">;
646 defm "" : LMULSchedReads<"ReadVFMinMaxF">;
647 // 13.12. Vector Floating-Point Sign-Injection Instructions
648 defm "" : LMULSchedReads<"ReadVFSgnjV">;
649 defm "" : LMULSchedReads<"ReadVFSgnjF">;
650 // 13.13. Vector Floating-Point Compare Instructions
651 defm "" : LMULSchedReads<"ReadVFCmpV">;
652 defm "" : LMULSchedReads<"ReadVFCmpF">;
653 // 13.14. Vector Floating-Point Classify Instruction
654 defm "" : LMULSchedReads<"ReadVFClassV">;
655 // 13.15. Vector Floating-Point Merge Instruction
656 defm "" : LMULSchedReads<"ReadVFMergeV">;
657 defm "" : LMULSchedReads<"ReadVFMergeF">;
658 // 13.16. Vector Floating-Point Move Instruction
659 defm "" : LMULSchedReads<"ReadVFMovF">;
660 // 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions
661 defm "" : LMULSchedReads<"ReadVFCvtIToFV">;
662 defm "" : LMULSchedReads<"ReadVFCvtFToIV">;
663 // 13.18. Widening Floating-Point/Integer Type-Convert Instructions
664 defm "" : LMULSchedReadsW<"ReadVFWCvtIToFV">;
665 defm "" : LMULSchedReadsFW<"ReadVFWCvtFToIV">;
666 defm "" : LMULSchedReadsFW<"ReadVFWCvtFToFV">;
667 // 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
668 defm "" : LMULSchedReadsFW<"ReadVFNCvtIToFV">;
669 defm "" : LMULSchedReadsW<"ReadVFNCvtFToIV">;
670 defm "" : LMULSchedReadsFW<"ReadVFNCvtFToFV">;
672 // 14. Vector Reduction Operations
673 // 14.1. Vector Single-Width Integer Reduction Instructions
674 def ReadVIRedV : SchedRead;
675 def ReadVIRedV0 : SchedRead;
676 // 14.2. Vector Widening Integer Reduction Instructions
677 def ReadVIWRedV : SchedRead;
678 def ReadVIWRedV0 : SchedRead;
679 // 14.3. Vector Single-Width Floating-Point Reduction Instructions
680 def ReadVFRedV : SchedRead;
681 def ReadVFRedV0 : SchedRead;
682 def ReadVFRedOV : SchedRead;
683 def ReadVFRedOV0 : SchedRead;
684 def ReadVFRedMinMaxV : SchedRead;
685 // 14.4. Vector Widening Floating-Point Reduction Instructions
686 def ReadVFWRedV : SchedRead;
687 def ReadVFWRedV0 : SchedRead;
688 def ReadVFWRedOV : SchedRead;
689 def ReadVFWRedOV0 : SchedRead;
691 // 15. Vector Mask Instructions
692 // 15.1. Vector Mask-Register Logical Instructions
693 defm "" : LMULSchedReads<"ReadVMALUV">;
694 // 15.2. Vector Mask Population Count
695 defm "" : LMULSchedReads<"ReadVMPopV">;
696 // 15.3. Vector Find-First-Set Mask Bit
697 defm "" : LMULSchedReads<"ReadVMFFSV">;
698 // 15.4. Vector Set-Before-First Mask Bit
699 // 15.5. Vector Set-Including-First Mask Bit
700 // 15.6. Vector Set-only-First Mask Bit
701 defm "" : LMULSchedReads<"ReadVMSFSV">;
702 // 15.8. Vector Iota Instruction
703 defm "" : LMULSchedReads<"ReadVMIotV">;
705 // 16. Vector Permutation Instructions
706 // 16.1. Integer Scalar Move Instructions
707 def ReadVIMovVX : SchedRead;
708 def ReadVIMovXV : SchedRead;
709 def ReadVIMovXX : SchedRead;
710 // 16.2. Floating-Point Scalar Move Instructions
711 def ReadVFMovVF : SchedRead;
712 def ReadVFMovFV : SchedRead;
713 def ReadVFMovFX : SchedRead;
714 // 16.3. Vector Slide Instructions
715 defm "" : LMULSchedReads<"ReadVISlideV">;
716 defm "" : LMULSchedReads<"ReadVISlideX">;
717 defm "" : LMULSchedReads<"ReadVFSlideV">;
718 defm "" : LMULSchedReads<"ReadVFSlideF">;
719 // 16.4. Vector Register Gather Instructions
720 defm "" : LMULSEWSchedReads<"ReadVRGatherVV_data">;
721 defm "" : LMULSEWSchedReads<"ReadVRGatherVV_index">;
722 defm "" : LMULSchedReads<"ReadVRGatherVX_data">;
723 defm "" : LMULSchedReads<"ReadVRGatherVX_index">;
724 defm "" : LMULSchedReads<"ReadVRGatherVI_data">;
725 // 16.5. Vector Compress Instruction
726 defm "" : LMULSEWSchedReads<"ReadVCompressV">;
727 // 16.6. Whole Vector Register Move
728 // These are already LMUL aware
729 def ReadVMov1V : SchedRead;
730 def ReadVMov2V : SchedRead;
731 def ReadVMov4V : SchedRead;
732 def ReadVMov8V : SchedRead;
734 // Others
735 def ReadVMask : SchedRead;
736 def ReadVMergeOp_WorstCase : SchedRead;
737 foreach mx = SchedMxList in {
738 def ReadVMergeOp_ # mx : SchedRead;
739 foreach sew = SchedSEWSet<mx>.val in
740 def ReadVMergeOp_ # mx # "_E" # sew : SchedRead;
741 }
743 //===----------------------------------------------------------------------===//
744 /// Define default scheduler resources for V.
746 multiclass UnsupportedSchedV {
747 let Unsupported = true in {
749 // 3.6 Vector Byte Length vlenb
750 def : WriteRes<WriteRdVLENB, []>;
752 // 6. Configuration-Setting Instructions
753 def : WriteRes<WriteVSETVLI, []>;
754 def : WriteRes<WriteVSETIVLI, []>;
755 def : WriteRes<WriteVSETVL, []>;
757 // 7. Vector Loads and Stores
758 defm "" : LMULWriteRes<"WriteVLDE", []>;
759 defm "" : LMULWriteRes<"WriteVSTE", []>;
760 defm "" : LMULWriteRes<"WriteVLDM", []>;
761 defm "" : LMULWriteRes<"WriteVSTM", []>;
762 defm "" : LMULWriteRes<"WriteVLDS8", []>;
763 defm "" : LMULWriteRes<"WriteVLDS16", []>;
764 defm "" : LMULWriteRes<"WriteVLDS32", []>;
765 defm "" : LMULWriteRes<"WriteVLDS64", []>;
766 defm "" : LMULWriteRes<"WriteVSTS8", []>;
767 defm "" : LMULWriteRes<"WriteVSTS16", []>;
768 defm "" : LMULWriteRes<"WriteVSTS32", []>;
769 defm "" : LMULWriteRes<"WriteVSTS64", []>;
770 defm "" : LMULWriteRes<"WriteVLDUX8", []>;
771 defm "" : LMULWriteRes<"WriteVLDUX16", []>;
772 defm "" : LMULWriteRes<"WriteVLDUX32", []>;
773 defm "" : LMULWriteRes<"WriteVLDUX64", []>;
774 defm "" : LMULWriteRes<"WriteVLDOX8", []>;
775 defm "" : LMULWriteRes<"WriteVLDOX16", []>;
776 defm "" : LMULWriteRes<"WriteVLDOX32", []>;
777 defm "" : LMULWriteRes<"WriteVLDOX64", []>;
778 defm "" : LMULWriteRes<"WriteVSTUX8", []>;
779 defm "" : LMULWriteRes<"WriteVSTUX16", []>;
780 defm "" : LMULWriteRes<"WriteVSTUX32", []>;
781 defm "" : LMULWriteRes<"WriteVSTUX64", []>;
782 defm "" : LMULWriteRes<"WriteVSTOX8", []>;
783 defm "" : LMULWriteRes<"WriteVSTOX16", []>;
784 defm "" : LMULWriteRes<"WriteVSTOX32", []>;
785 defm "" : LMULWriteRes<"WriteVSTOX64", []>;
786 defm "" : LMULWriteRes<"WriteVLDFF", []>;
787 // These are already LMUL aware
788 def : WriteRes<WriteVLD1R, []>;
789 def : WriteRes<WriteVLD2R, []>;
790 def : WriteRes<WriteVLD4R, []>;
791 def : WriteRes<WriteVLD8R, []>;
792 def : WriteRes<WriteVST1R, []>;
793 def : WriteRes<WriteVST2R, []>;
794 def : WriteRes<WriteVST4R, []>;
795 def : WriteRes<WriteVST8R, []>;
796 // Vector Segment Loads and Stores
797 foreach nf=2-8 in {
798 foreach eew = [8, 16, 32, 64] in {
799 defm "" : LMULWriteRes <"WriteVLSEG" # nf # "e" # eew, []>;
800 defm "" : LMULWriteRes <"WriteVLSEGFF" # nf # "e" # eew, []>;
801 defm "" : LMULWriteRes <"WriteVSSEG" # nf # "e" # eew, []>;
802 defm "" : LMULWriteRes <"WriteVLSSEG" # nf # "e" # eew, []>;
803 defm "" : LMULWriteRes <"WriteVSSSEG" # nf # "e" # eew, []>;
804 defm "" : LMULWriteRes <"WriteVLUXSEG" # nf # "e" # eew, []>;
805 defm "" : LMULWriteRes <"WriteVLOXSEG" # nf # "e" # eew, []>;
806 defm "" : LMULWriteRes <"WriteVSUXSEG" # nf # "e" # eew, []>;
807 defm "" : LMULWriteRes <"WriteVSOXSEG" # nf # "e" # eew, []>;
808 }
809 }
811 // 11. Vector Integer Arithmetic Instructions
812 defm "" : LMULWriteRes<"WriteVIALUV", []>;
813 defm "" : LMULWriteRes<"WriteVIALUX", []>;
814 defm "" : LMULWriteRes<"WriteVIALUI", []>;
815 defm "" : LMULWriteResW<"WriteVIWALUV", []>;
816 defm "" : LMULWriteResW<"WriteVIWALUX", []>;
817 defm "" : LMULWriteResW<"WriteVIWALUI", []>;
818 defm "" : LMULWriteRes<"WriteVExtV", []>;
819 defm "" : LMULWriteRes<"WriteVICALUV", []>;
820 defm "" : LMULWriteRes<"WriteVICALUX", []>;
821 defm "" : LMULWriteRes<"WriteVICALUI", []>;
822 defm "" : LMULWriteRes<"WriteVShiftV", []>;
823 defm "" : LMULWriteRes<"WriteVShiftX", []>;
824 defm "" : LMULWriteRes<"WriteVShiftI", []>;
825 defm "" : LMULWriteResW<"WriteVNShiftV", []>;
826 defm "" : LMULWriteResW<"WriteVNShiftX", []>;
827 defm "" : LMULWriteResW<"WriteVNShiftI", []>;
828 defm "" : LMULWriteRes<"WriteVICmpV", []>;
829 defm "" : LMULWriteRes<"WriteVICmpX", []>;
830 defm "" : LMULWriteRes<"WriteVICmpI", []>;
831 defm "" : LMULWriteRes<"WriteVIMinMaxV", []>;
832 defm "" : LMULWriteRes<"WriteVIMinMaxX", []>;
833 defm "" : LMULWriteRes<"WriteVIMulV", []>;
834 defm "" : LMULWriteRes<"WriteVIMulX", []>;
835 defm "" : LMULSEWWriteRes<"WriteVIDivV", []>;
836 defm "" : LMULSEWWriteRes<"WriteVIDivX", []>;
837 defm "" : LMULWriteResW<"WriteVIWMulV", []>;
838 defm "" : LMULWriteResW<"WriteVIWMulX", []>;
839 defm "" : LMULWriteRes<"WriteVIMulAddV", []>;
840 defm "" : LMULWriteRes<"WriteVIMulAddX", []>;
841 defm "" : LMULWriteResW<"WriteVIWMulAddV", []>;
842 defm "" : LMULWriteResW<"WriteVIWMulAddX", []>;
843 defm "" : LMULWriteRes<"WriteVIMergeV", []>;
844 defm "" : LMULWriteRes<"WriteVIMergeX", []>;
845 defm "" : LMULWriteRes<"WriteVIMergeI", []>;
846 defm "" : LMULWriteRes<"WriteVIMovV", []>;
847 defm "" : LMULWriteRes<"WriteVIMovX", []>;
848 defm "" : LMULWriteRes<"WriteVIMovI", []>;
850 // 12. Vector Fixed-Point Arithmetic Instructions
851 defm "" : LMULWriteRes<"WriteVSALUV", []>;
852 defm "" : LMULWriteRes<"WriteVSALUX", []>;
853 defm "" : LMULWriteRes<"WriteVSALUI", []>;
854 defm "" : LMULWriteRes<"WriteVAALUV", []>;
855 defm "" : LMULWriteRes<"WriteVAALUX", []>;
856 defm "" : LMULWriteRes<"WriteVSMulV", []>;
857 defm "" : LMULWriteRes<"WriteVSMulX", []>;
858 defm "" : LMULWriteRes<"WriteVSShiftV", []>;
859 defm "" : LMULWriteRes<"WriteVSShiftX", []>;
860 defm "" : LMULWriteRes<"WriteVSShiftI", []>;
861 defm "" : LMULWriteResW<"WriteVNClipV", []>;
862 defm "" : LMULWriteResW<"WriteVNClipX", []>;
863 defm "" : LMULWriteResW<"WriteVNClipI", []>;
865 // 13. Vector Floating-Point Instructions
866 defm "" : LMULWriteRes<"WriteVFALUV", []>;
867 defm "" : LMULWriteRes<"WriteVFALUF", []>;
868 defm "" : LMULWriteResFW<"WriteVFWALUV", []>;
869 defm "" : LMULWriteResFW<"WriteVFWALUF", []>;
870 defm "" : LMULWriteRes<"WriteVFMulV", []>;
871 defm "" : LMULWriteRes<"WriteVFMulF", []>;
872 defm "" : LMULSEWWriteResF<"WriteVFDivV", []>;
873 defm "" : LMULSEWWriteResF<"WriteVFDivF", []>;
874 defm "" : LMULWriteResFW<"WriteVFWMulV", []>;
875 defm "" : LMULWriteResFW<"WriteVFWMulF", []>;
876 defm "" : LMULWriteRes<"WriteVFMulAddV", []>;
877 defm "" : LMULWriteRes<"WriteVFMulAddF", []>;
878 defm "" : LMULWriteResFW<"WriteVFWMulAddV", []>;
879 defm "" : LMULWriteResFW<"WriteVFWMulAddF", []>;
880 defm "" : LMULSEWWriteResF<"WriteVFSqrtV", []>;
881 defm "" : LMULWriteRes<"WriteVFRecpV", []>;
882 defm "" : LMULWriteRes<"WriteVFMinMaxV", []>;
883 defm "" : LMULWriteRes<"WriteVFMinMaxF", []>;
884 defm "" : LMULWriteRes<"WriteVFSgnjV", []>;
885 defm "" : LMULWriteRes<"WriteVFSgnjF", []>;
886 defm "" : LMULWriteRes<"WriteVFCmpV", []>;
887 defm "" : LMULWriteRes<"WriteVFCmpF", []>;
888 defm "" : LMULWriteRes<"WriteVFClassV", []>;
889 defm "" : LMULWriteRes<"WriteVFMergeV", []>;
890 defm "" : LMULWriteRes<"WriteVFMovV", []>;
891 defm "" : LMULWriteRes<"WriteVFCvtIToFV", []>;
892 defm "" : LMULWriteRes<"WriteVFCvtFToIV", []>;
893 defm "" : LMULWriteResW<"WriteVFWCvtIToFV", []>;
894 defm "" : LMULWriteResFW<"WriteVFWCvtFToIV", []>;
895 defm "" : LMULWriteResFW<"WriteVFWCvtFToFV", []>;
896 defm "" : LMULWriteResFW<"WriteVFNCvtIToFV", []>;
897 defm "" : LMULWriteResW<"WriteVFNCvtFToIV", []>;
898 defm "" : LMULWriteResFW<"WriteVFNCvtFToFV", []>;
900 // 14. Vector Reduction Operations
901 defm "" : LMULSEWWriteRes<"WriteVIRedV_From", []>;
902 defm "" : LMULSEWWriteRes<"WriteVIRedMinMaxV_From", []>;
903 defm "" : LMULSEWWriteResWRed<"WriteVIWRedV_From", []>;
904 defm "" : LMULSEWWriteResF<"WriteVFRedV_From", []>;
905 defm "" : LMULSEWWriteResF<"WriteVFRedOV_From", []>;
906 defm "" : LMULSEWWriteResF<"WriteVFRedMinMaxV_From", []>;
907 defm "" : LMULSEWWriteResFWRed<"WriteVFWRedV_From", []>;
908 defm "" : LMULSEWWriteResFWRed<"WriteVFWRedOV_From", []>;
910 // 15. Vector Mask Instructions
911 defm "" : LMULWriteRes<"WriteVMALUV", []>;
912 defm "" : LMULWriteRes<"WriteVMPopV", []>;
913 defm "" : LMULWriteRes<"WriteVMFFSV", []>;
914 defm "" : LMULWriteRes<"WriteVMSFSV", []>;
915 defm "" : LMULWriteRes<"WriteVMIotV", []>;
916 defm "" : LMULWriteRes<"WriteVMIdxV", []>;
918 // 16. Vector Permutation Instructions
919 def : WriteRes<WriteVIMovVX, []>;
920 def : WriteRes<WriteVIMovXV, []>;
921 def : WriteRes<WriteVFMovVF, []>;
922 def : WriteRes<WriteVFMovFV, []>;
923 defm "" : LMULWriteRes<"WriteVISlideX", []>;
924 defm "" : LMULWriteRes<"WriteVISlideI", []>;
925 defm "" : LMULWriteRes<"WriteVISlide1X", []>;
926 defm "" : LMULWriteRes<"WriteVFSlide1F", []>;
927 defm "" : LMULSEWWriteRes<"WriteVRGatherVV", []>;
928 defm "" : LMULWriteRes<"WriteVRGatherVX", []>;
929 defm "" : LMULWriteRes<"WriteVRGatherVI", []>;
930 defm "" : LMULSEWWriteRes<"WriteVCompressV", []>;
931 // These are already LMUL aware
932 def : WriteRes<WriteVMov1V, []>;
933 def : WriteRes<WriteVMov2V, []>;
934 def : WriteRes<WriteVMov4V, []>;
935 def : WriteRes<WriteVMov8V, []>;
937 // 6. Configuration-Setting Instructions
938 def : ReadAdvance<ReadVSETVLI, 0>;
939 def : ReadAdvance<ReadVSETVL, 0>;
941 // 7. Vector Loads and Stores
942 def : ReadAdvance<ReadVLDX, 0>;
943 def : ReadAdvance<ReadVSTX, 0>;
944 defm "" : LMULReadAdvance<"ReadVSTEV", 0>;
945 defm "" : LMULReadAdvance<"ReadVSTM", 0>;
946 def : ReadAdvance<ReadVLDSX, 0>;
947 def : ReadAdvance<ReadVSTSX, 0>;
948 defm "" : LMULReadAdvance<"ReadVSTS8V", 0>;
949 defm "" : LMULReadAdvance<"ReadVSTS16V", 0>;
950 defm "" : LMULReadAdvance<"ReadVSTS32V", 0>;
951 defm "" : LMULReadAdvance<"ReadVSTS64V", 0>;
952 defm "" : LMULReadAdvance<"ReadVLDUXV", 0>;
953 defm "" : LMULReadAdvance<"ReadVLDOXV", 0>;
954 defm "" : LMULReadAdvance<"ReadVSTUXV", 0>;
955 defm "" : LMULReadAdvance<"ReadVSTUX8", 0>;
956 defm "" : LMULReadAdvance<"ReadVSTUX16", 0>;
957 defm "" : LMULReadAdvance<"ReadVSTUX32", 0>;
958 defm "" : LMULReadAdvance<"ReadVSTUX64", 0>;
959 defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>;
960 defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>;
961 defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>;
962 defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>;
963 defm "" : LMULReadAdvance<"ReadVSTOX8", 0>;
964 defm "" : LMULReadAdvance<"ReadVSTOX16", 0>;
965 defm "" : LMULReadAdvance<"ReadVSTOX32", 0>;
966 defm "" : LMULReadAdvance<"ReadVSTOX64", 0>;
967 defm "" : LMULReadAdvance<"ReadVSTOXV", 0>;
968 defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>;
969 defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>;
970 defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>;
971 defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>;
972 // These are already LMUL aware
973 def : ReadAdvance<ReadVST1R, 0>;
974 def : ReadAdvance<ReadVST2R, 0>;
975 def : ReadAdvance<ReadVST4R, 0>;
976 def : ReadAdvance<ReadVST8R, 0>;
978 // 11. Vector Integer Arithmetic Instructions
979 defm "" : LMULReadAdvance<"ReadVIALUV", 0>;
980 defm "" : LMULReadAdvance<"ReadVIALUX", 0>;
981 defm "" : LMULReadAdvanceW<"ReadVIWALUV", 0>;
982 defm "" : LMULReadAdvanceW<"ReadVIWALUX", 0>;
983 defm "" : LMULReadAdvance<"ReadVExtV", 0>;
984 defm "" : LMULReadAdvance<"ReadVICALUV", 0>;
985 defm "" : LMULReadAdvance<"ReadVICALUX", 0>;
986 defm "" : LMULReadAdvance<"ReadVShiftV", 0>;
987 defm "" : LMULReadAdvance<"ReadVShiftX", 0>;
988 defm "" : LMULReadAdvanceW<"ReadVNShiftV", 0>;
989 defm "" : LMULReadAdvanceW<"ReadVNShiftX", 0>;
990 defm "" : LMULReadAdvance<"ReadVICmpV", 0>;
991 defm "" : LMULReadAdvance<"ReadVICmpX", 0>;
992 defm "" : LMULReadAdvance<"ReadVIMinMaxV", 0>;
993 defm "" : LMULReadAdvance<"ReadVIMinMaxX", 0>;
994 defm "" : LMULReadAdvance<"ReadVIMulV", 0>;
995 defm "" : LMULReadAdvance<"ReadVIMulX", 0>;
996 defm "" : LMULSEWReadAdvance<"ReadVIDivV", 0>;
997 defm "" : LMULSEWReadAdvance<"ReadVIDivX", 0>;
998 defm "" : LMULReadAdvanceW<"ReadVIWMulV", 0>;
999 defm "" : LMULReadAdvanceW<"ReadVIWMulX", 0>;
1000 defm "" : LMULReadAdvance<"ReadVIMulAddV", 0>;
1001 defm "" : LMULReadAdvance<"ReadVIMulAddX", 0>;
1002 defm "" : LMULReadAdvanceW<"ReadVIWMulAddV", 0>;
1003 defm "" : LMULReadAdvanceW<"ReadVIWMulAddX", 0>;
1004 defm "" : LMULReadAdvance<"ReadVIMergeV", 0>;
1005 defm "" : LMULReadAdvance<"ReadVIMergeX", 0>;
1006 defm "" : LMULReadAdvance<"ReadVIMovV", 0>;
1007 defm "" : LMULReadAdvance<"ReadVIMovX", 0>;
1009 // 12. Vector Fixed-Point Arithmetic Instructions
1010 defm "" : LMULReadAdvance<"ReadVSALUV", 0>;
1011 defm "" : LMULReadAdvance<"ReadVSALUX", 0>;
1012 defm "" : LMULReadAdvance<"ReadVAALUV", 0>;
1013 defm "" : LMULReadAdvance<"ReadVAALUX", 0>;
1014 defm "" : LMULReadAdvance<"ReadVSMulV", 0>;
1015 defm "" : LMULReadAdvance<"ReadVSMulX", 0>;
1016 defm "" : LMULReadAdvance<"ReadVSShiftV", 0>;
1017 defm "" : LMULReadAdvance<"ReadVSShiftX", 0>;
1018 defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>;
1019 defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>;
1021 // 13. Vector Floating-Point Instructions
1022 defm "" : LMULReadAdvance<"ReadVFALUV", 0>;
1023 defm "" : LMULReadAdvance<"ReadVFALUF", 0>;
1024 defm "" : LMULReadAdvanceFW<"ReadVFWALUV", 0>;
1025 defm "" : LMULReadAdvanceFW<"ReadVFWALUF", 0>;
1026 defm "" : LMULReadAdvance<"ReadVFMulV", 0>;
1027 defm "" : LMULReadAdvance<"ReadVFMulF", 0>;
1028 defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>;
1029 defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>;
1030 defm "" : LMULReadAdvanceFW<"ReadVFWMulV", 0>;
1031 defm "" : LMULReadAdvanceFW<"ReadVFWMulF", 0>;
1032 defm "" : LMULReadAdvance<"ReadVFMulAddV", 0>;
1033 defm "" : LMULReadAdvance<"ReadVFMulAddF", 0>;
1034 defm "" : LMULReadAdvanceFW<"ReadVFWMulAddV", 0>;
1035 defm "" : LMULReadAdvanceFW<"ReadVFWMulAddF", 0>;
1036 defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;
1037 defm "" : LMULReadAdvance<"ReadVFRecpV", 0>;
1038 defm "" : LMULReadAdvance<"ReadVFMinMaxV", 0>;
1039 defm "" : LMULReadAdvance<"ReadVFMinMaxF", 0>;
1040 defm "" : LMULReadAdvance<"ReadVFSgnjV", 0>;
1041 defm "" : LMULReadAdvance<"ReadVFSgnjF", 0>;
1042 defm "" : LMULReadAdvance<"ReadVFCmpV", 0>;
1043 defm "" : LMULReadAdvance<"ReadVFCmpF", 0>;
1044 defm "" : LMULReadAdvance<"ReadVFClassV", 0>;
1045 defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;
1046 defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;
1047 defm "" : LMULReadAdvance<"ReadVFMovF", 0>;
1048 defm "" : LMULReadAdvance<"ReadVFCvtIToFV", 0>;
1049 defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;
1050 defm "" : LMULReadAdvanceW<"ReadVFWCvtIToFV", 0>;
1051 defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;
1052 defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToFV", 0>;
1053 defm "" : LMULReadAdvanceFW<"ReadVFNCvtIToFV", 0>;
1054 defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>;
1055 defm "" : LMULReadAdvanceFW<"ReadVFNCvtFToFV", 0>;
1057 // 14. Vector Reduction Operations
1058 def : ReadAdvance<ReadVIRedV, 0>;
1059 def : ReadAdvance<ReadVIRedV0, 0>;
1060 def : ReadAdvance<ReadVIWRedV, 0>;
1061 def : ReadAdvance<ReadVIWRedV0, 0>;
1062 def : ReadAdvance<ReadVFRedV, 0>;
1063 def : ReadAdvance<ReadVFRedV0, 0>;
1064 def : ReadAdvance<ReadVFRedOV, 0>;
1065 def : ReadAdvance<ReadVFRedOV0, 0>;
1066 def : ReadAdvance<ReadVFRedMinMaxV, 0>;
1067 def : ReadAdvance<ReadVFWRedV, 0>;
1068 def : ReadAdvance<ReadVFWRedV0, 0>;
1069 def : ReadAdvance<ReadVFWRedOV, 0>;
1070 def : ReadAdvance<ReadVFWRedOV0, 0>;
1072 // 15. Vector Mask Instructions
1073 defm "" : LMULReadAdvance<"ReadVMALUV", 0>;
1074 defm "" : LMULReadAdvance<"ReadVMPopV", 0>;
1075 defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;
1076 defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
1077 defm "" : LMULReadAdvance<"ReadVMIotV", 0>;
1079 // 16. Vector Permutation Instructions
1080 def : ReadAdvance<ReadVIMovVX, 0>;
1081 def : ReadAdvance<ReadVIMovXV, 0>;
1082 def : ReadAdvance<ReadVIMovXX, 0>;
1083 def : ReadAdvance<ReadVFMovVF, 0>;
1084 def : ReadAdvance<ReadVFMovFV, 0>;
1085 def : ReadAdvance<ReadVFMovFX, 0>;
1086 defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
1087 defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
1088 defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;
1089 defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;
1090 defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>;
1091 defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>;
1092 defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;
1093 defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;
1094 defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>;
1095 defm "" : LMULReadAdvance<"ReadVGatherV", 0>;
1096 defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>;
1097 // These are already LMUL aware
1098 def : ReadAdvance<ReadVMov1V, 0>;
1099 def : ReadAdvance<ReadVMov2V, 0>;
1100 def : ReadAdvance<ReadVMov4V, 0>;
1101 def : ReadAdvance<ReadVMov8V, 0>;
1103 // Others
1104 def : ReadAdvance<ReadVMask, 0>;
1105 def : ReadAdvance<ReadVMergeOp_WorstCase, 0>;
1106 foreach mx = SchedMxList in {
1107 def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx), 0>;
1108 foreach sew = SchedSEWSet<mx>.val in
1109 def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # sew), 0>;
1110 }
1112 } // Unsupported
1113 } // UnsupportedSchedV