flang/test/Lower/PowerPC/ppc-vec-merge-elem-order.f90

   1 ! RUN: %flang_fc1 -emit-fir %s -fno-ppc-native-vector-element-order -triple ppc64le-unknown-linux -o - | FileCheck --check-prefixes="FIR" %s
   2 ! RUN: %flang_fc1 -emit-llvm %s -fno-ppc-native-vector-element-order -triple ppc64le-unknown-linux -o - | FileCheck --check-prefixes="LLVMIR" %s
   3 ! REQUIRES: target=powerpc{{.*}}
   4
   5 !-----------------
   6 ! vec_mergeh
   7 !-----------------
   8
   9 ! CHECK-LABEL: vec_mergeh_test_i4
  10 subroutine vec_mergeh_test_i4(arg1, arg2)
  11   vector(integer(4)) :: arg1, arg2, r
  12   r = vec_mergeh(arg1, arg2)
  13
  14 ! FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>>
  15 ! FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>>
  16 ! FIR: %[[carg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:i32>) -> vector<4xi32>
  17 ! FIR: %[[carg2:.*]] = fir.convert %[[arg2]] : (!fir.vector<4:i32>) -> vector<4xi32>
  18 ! FIR: %[[r:.*]] = vector.shuffle %[[carg1]], %[[carg2]] [6, 2, 7, 3] : vector<4xi32>, vector<4xi32>
  19 ! FIR: %[[cr:.*]] = fir.convert %[[r]] : (vector<4xi32>) -> !fir.vector<4:i32>
  20 ! FIR: fir.store %[[cr]] to %{{.*}} : !fir.ref<!fir.vector<4:i32>>
  21
  22 ! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16
  23 ! LLVMIR: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16
  24 ! LLVMIR: %[[r:.*]] = shufflevector <4 x i32> %[[arg1]], <4 x i32> %[[arg2]], <4 x i32> <i32 6, i32 2, i32 7, i32 3>
  25 ! LLVMIR: store <4 x i32> %[[r]], ptr %{{.*}}, align 16
  26 end subroutine vec_mergeh_test_i4
  27
  28 !-----------------
  29 ! vec_mergel
  30 !-----------------
  31
  32 ! CHECK-LABEL: vec_mergel_test_r8
  33 subroutine vec_mergel_test_r8(arg1, arg2)
  34   vector(real(8)) :: arg1, arg2, r
  35   r = vec_mergel(arg1, arg2)
  36
  37 ! FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:f64>>
  38 ! FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:f64>>
  39 ! FIR: %[[carg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<2:f64>) -> vector<2xf64>
  40 ! FIR: %[[carg2:.*]] = fir.convert %[[arg2]] : (!fir.vector<2:f64>) -> vector<2xf64>
  41 ! FIR: %[[r:.*]] = vector.shuffle %[[carg1]], %[[carg2]] [2, 0] : vector<2xf64>, vector<2xf64>
  42 ! FIR: %[[cr:.*]] = fir.convert %[[r]] : (vector<2xf64>) -> !fir.vector<2:f64>
  43 ! FIR: fir.store %[[cr]] to %{{.*}} : !fir.ref<!fir.vector<2:f64>>
  44
  45 ! LLVMIR: %[[arg1:.*]] = load <2 x double>, ptr %{{.*}}, align 16
  46 ! LLVMIR: %[[arg2:.*]] = load <2 x double>, ptr %{{.*}}, align 16
  47 ! LLVMIR: %[[r:.*]] = shufflevector <2 x double> %[[arg1]], <2 x double> %[[arg2]], <2 x i32> <i32 2, i32 0>
  48 ! LLVMIR: store <2 x double> %[[r]], ptr %{{.*}}, align 16
  49 end subroutine vec_mergel_test_r8