flang/test/Lower/PowerPC/ppc-vec_add-and-mul-sub-xor.f90

   1 ! RUN: bbc -emit-fir %s -o - | FileCheck --check-prefixes="CHECK-FIR" %s
   2 ! RUN: %flang_fc1 -emit-fir %s -o - | fir-opt --fir-to-llvm-ir | FileCheck --check-prefixes="CHECK-LLVMIR" %s
   3 ! RUN: %flang_fc1 -emit-llvm %s -o - | FileCheck --check-prefixes="CHECK" %s
   4 ! REQUIRES: target=powerpc{{.*}}
   5
   6 ! vec_add
   7
   8 ! CHECK-LABEL: vec_add_testf32
   9 subroutine vec_add_testf32(x, y)
  10   vector(real(4)) :: vsum, x, y
  11   vsum = vec_add(x, y)
  12 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<4:f32>>
  13 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<4:f32>>
  14 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<4:f32>) -> vector<4xf32>
  15 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<4:f32>) -> vector<4xf32>
  16 ! CHECK-FIR: %[[vsum:.*]] = arith.addf %[[vx]], %[[vy]] fastmath<contract> : vector<4xf32>
  17 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vsum]] : (vector<4xf32>) -> !fir.vector<4:f32>
  18
  19 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<4xf32>>
  20 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<4xf32>>
  21 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.fadd %[[x]], %[[y]]  {fastmathFlags = #llvm.fastmath<contract>} : vector<4xf32>
  22
  23 ! CHECK: %[[x:.*]] = load <4 x float>, ptr %{{[0-9]}}, align 16
  24 ! CHECK: %[[y:.*]] = load <4 x float>, ptr %{{[0-9]}}, align 16
  25 ! CHECK: %{{[0-9]}} = fadd contract <4 x float> %[[x]], %[[y]]
  26 end subroutine vec_add_testf32
  27
  28 ! CHECK-LABEL: vec_add_testf64
  29 subroutine vec_add_testf64(x, y)
  30   vector(real(8)) :: vsum, x, y
  31   vsum = vec_add(x, y)
  32 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<2:f64>>
  33 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<2:f64>>
  34 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<2:f64>) -> vector<2xf64>
  35 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<2:f64>) -> vector<2xf64>
  36 ! CHECK-FIR: %[[vsum:.*]] = arith.addf %[[vx]], %[[vy]] fastmath<contract> : vector<2xf64>
  37 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vsum]] : (vector<2xf64>) -> !fir.vector<2:f64>
  38
  39 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<2xf64>>
  40 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<2xf64>>
  41 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.fadd %[[x]], %[[y]]  {fastmathFlags = #llvm.fastmath<contract>} : vector<2xf64>
  42
  43 ! CHECK: %[[x:.*]] = load <2 x double>, ptr %{{[0-9]}}, align 16
  44 ! CHECK: %[[y:.*]] = load <2 x double>, ptr %{{[0-9]}}, align 16
  45 ! CHECK: %{{[0-9]}} = fadd contract <2 x double> %[[x]], %[[y]]
  46 end subroutine vec_add_testf64
  47
  48 ! CHECK-LABEL: vec_add_testi8
  49 subroutine vec_add_testi8(x, y)
  50   vector(integer(1)) :: vsum, x, y
  51   vsum = vec_add(x, y)
  52 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<16:i8>>
  53 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<16:i8>>
  54 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<16:i8>) -> vector<16xi8>
  55 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<16:i8>) -> vector<16xi8>
  56 ! CHECK-FIR: %[[vsum:.*]] = arith.addi %[[vx]], %[[vy]] : vector<16xi8>
  57 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vsum]] : (vector<16xi8>) -> !fir.vector<16:i8>
  58
  59 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<16xi8>>
  60 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<16xi8>>
  61 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.add %[[x]], %[[y]] : vector<16xi8>
  62
  63 ! CHECK: %[[x:.*]] = load <16 x i8>, ptr %{{[0-9]}}, align 16
  64 ! CHECK: %[[y:.*]] = load <16 x i8>, ptr %{{[0-9]}}, align 16
  65 ! CHECK: %{{[0-9]}} = add <16 x i8> %[[x]], %[[y]]
  66 end subroutine vec_add_testi8
  67
  68 ! CHECK-LABEL: vec_add_testi16
  69 subroutine vec_add_testi16(x, y)
  70   vector(integer(2)) :: vsum, x, y
  71   vsum = vec_add(x, y)
  72 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<8:i16>>
  73 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<8:i16>>
  74 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<8:i16>) -> vector<8xi16>
  75 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<8:i16>) -> vector<8xi16>
  76 ! CHECK-FIR: %[[vsum:.*]] = arith.addi %[[vx]], %[[vy]] : vector<8xi16>
  77 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vsum]] : (vector<8xi16>) -> !fir.vector<8:i16>
  78
  79 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<8xi16>>
  80 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<8xi16>>
  81 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.add %[[x]], %[[y]] : vector<8xi16>
  82
  83 ! CHECK: %[[x:.*]] = load <8 x i16>, ptr %{{[0-9]}}, align 16
  84 ! CHECK: %[[y:.*]] = load <8 x i16>, ptr %{{[0-9]}}, align 16
  85 ! CHECK: %{{[0-9]}} = add <8 x i16> %[[x]], %[[y]]
  86 end subroutine vec_add_testi16
  87
  88 ! CHECK-LABEL: vec_add_testi32
  89 subroutine vec_add_testi32(x, y)
  90   vector(integer(4)) :: vsum, x, y
  91   vsum = vec_add(x, y)
  92 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<4:i32>>
  93 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<4:i32>>
  94 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<4:i32>) -> vector<4xi32>
  95 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<4:i32>) -> vector<4xi32>
  96 ! CHECK-FIR: %[[vsum:.*]] = arith.addi %[[vx]], %[[vy]] : vector<4xi32>
  97 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vsum]] : (vector<4xi32>) -> !fir.vector<4:i32>
  98
  99 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<4xi32>>
 100 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<4xi32>>
 101 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.add %[[x]], %[[y]] : vector<4xi32>
 102
 103 ! CHECK: %[[x:.*]] = load <4 x i32>, ptr %{{[0-9]}}, align 16
 104 ! CHECK: %[[y:.*]] = load <4 x i32>, ptr %{{[0-9]}}, align 16
 105 ! CHECK: %{{[0-9]}} = add <4 x i32> %[[x]], %[[y]]
 106 end subroutine vec_add_testi32
 107
 108 ! CHECK-LABEL: vec_add_testi64
 109 subroutine vec_add_testi64(x, y)
 110   vector(integer(8)) :: vsum, x, y
 111   vsum = vec_add(x, y)
 112 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<2:i64>>
 113 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<2:i64>>
 114 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<2:i64>) -> vector<2xi64>
 115 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<2:i64>) -> vector<2xi64>
 116 ! CHECK-FIR: %[[vsum:.*]] = arith.addi %[[vx]], %[[vy]] : vector<2xi64>
 117 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vsum]] : (vector<2xi64>) -> !fir.vector<2:i64>
 118
 119 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<2xi64>>
 120 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<2xi64>>
 121 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.add %[[x]], %[[y]] : vector<2xi64>
 122
 123 ! CHECK: %[[x:.*]] = load <2 x i64>, ptr %{{[0-9]}}, align 16
 124 ! CHECK: %[[y:.*]] = load <2 x i64>, ptr %{{[0-9]}}, align 16
 125 ! CHECK: %{{[0-9]}} = add <2 x i64> %[[x]], %[[y]]
 126 end subroutine vec_add_testi64
 127
 128 ! CHECK-LABEL: vec_add_testui8
 129 subroutine vec_add_testui8(x, y)
 130   vector(unsigned(1)) :: vsum, x, y
 131   vsum = vec_add(x, y)
 132 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<16:ui8>>
 133 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<16:ui8>>
 134 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<16:ui8>) -> vector<16xi8>
 135 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<16:ui8>) -> vector<16xi8>
 136 ! CHECK-FIR: %[[vsum:.*]] = arith.addi %[[vx]], %[[vy]] : vector<16xi8>
 137 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vsum]] : (vector<16xi8>) -> !fir.vector<16:ui8>
 138
 139 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<16xi8>>
 140 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<16xi8>>
 141 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.add %[[x]], %[[y]] : vector<16xi8>
 142
 143 ! CHECK: %[[x:.*]] = load <16 x i8>, ptr %{{[0-9]}}, align 16
 144 ! CHECK: %[[y:.*]] = load <16 x i8>, ptr %{{[0-9]}}, align 16
 145 ! CHECK: %{{[0-9]}} = add <16 x i8> %[[x]], %[[y]]
 146 end subroutine vec_add_testui8
 147
 148 ! CHECK-LABEL: vec_add_testui16
 149 subroutine vec_add_testui16(x, y)
 150   vector(unsigned(2)) :: vsum, x, y
 151   vsum = vec_add(x, y)
 152 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<8:ui16>>
 153 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<8:ui16>>
 154 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<8:ui16>) -> vector<8xi16>
 155 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<8:ui16>) -> vector<8xi16>
 156 ! CHECK-FIR: %[[vsum:.*]] = arith.addi %[[vx]], %[[vy]] : vector<8xi16>
 157 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vsum]] : (vector<8xi16>) -> !fir.vector<8:ui16>
 158
 159 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<8xi16>>
 160 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<8xi16>>
 161 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.add %[[x]], %[[y]] : vector<8xi16>
 162
 163 ! CHECK: %[[x:.*]] = load <8 x i16>, ptr %{{[0-9]}}, align 16
 164 ! CHECK: %[[y:.*]] = load <8 x i16>, ptr %{{[0-9]}}, align 16
 165 ! CHECK: %{{[0-9]}} = add <8 x i16> %[[x]], %[[y]]
 166 end subroutine vec_add_testui16
 167
 168 ! CHECK-LABEL: vec_add_testui32
 169 subroutine vec_add_testui32(x, y)
 170   vector(unsigned(4)) :: vsum, x, y
 171   vsum = vec_add(x, y)
 172 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<4:ui32>>
 173 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<4:ui32>>
 174 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<4:ui32>) -> vector<4xi32>
 175 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<4:ui32>) -> vector<4xi32>
 176 ! CHECK-FIR: %[[vsum:.*]] = arith.addi %[[vx]], %[[vy]] : vector<4xi32>
 177 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vsum]] : (vector<4xi32>) -> !fir.vector<4:ui32>
 178
 179 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<4xi32>>
 180 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<4xi32>>
 181 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.add %[[x]], %[[y]] : vector<4xi32>
 182
 183 ! CHECK: %[[x:.*]] = load <4 x i32>, ptr %{{[0-9]}}, align 16
 184 ! CHECK: %[[y:.*]] = load <4 x i32>, ptr %{{[0-9]}}, align 16
 185 ! CHECK: %{{[0-9]}} = add <4 x i32> %[[x]], %[[y]]
 186 end subroutine vec_add_testui32
 187
 188 ! CHECK-LABEL: vec_add_testui64
 189 subroutine vec_add_testui64(x, y)
 190   vector(unsigned(8)) :: vsum, x, y
 191   vsum = vec_add(x, y)
 192 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<2:ui64>>
 193 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<2:ui64>>
 194 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<2:ui64>) -> vector<2xi64>
 195 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<2:ui64>) -> vector<2xi64>
 196 ! CHECK-FIR: %[[vsum:.*]] = arith.addi %[[vx]], %[[vy]] : vector<2xi64>
 197 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vsum]] : (vector<2xi64>) -> !fir.vector<2:ui64>
 198
 199 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<2xi64>>
 200 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<2xi64>>
 201 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.add %[[x]], %[[y]] : vector<2xi64>
 202
 203 ! CHECK: %[[x:.*]] = load <2 x i64>, ptr %{{[0-9]}}, align 16
 204 ! CHECK: %[[y:.*]] = load <2 x i64>, ptr %{{[0-9]}}, align 16
 205 ! CHECK: %{{[0-9]}} = add <2 x i64> %[[x]], %[[y]]
 206 end subroutine vec_add_testui64
 207
 208 ! vec_mul
 209
 210 ! CHECK-LABEL: vec_mul_testf32
 211 subroutine vec_mul_testf32(x, y)
 212   vector(real(4)) :: vmul, x, y
 213   vmul = vec_mul(x, y)
 214 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<4:f32>>
 215 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<4:f32>>
 216 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<4:f32>) -> vector<4xf32>
 217 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<4:f32>) -> vector<4xf32>
 218 ! CHECK-FIR: %[[vmul:.*]] = arith.mulf %[[vx]], %[[vy]] fastmath<contract> : vector<4xf32>
 219 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vmul]] : (vector<4xf32>) -> !fir.vector<4:f32>
 220
 221 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<4xf32>>
 222 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<4xf32>>
 223 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.fmul %[[x]], %[[y]]  {fastmathFlags = #llvm.fastmath<contract>} : vector<4xf32>
 224
 225 ! CHECK: %[[x:.*]] = load <4 x float>, ptr %{{[0-9]}}, align 16
 226 ! CHECK: %[[y:.*]] = load <4 x float>, ptr %{{[0-9]}}, align 16
 227 ! CHECK: %{{[0-9]}} = fmul contract <4 x float> %[[x]], %[[y]]
 228 end subroutine vec_mul_testf32
 229
 230 ! CHECK-LABEL: vec_mul_testf64
 231 subroutine vec_mul_testf64(x, y)
 232   vector(real(8)) :: vmul, x, y
 233   vmul = vec_mul(x, y)
 234 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<2:f64>>
 235 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<2:f64>>
 236 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<2:f64>) -> vector<2xf64>
 237 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<2:f64>) -> vector<2xf64>
 238 ! CHECK-FIR: %[[vmul:.*]] = arith.mulf %[[vx]], %[[vy]] fastmath<contract> : vector<2xf64>
 239 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vmul]] : (vector<2xf64>) -> !fir.vector<2:f64>
 240
 241 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<2xf64>>
 242 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<2xf64>>
 243 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.fmul %[[x]], %[[y]]  {fastmathFlags = #llvm.fastmath<contract>} : vector<2xf64>
 244
 245 ! CHECK: %[[x:.*]] = load <2 x double>, ptr %{{[0-9]}}, align 16
 246 ! CHECK: %[[y:.*]] = load <2 x double>, ptr %{{[0-9]}}, align 16
 247 ! CHECK: %{{[0-9]}} = fmul contract <2 x double> %[[x]], %[[y]]
 248 end subroutine vec_mul_testf64
 249
 250 ! CHECK-LABEL: vec_mul_testi8
 251 subroutine vec_mul_testi8(x, y)
 252   vector(integer(1)) :: vmul, x, y
 253   vmul = vec_mul(x, y)
 254 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<16:i8>>
 255 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<16:i8>>
 256 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<16:i8>) -> vector<16xi8>
 257 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<16:i8>) -> vector<16xi8>
 258 ! CHECK-FIR: %[[vmul:.*]] = arith.muli %[[vx]], %[[vy]] : vector<16xi8>
 259 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vmul]] : (vector<16xi8>) -> !fir.vector<16:i8>
 260
 261 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<16xi8>>
 262 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<16xi8>>
 263 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.mul %[[x]], %[[y]] : vector<16xi8>
 264
 265 ! CHECK: %[[x:.*]] = load <16 x i8>, ptr %{{[0-9]}}, align 16
 266 ! CHECK: %[[y:.*]] = load <16 x i8>, ptr %{{[0-9]}}, align 16
 267 ! CHECK: %{{[0-9]}} = mul <16 x i8> %[[x]], %[[y]]
 268 end subroutine vec_mul_testi8
 269
 270 ! CHECK-LABEL: vec_mul_testi16
 271 subroutine vec_mul_testi16(x, y)
 272   vector(integer(2)) :: vmul, x, y
 273   vmul = vec_mul(x, y)
 274 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<8:i16>>
 275 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<8:i16>>
 276 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<8:i16>) -> vector<8xi16>
 277 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<8:i16>) -> vector<8xi16>
 278 ! CHECK-FIR: %[[vmul:.*]] = arith.muli %[[vx]], %[[vy]] : vector<8xi16>
 279 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vmul]] : (vector<8xi16>) -> !fir.vector<8:i16>
 280
 281 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<8xi16>>
 282 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<8xi16>>
 283 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.mul %[[x]], %[[y]] : vector<8xi16>
 284
 285 ! CHECK: %[[x:.*]] = load <8 x i16>, ptr %{{[0-9]}}, align 16
 286 ! CHECK: %[[y:.*]] = load <8 x i16>, ptr %{{[0-9]}}, align 16
 287 ! CHECK: %{{[0-9]}} = mul <8 x i16> %[[x]], %[[y]]
 288 end subroutine vec_mul_testi16
 289
 290 ! CHECK-LABEL: vec_mul_testi32
 291 subroutine vec_mul_testi32(x, y)
 292   vector(integer(4)) :: vmul, x, y
 293   vmul = vec_mul(x, y)
 294 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<4:i32>>
 295 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<4:i32>>
 296 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<4:i32>) -> vector<4xi32>
 297 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<4:i32>) -> vector<4xi32>
 298 ! CHECK-FIR: %[[vmul:.*]] = arith.muli %[[vx]], %[[vy]] : vector<4xi32>
 299 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vmul]] : (vector<4xi32>) -> !fir.vector<4:i32>
 300
 301 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<4xi32>>
 302 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<4xi32>>
 303 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.mul %[[x]], %[[y]] : vector<4xi32>
 304
 305 ! CHECK: %[[x:.*]] = load <4 x i32>, ptr %{{[0-9]}}, align 16
 306 ! CHECK: %[[y:.*]] = load <4 x i32>, ptr %{{[0-9]}}, align 16
 307 ! CHECK: %{{[0-9]}} = mul <4 x i32> %[[x]], %[[y]]
 308 end subroutine vec_mul_testi32
 309
 310 ! CHECK-LABEL: vec_mul_testi64
 311 subroutine vec_mul_testi64(x, y)
 312   vector(integer(8)) :: vmul, x, y
 313   vmul = vec_mul(x, y)
 314 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<2:i64>>
 315 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<2:i64>>
 316 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<2:i64>) -> vector<2xi64>
 317 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<2:i64>) -> vector<2xi64>
 318 ! CHECK-FIR: %[[vmul:.*]] = arith.muli %[[vx]], %[[vy]] : vector<2xi64>
 319 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vmul]] : (vector<2xi64>) -> !fir.vector<2:i64>
 320
 321 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<2xi64>>
 322 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<2xi64>>
 323 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.mul %[[x]], %[[y]] : vector<2xi64>
 324
 325 ! CHECK: %[[x:.*]] = load <2 x i64>, ptr %{{[0-9]}}, align 16
 326 ! CHECK: %[[y:.*]] = load <2 x i64>, ptr %{{[0-9]}}, align 16
 327 ! CHECK: %{{[0-9]}} = mul <2 x i64> %[[x]], %[[y]]
 328 end subroutine vec_mul_testi64
 329
 330 ! CHECK-LABEL: vec_mul_testui8
 331 subroutine vec_mul_testui8(x, y)
 332   vector(unsigned(1)) :: vmul, x, y
 333   vmul = vec_mul(x, y)
 334 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<16:ui8>>
 335 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<16:ui8>>
 336 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<16:ui8>) -> vector<16xi8>
 337 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<16:ui8>) -> vector<16xi8>
 338 ! CHECK-FIR: %[[vmul:.*]] = arith.muli %[[vx]], %[[vy]] : vector<16xi8>
 339 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vmul]] : (vector<16xi8>) -> !fir.vector<16:ui8>
 340
 341 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<16xi8>>
 342 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<16xi8>>
 343 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.mul %[[x]], %[[y]] : vector<16xi8>
 344
 345 ! CHECK: %[[x:.*]] = load <16 x i8>, ptr %{{[0-9]}}, align 16
 346 ! CHECK: %[[y:.*]] = load <16 x i8>, ptr %{{[0-9]}}, align 16
 347 ! CHECK: %{{[0-9]}} = mul <16 x i8> %[[x]], %[[y]]
 348 end subroutine vec_mul_testui8
 349
 350 ! CHECK-LABEL: vec_mul_testui16
 351 subroutine vec_mul_testui16(x, y)
 352   vector(unsigned(2)) :: vmul, x, y
 353   vmul = vec_mul(x, y)
 354 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<8:ui16>>
 355 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<8:ui16>>
 356 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<8:ui16>) -> vector<8xi16>
 357 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<8:ui16>) -> vector<8xi16>
 358 ! CHECK-FIR: %[[vmul:.*]] = arith.muli %[[vx]], %[[vy]] : vector<8xi16>
 359 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vmul]] : (vector<8xi16>) -> !fir.vector<8:ui16>
 360
 361 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<8xi16>>
 362 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<8xi16>>
 363 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.mul %[[x]], %[[y]] : vector<8xi16>
 364
 365 ! CHECK: %[[x:.*]] = load <8 x i16>, ptr %{{[0-9]}}, align 16
 366 ! CHECK: %[[y:.*]] = load <8 x i16>, ptr %{{[0-9]}}, align 16
 367 ! CHECK: %{{[0-9]}} = mul <8 x i16> %[[x]], %[[y]]
 368 end subroutine vec_mul_testui16
 369
 370 ! CHECK-LABEL: vec_mul_testui32
 371 subroutine vec_mul_testui32(x, y)
 372   vector(unsigned(4)) :: vmul, x, y
 373   vmul = vec_mul(x, y)
 374 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<4:ui32>>
 375 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<4:ui32>>
 376 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<4:ui32>) -> vector<4xi32>
 377 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<4:ui32>) -> vector<4xi32>
 378 ! CHECK-FIR: %[[vmul:.*]] = arith.muli %[[vx]], %[[vy]] : vector<4xi32>
 379 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vmul]] : (vector<4xi32>) -> !fir.vector<4:ui32>
 380
 381 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<4xi32>>
 382 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<4xi32>>
 383 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.mul %[[x]], %[[y]] : vector<4xi32>
 384
 385 ! CHECK: %[[x:.*]] = load <4 x i32>, ptr %{{[0-9]}}, align 16
 386 ! CHECK: %[[y:.*]] = load <4 x i32>, ptr %{{[0-9]}}, align 16
 387 ! CHECK: %{{[0-9]}} = mul <4 x i32> %[[x]], %[[y]]
 388 end subroutine vec_mul_testui32
 389
 390 ! CHECK-LABEL: vec_mul_testui64
 391 subroutine vec_mul_testui64(x, y)
 392   vector(unsigned(8)) :: vmul, x, y
 393   vmul = vec_mul(x, y)
 394 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<2:ui64>>
 395 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<2:ui64>>
 396 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<2:ui64>) -> vector<2xi64>
 397 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<2:ui64>) -> vector<2xi64>
 398 ! CHECK-FIR: %[[vmul:.*]] = arith.muli %[[vx]], %[[vy]] : vector<2xi64>
 399 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vmul]] : (vector<2xi64>) -> !fir.vector<2:ui64>
 400
 401 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<2xi64>>
 402 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<2xi64>>
 403 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.mul %[[x]], %[[y]] : vector<2xi64>
 404
 405 ! CHECK: %[[x:.*]] = load <2 x i64>, ptr %{{[0-9]}}, align 16
 406 ! CHECK: %[[y:.*]] = load <2 x i64>, ptr %{{[0-9]}}, align 16
 407 ! CHECK: %{{[0-9]}} = mul <2 x i64> %[[x]], %[[y]]
 408 end subroutine vec_mul_testui64
 409
 410 ! vec_sub
 411
 412 ! CHECK-LABEL: vec_sub_testf32
 413 subroutine vec_sub_testf32(x, y)
 414   vector(real(4)) :: vsub, x, y
 415   vsub = vec_sub(x, y)
 416 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<4:f32>>
 417 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<4:f32>>
 418 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<4:f32>) -> vector<4xf32>
 419 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<4:f32>) -> vector<4xf32>
 420 ! CHECK-FIR: %[[vsub:.*]] = arith.subf %[[vx]], %[[vy]] fastmath<contract> : vector<4xf32>
 421 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vsub]] : (vector<4xf32>) -> !fir.vector<4:f32>
 422
 423 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<4xf32>>
 424 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<4xf32>>
 425 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.fsub %[[x]], %[[y]]  {fastmathFlags = #llvm.fastmath<contract>} : vector<4xf32>
 426
 427 ! CHECK: %[[x:.*]] = load <4 x float>, ptr %{{[0-9]}}, align 16
 428 ! CHECK: %[[y:.*]] = load <4 x float>, ptr %{{[0-9]}}, align 16
 429 ! CHECK: %{{[0-9]}} = fsub contract <4 x float> %[[x]], %[[y]]
 430 end subroutine vec_sub_testf32
 431
 432 ! CHECK-LABEL: vec_sub_testf64
 433 subroutine vec_sub_testf64(x, y)
 434   vector(real(8)) :: vsub, x, y
 435   vsub = vec_sub(x, y)
 436 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<2:f64>>
 437 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<2:f64>>
 438 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<2:f64>) -> vector<2xf64>
 439 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<2:f64>) -> vector<2xf64>
 440 ! CHECK-FIR: %[[vsub:.*]] = arith.subf %[[vx]], %[[vy]] fastmath<contract> : vector<2xf64>
 441 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vsub]] : (vector<2xf64>) -> !fir.vector<2:f64>
 442
 443 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<2xf64>>
 444 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<2xf64>>
 445 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.fsub %[[x]], %[[y]]  {fastmathFlags = #llvm.fastmath<contract>} : vector<2xf64>
 446
 447 ! CHECK: %[[x:.*]] = load <2 x double>, ptr %{{[0-9]}}, align 16
 448 ! CHECK: %[[y:.*]] = load <2 x double>, ptr %{{[0-9]}}, align 16
 449 ! CHECK: %{{[0-9]}} = fsub contract <2 x double> %[[x]], %[[y]]
 450 end subroutine vec_sub_testf64
 451
 452 ! CHECK-LABEL: vec_sub_testi8
 453 subroutine vec_sub_testi8(x, y)
 454   vector(integer(1)) :: vsub, x, y
 455   vsub = vec_sub(x, y)
 456 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<16:i8>>
 457 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<16:i8>>
 458 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<16:i8>) -> vector<16xi8>
 459 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<16:i8>) -> vector<16xi8>
 460 ! CHECK-FIR: %[[vsub:.*]] = arith.subi %[[vx]], %[[vy]] : vector<16xi8>
 461 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vsub]] : (vector<16xi8>) -> !fir.vector<16:i8>
 462
 463 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<16xi8>>
 464 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<16xi8>>
 465 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.sub %[[x]], %[[y]] : vector<16xi8>
 466
 467 ! CHECK: %[[x:.*]] = load <16 x i8>, ptr %{{[0-9]}}, align 16
 468 ! CHECK: %[[y:.*]] = load <16 x i8>, ptr %{{[0-9]}}, align 16
 469 ! CHECK: %{{[0-9]}} = sub <16 x i8> %[[x]], %[[y]]
 470 end subroutine vec_sub_testi8
 471
 472 ! CHECK-LABEL: vec_sub_testi16
 473 subroutine vec_sub_testi16(x, y)
 474   vector(integer(2)) :: vsub, x, y
 475   vsub = vec_sub(x, y)
 476 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<8:i16>>
 477 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<8:i16>>
 478 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<8:i16>) -> vector<8xi16>
 479 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<8:i16>) -> vector<8xi16>
 480 ! CHECK-FIR: %[[vsub:.*]] = arith.subi %[[vx]], %[[vy]] : vector<8xi16>
 481 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vsub]] : (vector<8xi16>) -> !fir.vector<8:i16>
 482
 483 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<8xi16>>
 484 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<8xi16>>
 485 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.sub %[[x]], %[[y]] : vector<8xi16>
 486
 487 ! CHECK: %[[x:.*]] = load <8 x i16>, ptr %{{[0-9]}}, align 16
 488 ! CHECK: %[[y:.*]] = load <8 x i16>, ptr %{{[0-9]}}, align 16
 489 ! CHECK: %{{[0-9]}} = sub <8 x i16> %[[x]], %[[y]]
 490 end subroutine vec_sub_testi16
 491
 492 ! CHECK-LABEL: vec_sub_testi32
 493 subroutine vec_sub_testi32(x, y)
 494   vector(integer(4)) :: vsub, x, y
 495   vsub = vec_sub(x, y)
 496 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<4:i32>>
 497 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<4:i32>>
 498 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<4:i32>) -> vector<4xi32>
 499 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<4:i32>) -> vector<4xi32>
 500 ! CHECK-FIR: %[[vsub:.*]] = arith.subi %[[vx]], %[[vy]] : vector<4xi32>
 501 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vsub]] : (vector<4xi32>) -> !fir.vector<4:i32>
 502
 503 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<4xi32>>
 504 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<4xi32>>
 505 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.sub %[[x]], %[[y]] : vector<4xi32>
 506
 507 ! CHECK: %[[x:.*]] = load <4 x i32>, ptr %{{[0-9]}}, align 16
 508 ! CHECK: %[[y:.*]] = load <4 x i32>, ptr %{{[0-9]}}, align 16
 509 ! CHECK: %{{[0-9]}} = sub <4 x i32> %[[x]], %[[y]]
 510 end subroutine vec_sub_testi32
 511
 512 ! CHECK-LABEL: vec_sub_testi64
 513 subroutine vec_sub_testi64(x, y)
 514   vector(integer(8)) :: vsub, x, y
 515   vsub = vec_sub(x, y)
 516 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<2:i64>>
 517 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<2:i64>>
 518 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<2:i64>) -> vector<2xi64>
 519 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<2:i64>) -> vector<2xi64>
 520 ! CHECK-FIR: %[[vsub:.*]] = arith.subi %[[vx]], %[[vy]] : vector<2xi64>
 521 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vsub]] : (vector<2xi64>) -> !fir.vector<2:i64>
 522
 523 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<2xi64>>
 524 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<2xi64>>
 525 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.sub %[[x]], %[[y]] : vector<2xi64>
 526
 527 ! CHECK: %[[x:.*]] = load <2 x i64>, ptr %{{[0-9]}}, align 16
 528 ! CHECK: %[[y:.*]] = load <2 x i64>, ptr %{{[0-9]}}, align 16
 529 ! CHECK: %{{[0-9]}} = sub <2 x i64> %[[x]], %[[y]]
 530 end subroutine vec_sub_testi64
 531
 532 ! CHECK-LABEL: vec_sub_testui8
 533 subroutine vec_sub_testui8(x, y)
 534   vector(unsigned(1)) :: vsub, x, y
 535   vsub = vec_sub(x, y)
 536 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<16:ui8>>
 537 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<16:ui8>>
 538 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<16:ui8>) -> vector<16xi8>
 539 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<16:ui8>) -> vector<16xi8>
 540 ! CHECK-FIR: %[[vsub:.*]] = arith.subi %[[vx]], %[[vy]] : vector<16xi8>
 541 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vsub]] : (vector<16xi8>) -> !fir.vector<16:ui8>
 542
 543 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<16xi8>>
 544 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<16xi8>>
 545 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.sub %[[x]], %[[y]] : vector<16xi8>
 546
 547 ! CHECK: %[[x:.*]] = load <16 x i8>, ptr %{{[0-9]}}, align 16
 548 ! CHECK: %[[y:.*]] = load <16 x i8>, ptr %{{[0-9]}}, align 16
 549 ! CHECK: %{{[0-9]}} = sub <16 x i8> %[[x]], %[[y]]
 550 end subroutine vec_sub_testui8
 551
 552 ! CHECK-LABEL: vec_sub_testui16
 553 subroutine vec_sub_testui16(x, y)
 554   vector(unsigned(2)) :: vsub, x, y
 555   vsub = vec_sub(x, y)
 556 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<8:ui16>>
 557 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<8:ui16>>
 558 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<8:ui16>) -> vector<8xi16>
 559 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<8:ui16>) -> vector<8xi16>
 560 ! CHECK-FIR: %[[vsub:.*]] = arith.subi %[[vx]], %[[vy]] : vector<8xi16>
 561 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vsub]] : (vector<8xi16>) -> !fir.vector<8:ui16>
 562
 563 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<8xi16>>
 564 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<8xi16>>
 565 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.sub %[[x]], %[[y]] : vector<8xi16>
 566
 567 ! CHECK: %[[x:.*]] = load <8 x i16>, ptr %{{[0-9]}}, align 16
 568 ! CHECK: %[[y:.*]] = load <8 x i16>, ptr %{{[0-9]}}, align 16
 569 ! CHECK: %{{[0-9]}} = sub <8 x i16> %[[x]], %[[y]]
 570 end subroutine vec_sub_testui16
 571
 572 ! CHECK-LABEL: vec_sub_testui32
 573 subroutine vec_sub_testui32(x, y)
 574   vector(unsigned(4)) :: vsub, x, y
 575   vsub = vec_sub(x, y)
 576 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<4:ui32>>
 577 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<4:ui32>>
 578 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<4:ui32>) -> vector<4xi32>
 579 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<4:ui32>) -> vector<4xi32>
 580 ! CHECK-FIR: %[[vsub:.*]] = arith.subi %[[vx]], %[[vy]] : vector<4xi32>
 581 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vsub]] : (vector<4xi32>) -> !fir.vector<4:ui32>
 582
 583 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<4xi32>>
 584 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<4xi32>>
 585 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.sub %[[x]], %[[y]] : vector<4xi32>
 586
 587 ! CHECK: %[[x:.*]] = load <4 x i32>, ptr %{{[0-9]}}, align 16
 588 ! CHECK: %[[y:.*]] = load <4 x i32>, ptr %{{[0-9]}}, align 16
 589 ! CHECK: %{{[0-9]}} = sub <4 x i32> %[[x]], %[[y]]
 590 end subroutine vec_sub_testui32
 591
 592 ! CHECK-LABEL: vec_sub_testui64
 593 subroutine vec_sub_testui64(x, y)
 594   vector(unsigned(8)) :: vsub, x, y
 595   vsub = vec_sub(x, y)
 596 ! CHECK-FIR: %[[x:.*]] = fir.load %arg0 : !fir.ref<!fir.vector<2:ui64>>
 597 ! CHECK-FIR: %[[y:.*]] = fir.load %arg1 : !fir.ref<!fir.vector<2:ui64>>
 598 ! CHECK-FIR: %[[vx:.*]] = fir.convert %[[x]] : (!fir.vector<2:ui64>) -> vector<2xi64>
 599 ! CHECK-FIR: %[[vy:.*]] = fir.convert %[[y]] : (!fir.vector<2:ui64>) -> vector<2xi64>
 600 ! CHECK-FIR: %[[vsub:.*]] = arith.subi %[[vx]], %[[vy]] : vector<2xi64>
 601 ! CHECK-FIR: %{{[0-9]}} = fir.convert %[[vsub]] : (vector<2xi64>) -> !fir.vector<2:ui64>
 602
 603 ! CHECK-LLVMIR: %[[x:.*]] = llvm.load %arg0 : !llvm.ptr<vector<2xi64>>
 604 ! CHECK-LLVMIR: %[[y:.*]] = llvm.load %arg1 : !llvm.ptr<vector<2xi64>>
 605 ! CHECK-LLVMIR: %{{[0-9]}} = llvm.sub %[[x]], %[[y]] : vector<2xi64>
 606
 607 ! CHECK: %[[x:.*]] = load <2 x i64>, ptr %{{[0-9]}}, align 16
 608 ! CHECK: %[[y:.*]] = load <2 x i64>, ptr %{{[0-9]}}, align 16
 609 ! CHECK: %{{[0-9]}} = sub <2 x i64> %[[x]], %[[y]]
 610 end subroutine vec_sub_testui64
 611
 612 !----------------------
 613 ! vec_and
 614 !----------------------
 615
 616 ! CHECK-LABEL: vec_and_test_i8
 617 subroutine vec_and_test_i8(arg1, arg2)
 618   vector(integer(1)) :: r, arg1, arg2
 619   r = vec_and(arg1, arg2)
 620 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:i8>>
 621 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:i8>>
 622 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<16:i8>) -> vector<16xi8>
 623 ! CHECK-FIR: %[[varg2:.*]] = fir.convert %[[arg2]] : (!fir.vector<16:i8>) -> vector<16xi8>
 624 ! CHECK-FIR: %[[r:.*]] = arith.andi %[[varg1]], %[[varg2]] : vector<16xi8>
 625 ! CHECK-FIR: %{{[0-9]+}} = fir.convert %[[r]] : (vector<16xi8>) -> !fir.vector<16:i8>
 626
 627 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>>
 628 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>>
 629 ! CHECK-LLVMIR: %{{[0-9]+}} = llvm.and %[[arg1]], %[[arg2]] : vector<16xi8>
 630
 631 ! CHECK: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16
 632 ! CHECK: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16
 633 ! CHECK: %{{[0-9]+}} = and <16 x i8> %[[arg1]], %[[arg2]]
 634 end subroutine vec_and_test_i8
 635
 636 ! CHECK-LABEL: vec_and_test_i16
 637 subroutine vec_and_test_i16(arg1, arg2)
 638   vector(integer(2)) :: r, arg1, arg2
 639   r = vec_and(arg1, arg2)
 640 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:i16>>
 641 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:i16>>
 642 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<8:i16>) -> vector<8xi16>
 643 ! CHECK-FIR: %[[varg2:.*]] = fir.convert %[[arg2]] : (!fir.vector<8:i16>) -> vector<8xi16>
 644 ! CHECK-FIR: %[[r:.*]] = arith.andi %[[varg1]], %[[varg2]] : vector<8xi16>
 645 ! CHECK-FIR: %{{[0-9]+}} = fir.convert %[[r]] : (vector<8xi16>) -> !fir.vector<8:i16>
 646
 647 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>>
 648 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>>
 649 ! CHECK-LLVMIR: %{{[0-9]+}} = llvm.and %[[arg1]], %[[arg2]] : vector<8xi16>
 650
 651 ! CHECK: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16
 652 ! CHECK: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16
 653 ! CHECK: %{{[0-9]+}} = and <8 x i16> %[[arg1]], %[[arg2]]
 654 end subroutine vec_and_test_i16
 655
 656 ! CHECK-LABEL: vec_and_test_i32
 657 subroutine vec_and_test_i32(arg1, arg2)
 658   vector(integer(4)) :: r, arg1, arg2
 659   r = vec_and(arg1, arg2)
 660 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>>
 661 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>>
 662 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:i32>) -> vector<4xi32>
 663 ! CHECK-FIR: %[[varg2:.*]] = fir.convert %[[arg2]] : (!fir.vector<4:i32>) -> vector<4xi32>
 664 ! CHECK-FIR: %[[r:.*]] = arith.andi %[[varg1]], %[[varg2]] : vector<4xi32>
 665 ! CHECK-FIR: %{{[0-9]+}} = fir.convert %[[r]] : (vector<4xi32>) -> !fir.vector<4:i32>
 666
 667 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>>
 668 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>>
 669 ! CHECK-LLVMIR: %{{[0-9]+}} = llvm.and %[[arg1]], %[[arg2]] : vector<4xi32>
 670
 671 ! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16
 672 ! CHECK: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16
 673 ! CHECK: %{{[0-9]+}} = and <4 x i32> %[[arg1]], %[[arg2]]
 674 end subroutine vec_and_test_i32
 675
 676 ! CHECK-LABEL: vec_and_test_i64
 677 subroutine vec_and_test_i64(arg1, arg2)
 678   vector(integer(8)) :: r, arg1, arg2
 679   r = vec_and(arg1, arg2)
 680 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:i64>>
 681 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:i64>>
 682 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<2:i64>) -> vector<2xi64>
 683 ! CHECK-FIR: %[[varg2:.*]] = fir.convert %[[arg2]] : (!fir.vector<2:i64>) -> vector<2xi64>
 684 ! CHECK-FIR: %[[r:.*]] = arith.andi %[[varg1]], %[[varg2]] : vector<2xi64>
 685 ! CHECK-FIR: %{{[0-9]+}} = fir.convert %[[r]] : (vector<2xi64>) -> !fir.vector<2:i64>
 686
 687 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>>
 688 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>>
 689 ! CHECK-LLVMIR: %{{[0-9]+}} = llvm.and %[[arg1]], %[[arg2]] : vector<2xi64>
 690
 691 ! CHECK: %[[arg1:.*]] = load <2 x i64>, ptr %{{.*}}, align 16
 692 ! CHECK: %[[arg2:.*]] = load <2 x i64>, ptr %{{.*}}, align 16
 693 ! CHECK: %{{[0-9]+}} = and <2 x i64> %[[arg1]], %[[arg2]]
 694 end subroutine vec_and_test_i64
 695
 696 ! CHECK-LABEL: vec_and_test_u8
 697 subroutine vec_and_test_u8(arg1, arg2)
 698   vector(unsigned(1)) :: r, arg1, arg2
 699   r = vec_and(arg1, arg2)
 700 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:ui8>>
 701 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:ui8>>
 702 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<16:ui8>) -> vector<16xi8>
 703 ! CHECK-FIR: %[[varg2:.*]] = fir.convert %[[arg2]] : (!fir.vector<16:ui8>) -> vector<16xi8>
 704 ! CHECK-FIR: %[[r:.*]] = arith.andi %[[varg1]], %[[varg2]] : vector<16xi8>
 705 ! CHECK-FIR: %{{[0-9]+}} = fir.convert %[[r]] : (vector<16xi8>) -> !fir.vector<16:ui8>
 706
 707 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>>
 708 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>>
 709 ! CHECK-LLVMIR: %{{[0-9]+}} = llvm.and %[[arg1]], %[[arg2]] : vector<16xi8>
 710
 711 ! CHECK: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16
 712 ! CHECK: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16
 713 ! CHECK: %{{[0-9]+}} = and <16 x i8> %[[arg1]], %[[arg2]]
 714 end subroutine vec_and_test_u8
 715
 716 ! CHECK-LABEL: vec_and_test_u16
 717 subroutine vec_and_test_u16(arg1, arg2)
 718   vector(unsigned(2)) :: r, arg1, arg2
 719   r = vec_and(arg1, arg2)
 720 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:ui16>>
 721 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:ui16>>
 722 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<8:ui16>) -> vector<8xi16>
 723 ! CHECK-FIR: %[[varg2:.*]] = fir.convert %[[arg2]] : (!fir.vector<8:ui16>) -> vector<8xi16>
 724 ! CHECK-FIR: %[[r:.*]] = arith.andi %[[varg1]], %[[varg2]] : vector<8xi16>
 725 ! CHECK-FIR: %{{[0-9]+}} = fir.convert %[[r]] : (vector<8xi16>) -> !fir.vector<8:ui16>
 726
 727 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>>
 728 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>>
 729 ! CHECK-LLVMIR: %{{[0-9]+}} = llvm.and %[[arg1]], %[[arg2]] : vector<8xi16>
 730
 731 ! CHECK: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16
 732 ! CHECK: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16
 733 ! CHECK: %{{[0-9]+}} = and <8 x i16> %[[arg1]], %[[arg2]]
 734 end subroutine vec_and_test_u16
 735
 736 ! CHECK-LABEL: vec_and_test_u32
 737 subroutine vec_and_test_u32(arg1, arg2)
 738   vector(unsigned(4)) :: r, arg1, arg2
 739   r = vec_and(arg1, arg2)
 740 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:ui32>>
 741 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:ui32>>
 742 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:ui32>) -> vector<4xi32>
 743 ! CHECK-FIR: %[[varg2:.*]] = fir.convert %[[arg2]] : (!fir.vector<4:ui32>) -> vector<4xi32>
 744 ! CHECK-FIR: %[[r:.*]] = arith.andi %[[varg1]], %[[varg2]] : vector<4xi32>
 745 ! CHECK-FIR: %{{[0-9]+}} = fir.convert %[[r]] : (vector<4xi32>) -> !fir.vector<4:ui32>
 746
 747 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>>
 748 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>>
 749 ! CHECK-LLVMIR: %{{[0-9]+}} = llvm.and %[[arg1]], %[[arg2]] : vector<4xi32>
 750
 751 ! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16
 752 ! CHECK: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16
 753 ! CHECK: %{{[0-9]+}} = and <4 x i32> %[[arg1]], %[[arg2]]
 754 end subroutine vec_and_test_u32
 755
 756 ! CHECK-LABEL: vec_and_test_u64
 757 subroutine vec_and_test_u64(arg1, arg2)
 758   vector(unsigned(8)) :: r, arg1, arg2
 759   r = vec_and(arg1, arg2)
 760 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:ui64>>
 761 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:ui64>>
 762 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<2:ui64>) -> vector<2xi64>
 763 ! CHECK-FIR: %[[varg2:.*]] = fir.convert %[[arg2]] : (!fir.vector<2:ui64>) -> vector<2xi64>
 764 ! CHECK-FIR: %[[r:.*]] = arith.andi %[[varg1]], %[[varg2]] : vector<2xi64>
 765 ! CHECK-FIR: %{{[0-9]+}} = fir.convert %[[r]] : (vector<2xi64>) -> !fir.vector<2:ui64>
 766
 767 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>>
 768 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>>
 769 ! CHECK-LLVMIR: %{{[0-9]+}} = llvm.and %[[arg1]], %[[arg2]] : vector<2xi64>
 770
 771 ! CHECK: %[[arg1:.*]] = load <2 x i64>, ptr %{{.*}}, align 16
 772 ! CHECK: %[[arg2:.*]] = load <2 x i64>, ptr %{{.*}}, align 16
 773 ! CHECK: %{{[0-9]+}} = and <2 x i64> %[[arg1]], %[[arg2]]
 774 end subroutine vec_and_test_u64
 775
 776 ! CHECK-LABEL: vec_and_testf32
 777 subroutine vec_and_testf32(arg1, arg2)
 778   vector(real(4)) :: r, arg1, arg2
 779   r = vec_and(arg1, arg2)
 780 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:f32>>
 781 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:f32>>
 782 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:f32>) -> vector<4xf32>
 783 ! CHECK-FIR: %[[varg2:.*]] = fir.convert %[[arg2]] : (!fir.vector<4:f32>) -> vector<4xf32>
 784 ! CHECK-FIR: %[[bc1:.*]] = vector.bitcast %[[varg1]] : vector<4xf32> to vector<4xi32>
 785 ! CHECK-FIR: %[[bc2:.*]] = vector.bitcast %[[varg2]] : vector<4xf32> to vector<4xi32>
 786 ! CHECK-FIR: %[[r:.*]] = arith.andi %[[bc1]], %[[bc2]] : vector<4xi32>
 787 ! CHECK-FIR: %[[vr:.*]] = vector.bitcast %[[r]] : vector<4xi32> to vector<4xf32>
 788 ! CHECK-FIR: %{{[0-9]+}} = fir.convert %[[vr]] : (vector<4xf32>) -> !fir.vector<4:f32>
 789
 790 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xf32>>
 791 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xf32>>
 792 ! CHECK-LLVMIR: %[[bc1:.*]] = llvm.bitcast %[[arg1]] : vector<4xf32> to vector<4xi32>
 793 ! CHECK-LLVMIR: %[[bc2:.*]] = llvm.bitcast %[[arg2]] : vector<4xf32> to vector<4xi32>
 794 ! CHECK-LLVMIR: %[[r:.*]] = llvm.and %[[bc1]], %[[bc2]]  : vector<4xi32>
 795 ! CHECK-LLVMIR: %{{[0-9]+}} = llvm.bitcast %[[r]] : vector<4xi32> to vector<4xf32>
 796
 797 ! CHECK: %[[arg1:.*]] = load <4 x float>, ptr %{{.*}}, align 16
 798 ! CHECK: %[[arg2:.*]] = load <4 x float>, ptr %{{.*}}, align 16
 799 ! CHECK: %[[bc1:.*]] = bitcast <4 x float> %[[arg1]] to <4 x i32>
 800 ! CHECK: %[[bc2:.*]] = bitcast <4 x float> %[[arg2]] to <4 x i32>
 801 ! CHECK: %[[r:.*]] = and <4 x i32> %[[bc1]], %[[bc2]]
 802 ! CHECK: %{{[0-9]+}} = bitcast <4 x i32> %[[r]] to <4 x float>
 803 end subroutine vec_and_testf32
 804
 805 ! CHECK-LABEL: vec_and_testf64
 806 subroutine vec_and_testf64(arg1, arg2)
 807   vector(real(8)) :: r, arg1, arg2
 808   r = vec_and(arg1, arg2)
 809 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:f64>>
 810 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:f64>>
 811 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<2:f64>) -> vector<2xf64>
 812 ! CHECK-FIR: %[[varg2:.*]] = fir.convert %[[arg2]] : (!fir.vector<2:f64>) -> vector<2xf64>
 813 ! CHECK-FIR: %[[bc1:.*]] = vector.bitcast %[[varg1]] : vector<2xf64> to vector<2xi64>
 814 ! CHECK-FIR: %[[bc2:.*]] = vector.bitcast %[[varg2]] : vector<2xf64> to vector<2xi64>
 815 ! CHECK-FIR: %[[r:.*]] = arith.andi %[[bc1]], %[[bc2]] : vector<2xi64>
 816 ! CHECK-FIR: %[[vr:.*]] = vector.bitcast %[[r]] : vector<2xi64> to vector<2xf64>
 817 ! CHECK-FIR: %{{[0-9]+}} = fir.convert %[[vr]] : (vector<2xf64>) -> !fir.vector<2:f64>
 818
 819 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xf64>>
 820 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xf64>>
 821 ! CHECK-LLVMIR: %[[bc1:.*]] = llvm.bitcast %[[arg1]] : vector<2xf64> to vector<2xi64>
 822 ! CHECK-LLVMIR: %[[bc2:.*]] = llvm.bitcast %[[arg2]] : vector<2xf64> to vector<2xi64>
 823 ! CHECK-LLVMIR: %[[r:.*]] = llvm.and %[[bc1]], %[[bc2]]  : vector<2xi64>
 824 ! CHECK-LLVMIR: %{{[0-9]+}} = llvm.bitcast %[[r]] : vector<2xi64> to vector<2xf64>
 825
 826 ! CHECK: %[[arg1:.*]] = load <2 x double>, ptr %{{.*}}, align 16
 827 ! CHECK: %[[arg2:.*]] = load <2 x double>, ptr %{{.*}}, align 16
 828 ! CHECK: %[[bc1:.*]] = bitcast <2 x double> %[[arg1]] to <2 x i64>
 829 ! CHECK: %[[bc2:.*]] = bitcast <2 x double> %[[arg2]] to <2 x i64>
 830 ! CHECK: %[[r:.*]] = and <2 x i64> %[[bc1]], %[[bc2]]
 831 ! CHECK: %{{[0-9]+}} = bitcast <2 x i64> %[[r]] to <2 x double>
 832 end subroutine vec_and_testf64
 833
 834 !----------------------
 835 ! vec_xor
 836 !----------------------
 837
 838 ! CHECK-LABEL: vec_xor_test_i8
 839 subroutine vec_xor_test_i8(arg1, arg2)
 840   vector(integer(1)) :: r, arg1, arg2
 841   r = vec_xor(arg1, arg2)
 842 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:i8>>
 843 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:i8>>
 844 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<16:i8>) -> vector<16xi8>
 845 ! CHECK-FIR: %[[varg2:.*]] = fir.convert %[[arg2]] : (!fir.vector<16:i8>) -> vector<16xi8>
 846 ! CHECK-FIR: %[[r:.*]] = arith.xori %[[varg1]], %[[varg2]] : vector<16xi8>
 847 ! CHECK-FIR: %{{[0-9]+}} = fir.convert %[[r]] : (vector<16xi8>) -> !fir.vector<16:i8>
 848
 849 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>>
 850 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>>
 851 ! CHECK-LLVMIR: %{{[0-9]+}} = llvm.xor %[[arg1]], %[[arg2]] : vector<16xi8>
 852
 853 ! CHECK: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16
 854 ! CHECK: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16
 855 ! CHECK: %{{[0-9]+}} = xor <16 x i8> %[[arg1]], %[[arg2]]
 856 end subroutine vec_xor_test_i8
 857
 858 ! CHECK-LABEL: vec_xor_test_i16
 859 subroutine vec_xor_test_i16(arg1, arg2)
 860   vector(integer(2)) :: r, arg1, arg2
 861   r = vec_xor(arg1, arg2)
 862 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:i16>>
 863 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:i16>>
 864 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<8:i16>) -> vector<8xi16>
 865 ! CHECK-FIR: %[[varg2:.*]] = fir.convert %[[arg2]] : (!fir.vector<8:i16>) -> vector<8xi16>
 866 ! CHECK-FIR: %[[r:.*]] = arith.xori %[[varg1]], %[[varg2]] : vector<8xi16>
 867 ! CHECK-FIR: %{{[0-9]+}} = fir.convert %[[r]] : (vector<8xi16>) -> !fir.vector<8:i16>
 868
 869 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>>
 870 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>>
 871 ! CHECK-LLVMIR: %{{[0-9]+}} = llvm.xor %[[arg1]], %[[arg2]] : vector<8xi16>
 872
 873 ! CHECK: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16
 874 ! CHECK: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16
 875 ! CHECK: %{{[0-9]+}} = xor <8 x i16> %[[arg1]], %[[arg2]]
 876 end subroutine vec_xor_test_i16
 877
 878 ! CHECK-LABEL: vec_xor_test_i32
 879 subroutine vec_xor_test_i32(arg1, arg2)
 880   vector(integer(4)) :: r, arg1, arg2
 881   r = vec_xor(arg1, arg2)
 882 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>>
 883 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:i32>>
 884 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:i32>) -> vector<4xi32>
 885 ! CHECK-FIR: %[[varg2:.*]] = fir.convert %[[arg2]] : (!fir.vector<4:i32>) -> vector<4xi32>
 886 ! CHECK-FIR: %[[r:.*]] = arith.xori %[[varg1]], %[[varg2]] : vector<4xi32>
 887 ! CHECK-FIR: %{{[0-9]+}} = fir.convert %[[r]] : (vector<4xi32>) -> !fir.vector<4:i32>
 888
 889 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>>
 890 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>>
 891 ! CHECK-LLVMIR: %{{[0-9]+}} = llvm.xor %[[arg1]], %[[arg2]] : vector<4xi32>
 892
 893 ! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16
 894 ! CHECK: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16
 895 ! CHECK: %{{[0-9]+}} = xor <4 x i32> %[[arg1]], %[[arg2]]
 896 end subroutine vec_xor_test_i32
 897
 898 ! CHECK-LABEL: vec_xor_test_i64
 899 subroutine vec_xor_test_i64(arg1, arg2)
 900   vector(integer(8)) :: r, arg1, arg2
 901   r = vec_xor(arg1, arg2)
 902 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:i64>>
 903 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:i64>>
 904 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<2:i64>) -> vector<2xi64>
 905 ! CHECK-FIR: %[[varg2:.*]] = fir.convert %[[arg2]] : (!fir.vector<2:i64>) -> vector<2xi64>
 906 ! CHECK-FIR: %[[r:.*]] = arith.xori %[[varg1]], %[[varg2]] : vector<2xi64>
 907 ! CHECK-FIR: %{{[0-9]+}} = fir.convert %[[r]] : (vector<2xi64>) -> !fir.vector<2:i64>
 908
 909 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>>
 910 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>>
 911 ! CHECK-LLVMIR: %{{[0-9]+}} = llvm.xor %[[arg1]], %[[arg2]] : vector<2xi64>
 912
 913 ! CHECK: %[[arg1:.*]] = load <2 x i64>, ptr %{{.*}}, align 16
 914 ! CHECK: %[[arg2:.*]] = load <2 x i64>, ptr %{{.*}}, align 16
 915 ! CHECK: %{{[0-9]+}} = xor <2 x i64> %[[arg1]], %[[arg2]]
 916 end subroutine vec_xor_test_i64
 917
 918 ! CHECK-LABEL: vec_xor_test_u8
 919 subroutine vec_xor_test_u8(arg1, arg2)
 920   vector(unsigned(1)) :: r, arg1, arg2
 921   r = vec_xor(arg1, arg2)
 922 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:ui8>>
 923 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<16:ui8>>
 924 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<16:ui8>) -> vector<16xi8>
 925 ! CHECK-FIR: %[[varg2:.*]] = fir.convert %[[arg2]] : (!fir.vector<16:ui8>) -> vector<16xi8>
 926 ! CHECK-FIR: %[[r:.*]] = arith.xori %[[varg1]], %[[varg2]] : vector<16xi8>
 927 ! CHECK-FIR: %{{[0-9]+}} = fir.convert %[[r]] : (vector<16xi8>) -> !fir.vector<16:ui8>
 928
 929 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>>
 930 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<16xi8>>
 931 ! CHECK-LLVMIR: %{{[0-9]+}} = llvm.xor %[[arg1]], %[[arg2]] : vector<16xi8>
 932
 933 ! CHECK: %[[arg1:.*]] = load <16 x i8>, ptr %{{.*}}, align 16
 934 ! CHECK: %[[arg2:.*]] = load <16 x i8>, ptr %{{.*}}, align 16
 935 ! CHECK: %{{[0-9]+}} = xor <16 x i8> %[[arg1]], %[[arg2]]
 936 end subroutine vec_xor_test_u8
 937
 938 ! CHECK-LABEL: vec_xor_test_u16
 939 subroutine vec_xor_test_u16(arg1, arg2)
 940   vector(unsigned(2)) :: r, arg1, arg2
 941   r = vec_xor(arg1, arg2)
 942 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:ui16>>
 943 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<8:ui16>>
 944 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<8:ui16>) -> vector<8xi16>
 945 ! CHECK-FIR: %[[varg2:.*]] = fir.convert %[[arg2]] : (!fir.vector<8:ui16>) -> vector<8xi16>
 946 ! CHECK-FIR: %[[r:.*]] = arith.xori %[[varg1]], %[[varg2]] : vector<8xi16>
 947 ! CHECK-FIR: %{{[0-9]+}} = fir.convert %[[r]] : (vector<8xi16>) -> !fir.vector<8:ui16>
 948
 949 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>>
 950 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<8xi16>>
 951 ! CHECK-LLVMIR: %{{[0-9]+}} = llvm.xor %[[arg1]], %[[arg2]] : vector<8xi16>
 952
 953 ! CHECK: %[[arg1:.*]] = load <8 x i16>, ptr %{{.*}}, align 16
 954 ! CHECK: %[[arg2:.*]] = load <8 x i16>, ptr %{{.*}}, align 16
 955 ! CHECK: %{{[0-9]+}} = xor <8 x i16> %[[arg1]], %[[arg2]]
 956 end subroutine vec_xor_test_u16
 957
 958 ! CHECK-LABEL: vec_xor_test_u32
 959 subroutine vec_xor_test_u32(arg1, arg2)
 960   vector(unsigned(4)) :: r, arg1, arg2
 961   r = vec_xor(arg1, arg2)
 962 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:ui32>>
 963 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:ui32>>
 964 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:ui32>) -> vector<4xi32>
 965 ! CHECK-FIR: %[[varg2:.*]] = fir.convert %[[arg2]] : (!fir.vector<4:ui32>) -> vector<4xi32>
 966 ! CHECK-FIR: %[[r:.*]] = arith.xori %[[varg1]], %[[varg2]] : vector<4xi32>
 967 ! CHECK-FIR: %{{[0-9]+}} = fir.convert %[[r]] : (vector<4xi32>) -> !fir.vector<4:ui32>
 968
 969 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>>
 970 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xi32>>
 971 ! CHECK-LLVMIR: %{{[0-9]+}} = llvm.xor %[[arg1]], %[[arg2]] : vector<4xi32>
 972
 973 ! CHECK: %[[arg1:.*]] = load <4 x i32>, ptr %{{.*}}, align 16
 974 ! CHECK: %[[arg2:.*]] = load <4 x i32>, ptr %{{.*}}, align 16
 975 ! CHECK: %{{[0-9]+}} = xor <4 x i32> %[[arg1]], %[[arg2]]
 976 end subroutine vec_xor_test_u32
 977
 978 ! CHECK-LABEL: vec_xor_test_u64
 979 subroutine vec_xor_test_u64(arg1, arg2)
 980   vector(unsigned(8)) :: r, arg1, arg2
 981   r = vec_xor(arg1, arg2)
 982 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:ui64>>
 983 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:ui64>>
 984 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<2:ui64>) -> vector<2xi64>
 985 ! CHECK-FIR: %[[varg2:.*]] = fir.convert %[[arg2]] : (!fir.vector<2:ui64>) -> vector<2xi64>
 986 ! CHECK-FIR: %[[r:.*]] = arith.xori %[[varg1]], %[[varg2]] : vector<2xi64>
 987 ! CHECK-FIR: %{{[0-9]+}} = fir.convert %[[r]] : (vector<2xi64>) -> !fir.vector<2:ui64>
 988
 989 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>>
 990 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xi64>>
 991 ! CHECK-LLVMIR: %{{[0-9]+}} = llvm.xor %[[arg1]], %[[arg2]] : vector<2xi64>
 992
 993 ! CHECK: %[[arg1:.*]] = load <2 x i64>, ptr %{{.*}}, align 16
 994 ! CHECK: %[[arg2:.*]] = load <2 x i64>, ptr %{{.*}}, align 16
 995 ! CHECK: %{{[0-9]+}} = xor <2 x i64> %[[arg1]], %[[arg2]]
 996 end subroutine vec_xor_test_u64
 997
 998 ! CHECK-LABEL: vec_xor_testf32
 999 subroutine vec_xor_testf32(arg1, arg2)
1000   vector(real(4)) :: r, arg1, arg2
1001   r = vec_xor(arg1, arg2)
1002 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:f32>>
1003 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<4:f32>>
1004 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<4:f32>) -> vector<4xf32>
1005 ! CHECK-FIR: %[[varg2:.*]] = fir.convert %[[arg2]] : (!fir.vector<4:f32>) -> vector<4xf32>
1006 ! CHECK-FIR: %[[bc1:.*]] = vector.bitcast %[[varg1]] : vector<4xf32> to vector<4xi32>
1007 ! CHECK-FIR: %[[bc2:.*]] = vector.bitcast %[[varg2]] : vector<4xf32> to vector<4xi32>
1008 ! CHECK-FIR: %[[r:.*]] = arith.xori %[[bc1]], %[[bc2]] : vector<4xi32>
1009 ! CHECK-FIR: %[[vr:.*]] = vector.bitcast %[[r]] : vector<4xi32> to vector<4xf32>
1010 ! CHECK-FIR: %{{[0-9]+}} = fir.convert %[[vr]] : (vector<4xf32>) -> !fir.vector<4:f32>
1011
1012 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xf32>>
1013 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<4xf32>>
1014 ! CHECK-LLVMIR: %[[bc1:.*]] = llvm.bitcast %[[arg1]] : vector<4xf32> to vector<4xi32>
1015 ! CHECK-LLVMIR: %[[bc2:.*]] = llvm.bitcast %[[arg2]] : vector<4xf32> to vector<4xi32>
1016 ! CHECK-LLVMIR: %[[r:.*]] = llvm.xor %[[bc1]], %[[bc2]]  : vector<4xi32>
1017 ! CHECK-LLVMIR: %{{[0-9]+}} = llvm.bitcast %[[r]] : vector<4xi32> to vector<4xf32>
1018
1019 ! CHECK: %[[arg1:.*]] = load <4 x float>, ptr %{{.*}}, align 16
1020 ! CHECK: %[[arg2:.*]] = load <4 x float>, ptr %{{.*}}, align 16
1021 ! CHECK: %[[bc1:.*]] = bitcast <4 x float> %[[arg1]] to <4 x i32>
1022 ! CHECK: %[[bc2:.*]] = bitcast <4 x float> %[[arg2]] to <4 x i32>
1023 ! CHECK: %[[r:.*]] = xor <4 x i32> %[[bc1]], %[[bc2]]
1024 ! CHECK: %{{[0-9]+}} = bitcast <4 x i32> %[[r]] to <4 x float>
1025 end subroutine vec_xor_testf32
1026
1027 ! CHECK-LABEL: vec_xor_testf64
1028 subroutine vec_xor_testf64(arg1, arg2)
1029   vector(real(8)) :: r, arg1, arg2
1030   r = vec_xor(arg1, arg2)
1031 ! CHECK-FIR: %[[arg1:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:f64>>
1032 ! CHECK-FIR: %[[arg2:.*]] = fir.load %{{.*}} : !fir.ref<!fir.vector<2:f64>>
1033 ! CHECK-FIR: %[[varg1:.*]] = fir.convert %[[arg1]] : (!fir.vector<2:f64>) -> vector<2xf64>
1034 ! CHECK-FIR: %[[varg2:.*]] = fir.convert %[[arg2]] : (!fir.vector<2:f64>) -> vector<2xf64>
1035 ! CHECK-FIR: %[[bc1:.*]] = vector.bitcast %[[varg1]] : vector<2xf64> to vector<2xi64>
1036 ! CHECK-FIR: %[[bc2:.*]] = vector.bitcast %[[varg2]] : vector<2xf64> to vector<2xi64>
1037 ! CHECK-FIR: %[[r:.*]] = arith.xori %[[bc1]], %[[bc2]] : vector<2xi64>
1038 ! CHECK-FIR: %[[vr:.*]] = vector.bitcast %[[r]] : vector<2xi64> to vector<2xf64>
1039 ! CHECK-FIR: %{{[0-9]+}} = fir.convert %[[vr]] : (vector<2xf64>) -> !fir.vector<2:f64>
1040
1041 ! CHECK-LLVMIR: %[[arg1:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xf64>>
1042 ! CHECK-LLVMIR: %[[arg2:.*]] = llvm.load %{{.*}} : !llvm.ptr<vector<2xf64>>
1043 ! CHECK-LLVMIR: %[[bc1:.*]] = llvm.bitcast %[[arg1]] : vector<2xf64> to vector<2xi64>
1044 ! CHECK-LLVMIR: %[[bc2:.*]] = llvm.bitcast %[[arg2]] : vector<2xf64> to vector<2xi64>
1045 ! CHECK-LLVMIR: %[[r:.*]] = llvm.xor %[[bc1]], %[[bc2]]  : vector<2xi64>
1046 ! CHECK-LLVMIR: %{{[0-9]+}} = llvm.bitcast %[[r]] : vector<2xi64> to vector<2xf64>
1047
1048 ! CHECK: %[[arg1:.*]] = load <2 x double>, ptr %{{.*}}, align 16
1049 ! CHECK: %[[arg2:.*]] = load <2 x double>, ptr %{{.*}}, align 16
1050 ! CHECK: %[[bc1:.*]] = bitcast <2 x double> %[[arg1]] to <2 x i64>
1051 ! CHECK: %[[bc2:.*]] = bitcast <2 x double> %[[arg2]] to <2 x i64>
1052 ! CHECK: %[[r:.*]] = xor <2 x i64> %[[bc1]], %[[bc2]]
1053 ! CHECK: %{{[0-9]+}} = bitcast <2 x i64> %[[r]] to <2 x double>
1054 end subroutine vec_xor_testf64
1055