1 # RUN: llc -O0 -mtriple arm-- -mattr=+v6 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,ARM
2 # RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,THUMB
4 define void @test_shifts_to_revsh() { ret void }
5 define void @test_shifts_to_revsh_commutative() { ret void }
6 define void @test_shifts_no_revsh_constants() { ret void }
9 name: test_shifts_to_revsh
10 # CHECK-LABEL: name: test_shifts_to_revsh
14 # CHECK: selected: true
16 - { id: 0, class: gprb }
17 - { id: 1, class: gprb }
18 - { id: 2, class: gprb }
19 - { id: 3, class: gprb }
20 - { id: 4, class: gprb }
21 - { id: 5, class: gprb }
22 - { id: 6, class: gprb }
23 - { id: 7, class: gprb }
24 - { id: 8, class: gprb }
25 - { id: 9, class: gprb }
31 ; ARM: [[VREGX:%[0-9]+]]:gpr = COPY $r0
32 ; THUMB: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
34 %1(s32) = G_CONSTANT i32 24
35 %2(s32) = G_SHL %0(s32), %1(s32)
37 %3(s32) = G_CONSTANT i32 16
38 %4(s32) = G_ASHR %2(s32), %3(s32)
40 %5(s32) = G_CONSTANT i32 8
41 %6(s32) = G_LSHR %0(s32), %5(s32)
43 %7(s32) = G_CONSTANT i32 255
44 %8(s32) = G_AND %6(s32), %7(s32)
46 %9(s32) = G_OR %4(s32), %8(s32)
47 ; ARM: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]]
48 ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2REVSH [[VREGX]]
51 ; CHECK: $r0 = COPY [[VREGR]]
53 BX_RET 14, $noreg, implicit $r0
54 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
57 name: test_shifts_to_revsh_commutative
58 # CHECK-LABEL: name: test_shifts_to_revsh_commutative
62 # CHECK: selected: true
64 - { id: 0, class: gprb }
65 - { id: 1, class: gprb }
66 - { id: 2, class: gprb }
67 - { id: 3, class: gprb }
68 - { id: 4, class: gprb }
69 - { id: 5, class: gprb }
70 - { id: 6, class: gprb }
71 - { id: 7, class: gprb }
72 - { id: 8, class: gprb }
73 - { id: 9, class: gprb }
79 ; ARM: [[VREGX:%[0-9]+]]:gpr = COPY $r0
80 ; THUMB: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
82 %1(s32) = G_CONSTANT i32 24
83 %2(s32) = G_SHL %0(s32), %1(s32)
85 %3(s32) = G_CONSTANT i32 16
86 %4(s32) = G_ASHR %2(s32), %3(s32)
88 %5(s32) = G_CONSTANT i32 8
89 %6(s32) = G_LSHR %0(s32), %5(s32)
91 %7(s32) = G_CONSTANT i32 255
92 %8(s32) = G_AND %6(s32), %7(s32)
94 %9(s32) = G_OR %8(s32), %4(s32)
95 ; ARM: [[VREGR:%[0-9]+]]:gpr = REVSH [[VREGX]]
96 ; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2REVSH [[VREGX]]
99 ; CHECK: $r0 = COPY [[VREGR]]
101 BX_RET 14, $noreg, implicit $r0
102 ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
105 name: test_shifts_no_revsh_constants
106 # CHECK-LABEL: name: test_shifts_no_revsh_constants
108 regBankSelected: true
110 # CHECK: selected: true
112 - { id: 0, class: gprb }
113 - { id: 1, class: gprb }
114 - { id: 2, class: gprb }
115 - { id: 3, class: gprb }
116 - { id: 4, class: gprb }
117 - { id: 5, class: gprb }
118 - { id: 6, class: gprb }
119 - { id: 7, class: gprb }
120 - { id: 8, class: gprb }
121 - { id: 9, class: gprb }
128 %1(s32) = G_CONSTANT i32 16 ; REVSH needs 24 here
129 %2(s32) = G_SHL %0(s32), %1(s32)
131 %3(s32) = G_CONSTANT i32 24 ; REVSH needs 16 here
132 %4(s32) = G_ASHR %2(s32), %3(s32)
134 %5(s32) = G_CONSTANT i32 8
135 %6(s32) = G_LSHR %0(s32), %5(s32)
137 %7(s32) = G_CONSTANT i32 255
138 %8(s32) = G_AND %6(s32), %7(s32)
140 %9(s32) = G_OR %4(s32), %8(s32)
141 ; We don't really care how this is folded as long as it's not into a REVSH.
146 BX_RET 14, $noreg, implicit $r0