1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -pre-RA-sched=source | FileCheck %s
3 ; Test that we correctly align elements when using va_arg
5 define i64 @test1(i32 %i, ...) nounwind optsize {
7 ; CHECK: @ %bb.0: @ %entry
9 ; CHECK-NEXT: sub sp, sp, #16
10 ; CHECK-NEXT: add r0, sp, #4
11 ; CHECK-NEXT: stmib sp, {r1, r2, r3}
12 ; CHECK-NEXT: add r0, r0, #7
13 ; CHECK-NEXT: bic r1, r0, #7
14 ; CHECK-NEXT: orr r0, r1, #4
15 ; CHECK-NEXT: str r0, [sp]
16 ; CHECK-NEXT: ldr r0, [r1]
17 ; CHECK-NEXT: add r2, r1, #8
18 ; CHECK-NEXT: str r2, [sp]
19 ; CHECK-NEXT: ldr r1, [r1, #4]
20 ; CHECK-NEXT: add sp, sp, #16
23 %g = alloca ptr, align 4
24 call void @llvm.va_start(ptr %g)
25 %0 = va_arg ptr %g, i64
26 call void @llvm.va_end(ptr %g)
30 define double @test2(i32 %a, ptr %b, ...) nounwind optsize {
32 ; CHECK: @ %bb.0: @ %entry
33 ; CHECK-NEXT: .pad #12
34 ; CHECK-NEXT: sub sp, sp, #12
35 ; CHECK-NEXT: add r0, sp, #4
36 ; CHECK-NEXT: stmib sp, {r2, r3}
37 ; CHECK-NEXT: add r0, r0, #11
38 ; CHECK-NEXT: bic r0, r0, #3
39 ; CHECK-NEXT: str r2, [r1]
40 ; CHECK-NEXT: add r1, r0, #8
41 ; CHECK-NEXT: str r1, [sp]
42 ; CHECK-NEXT: vldr d16, [r0]
43 ; CHECK-NEXT: vmov r0, r1, d16
44 ; CHECK-NEXT: add sp, sp, #12
47 %ap = alloca ptr, align 4 ; <ptr> [#uses=3]
48 call void @llvm.va_start(ptr %ap)
49 %0 = va_arg ptr %ap, i32 ; <i32> [#uses=0]
51 %1 = va_arg ptr %ap, double ; <double> [#uses=1]
52 call void @llvm.va_end(ptr %ap)
57 declare void @llvm.va_start(ptr) nounwind
59 declare void @llvm.va_end(ptr) nounwind