1 # RUN: llc -march=hexagon -run-pass machine-sink -o - %s | FileCheck %s
3 # Test that MachineSink does not sink F2_conv_w2sf.
4 # CHECK: name:{{.*}} main
5 # CHECK: J2_call @feclearexcept
7 # CHECK: J2_call @fetestexcept
9 target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
10 target triple = "hexagon"
12 @.str = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 1
14 ; Function Attrs: mustprogress nofree norecurse nosync nounwind readnone willreturn
15 define dso_local i32 @syst_int32_to_float32(i32 %a) local_unnamed_addr #0 {
17 %conv = sitofp i32 %a to float
18 %0 = bitcast float %conv to i32
22 ; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
23 declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1
25 ; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
26 declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) #1
28 ; Function Attrs: nounwind
29 define dso_local i32 @main() local_unnamed_addr #2 {
31 %a = alloca i32, align 4
32 %b = alloca i32, align 4
33 %c = alloca i32, align 4
34 %a.0.a.0.a.0.a.0..sroa_cast = bitcast i32* %a to i8*
35 call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %a.0.a.0.a.0.a.0..sroa_cast)
36 store volatile i32 -16777235, i32* %a, align 4, !tbaa !3
37 %b.0.b.0.b.0.b.0..sroa_cast = bitcast i32* %b to i8*
38 call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %b.0.b.0.b.0.b.0..sroa_cast)
39 store volatile i32 34, i32* %b, align 4, !tbaa !3
40 %c.0.c.0.c.0.c.0..sroa_cast = bitcast i32* %c to i8*
41 call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %c.0.c.0.c.0.c.0..sroa_cast)
42 store volatile i32 34, i32* %c, align 4, !tbaa !3
43 %b.0.b.0.b.0.b.0.29 = load volatile i32, i32* %b, align 4, !tbaa !3
44 %cmp30 = icmp sgt i32 %b.0.b.0.b.0.b.0.29, 0
45 br i1 %cmp30, label %for.body, label %if.end
47 for.cond.for.cond.cleanup_crit_edge: ; preds = %for.body
48 %conv.i.le = sitofp i32 %a.0.a.0.a.0.a.0. to float
49 %0 = bitcast float %conv.i.le to i32
50 %phi.cmp = icmp ugt i32 %0, 100
51 br i1 %phi.cmp, label %if.then, label %if.end
53 for.body: ; preds = %entry, %for.body
54 %i.031 = phi i32 [ %inc4, %for.body ], [ 0, %entry ]
55 %c.0.c.0.c.0.c.0. = load volatile i32, i32* %c, align 4, !tbaa !3
56 %inc = add nsw i32 %c.0.c.0.c.0.c.0., 1
57 store volatile i32 %inc, i32* %c, align 4, !tbaa !3
58 %call = tail call i32 @feclearexcept(i32 31) #5
59 %a.0.a.0.a.0.a.0. = load volatile i32, i32* %a, align 4, !tbaa !3
60 %call2 = tail call i32 @fetestexcept(i32 31) #5
61 %call3 = tail call i32 (i8*, ...) @printf(i8* nonnull dereferenceable(1) getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %call2) #5
62 %inc4 = add nuw nsw i32 %i.031, 1
63 %b.0.b.0.b.0.b.0. = load volatile i32, i32* %b, align 4, !tbaa !3
64 %cmp = icmp slt i32 %inc4, %b.0.b.0.b.0.b.0.
65 br i1 %cmp, label %for.body, label %for.cond.for.cond.cleanup_crit_edge, !llvm.loop !7
67 if.then: ; preds = %for.cond.for.cond.cleanup_crit_edge
68 %a.0.a.0.a.0.a.0.23 = load volatile i32, i32* %a, align 4, !tbaa !3
69 %b.0.b.0.b.0.b.0.20 = load volatile i32, i32* %b, align 4, !tbaa !3
70 %add = add nsw i32 %b.0.b.0.b.0.b.0.20, %a.0.a.0.a.0.a.0.23
71 %c.0.c.0.c.0.c.0.17 = load volatile i32, i32* %c, align 4, !tbaa !3
72 %add7 = add nsw i32 %add, %c.0.c.0.c.0.c.0.17
75 if.end: ; preds = %entry, %for.cond.for.cond.cleanup_crit_edge
76 %a.0.a.0.a.0.a.0.24 = load volatile i32, i32* %a, align 4, !tbaa !3
77 %b.0.b.0.b.0.b.0.21 = load volatile i32, i32* %b, align 4, !tbaa !3
78 %mul.neg = mul i32 %b.0.b.0.b.0.b.0.21, -6
79 %sub = add i32 %mul.neg, %a.0.a.0.a.0.a.0.24
80 %c.0.c.0.c.0.c.0.18 = load volatile i32, i32* %c, align 4, !tbaa !3
81 %mul8 = mul nsw i32 %c.0.c.0.c.0.c.0.18, 3
82 %add9 = add nsw i32 %sub, %mul8
85 cleanup: ; preds = %if.end, %if.then
86 %retval.0 = phi i32 [ %add7, %if.then ], [ %add9, %if.end ]
87 %1 = bitcast i32* %c to i8*
88 %2 = bitcast i32* %b to i8*
89 %3 = bitcast i32* %a to i8*
90 call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %1)
91 call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %2)
92 call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %3)
96 declare dso_local i32 @feclearexcept(i32) local_unnamed_addr #3
98 declare dso_local i32 @fetestexcept(i32) local_unnamed_addr #3
100 ; Function Attrs: nofree nounwind
101 declare dso_local noundef i32 @printf(i8* nocapture noundef readonly, ...) local_unnamed_addr #4
103 attributes #0 = { mustprogress nofree norecurse nosync nounwind readnone willreturn "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv68" "target-features"="+v68,-long-calls" }
104 attributes #1 = { argmemonly mustprogress nofree nosync nounwind willreturn }
105 attributes #2 = { nounwind "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv68" "target-features"="+v68,-long-calls" }
106 attributes #3 = { "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv68" "target-features"="+v68,-long-calls" }
107 attributes #4 = { nofree nounwind "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv68" "target-features"="+v68,-long-calls" }
108 attributes #5 = { nounwind }
110 !llvm.module.flags = !{!0, !1}
112 !0 = !{i32 1, !"wchar_size", i32 4}
113 !1 = !{i32 7, !"frame-pointer", i32 2}
114 !3 = !{!4, !4, i64 0}
115 !4 = !{!"int", !5, i64 0}
116 !5 = !{!"omnipotent char", !6, i64 0}
117 !6 = !{!"Simple C/C++ TBAA"}
118 !7 = distinct !{!7, !8}
119 !8 = !{!"llvm.loop.mustprogress"}
123 name: syst_int32_to_float32
125 exposesReturnsTwice: false
127 regBankSelected: false
130 tracksRegLiveness: true
133 - { id: 0, class: intregs, preferred-register: '' }
134 - { id: 1, class: intregs, preferred-register: '' }
136 - { reg: '$r0', virtual-reg: '%0' }
138 isFrameAddressTaken: false
139 isReturnAddressTaken: false
148 maxCallFrameSize: 4294967295
149 cvBytesOfCalleeSavedRegisters: 0
150 hasOpaqueSPAdjustment: false
152 hasMustTailInVarArgFunc: false
160 debugValueSubstitutions: []
162 machineFunctionInfo: {}
167 %0:intregs = COPY $r0
168 %1:intregs = F2_conv_w2sf %0, implicit $usr
170 PS_jmpret $r31, implicit-def dead $pc, implicit $r0
176 exposesReturnsTwice: false
178 regBankSelected: false
181 tracksRegLiveness: true
184 - { id: 0, class: intregs, preferred-register: '' }
185 - { id: 1, class: intregs, preferred-register: '' }
186 - { id: 2, class: intregs, preferred-register: '' }
187 - { id: 3, class: intregs, preferred-register: '' }
188 - { id: 4, class: intregs, preferred-register: '' }
189 - { id: 5, class: intregs, preferred-register: '' }
190 - { id: 6, class: intregs, preferred-register: '' }
191 - { id: 7, class: intregs, preferred-register: '' }
192 - { id: 8, class: predregs, preferred-register: '' }
193 - { id: 9, class: intregs, preferred-register: '' }
194 - { id: 10, class: intregs, preferred-register: '' }
195 - { id: 11, class: intregs, preferred-register: '' }
196 - { id: 12, class: intregs, preferred-register: '' }
197 - { id: 13, class: intregs, preferred-register: '' }
198 - { id: 14, class: intregs, preferred-register: '' }
199 - { id: 15, class: intregs, preferred-register: '' }
200 - { id: 16, class: predregs, preferred-register: '' }
201 - { id: 17, class: intregs, preferred-register: '' }
202 - { id: 18, class: predregs, preferred-register: '' }
203 - { id: 19, class: intregs, preferred-register: '' }
204 - { id: 20, class: intregs, preferred-register: '' }
205 - { id: 21, class: intregs, preferred-register: '' }
206 - { id: 22, class: intregs, preferred-register: '' }
207 - { id: 23, class: intregs, preferred-register: '' }
208 - { id: 24, class: intregs, preferred-register: '' }
209 - { id: 25, class: intregs, preferred-register: '' }
210 - { id: 26, class: intregs, preferred-register: '' }
211 - { id: 27, class: intregs, preferred-register: '' }
214 isFrameAddressTaken: false
215 isReturnAddressTaken: false
224 maxCallFrameSize: 4294967295
225 cvBytesOfCalleeSavedRegisters: 0
226 hasOpaqueSPAdjustment: false
228 hasMustTailInVarArgFunc: false
235 - { id: 0, name: a, type: default, offset: 0, size: 4, alignment: 4,
236 stack-id: default, callee-saved-register: '', callee-saved-restored: true,
237 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
238 - { id: 1, name: b, type: default, offset: 0, size: 4, alignment: 4,
239 stack-id: default, callee-saved-register: '', callee-saved-restored: true,
240 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
241 - { id: 2, name: c, type: default, offset: 0, size: 4, alignment: 4,
242 stack-id: default, callee-saved-register: '', callee-saved-restored: true,
243 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
245 debugValueSubstitutions: []
247 machineFunctionInfo: {}
250 successors: %bb.6(0x50000000), %bb.4(0x30000000)
252 S4_storeiri_io %stack.0.a, 0, -16777235 :: (volatile store (s32) into %ir.a, !tbaa !3)
253 S4_storeiri_io %stack.1.b, 0, 34 :: (volatile store (s32) into %ir.b, !tbaa !3)
254 S4_storeiri_io %stack.2.c, 0, 34 :: (volatile store (s32) into %ir.c, !tbaa !3)
255 %7:intregs = L2_loadri_io %stack.1.b, 0 :: (volatile dereferenceable load (s32) from %ir.b, !tbaa !3)
256 %8:predregs = C2_cmpgti %7, 0
257 %6:intregs = A2_tfrsi 0
258 J2_jumpf %8, %bb.4, implicit-def $pc
261 successors: %bb.2(0x80000000)
263 %9:intregs = A2_tfrsi 31
264 %13:intregs = A2_tfrsi @.str
265 J2_jump %bb.2, implicit-def $pc
267 bb.1.for.cond.for.cond.cleanup_crit_edge:
268 successors: %bb.4(0x40000000)
270 J2_jump %bb.4, implicit-def dead $pc
273 successors: %bb.2(0x7c000000), %bb.1(0x04000000)
275 %0:intregs = PHI %6, %bb.6, %2, %bb.2
276 L4_iadd_memopw_io %stack.2.c, 0, 1 :: (volatile store (s32) into %ir.c, !tbaa !3), (volatile dereferenceable load (s32) from %ir.c, !tbaa !3)
277 ADJCALLSTACKDOWN 0, 0, implicit-def $r29, implicit-def dead $r30, implicit $r31, implicit $r30, implicit $r29
279 J2_call @feclearexcept, hexagoncsr, implicit-def dead $pc, implicit-def dead $r31, implicit $r29, implicit $r0, implicit-def $r29, implicit-def $r0
280 ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit-def dead $r31, implicit $r29
281 %1:intregs = L2_loadri_io %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a, !tbaa !3)
282 ADJCALLSTACKDOWN 0, 0, implicit-def $r29, implicit-def dead $r30, implicit $r31, implicit $r30, implicit $r29
283 %17:intregs = F2_conv_w2sf %1, implicit $usr
285 J2_call @fetestexcept, hexagoncsr, implicit-def dead $pc, implicit-def dead $r31, implicit $r29, implicit $r0, implicit-def $r29, implicit-def $r0
286 ADJCALLSTACKUP 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit-def dead $r31, implicit $r29
287 %11:intregs = COPY $r0
288 %12:intregs = COPY $r29
289 S2_storeri_io %12, 0, %11 :: (store (s32) into stack)
290 ADJCALLSTACKDOWN 4, 0, implicit-def $r29, implicit-def dead $r30, implicit $r31, implicit $r30, implicit $r29
292 J2_call @printf, hexagoncsr, implicit-def dead $pc, implicit-def dead $r31, implicit $r29, implicit $r0, implicit-def $r29, implicit-def $r0
293 ADJCALLSTACKUP 4, 0, implicit-def dead $r29, implicit-def dead $r30, implicit-def dead $r31, implicit $r29
294 %2:intregs = nuw nsw A2_addi %0, 1
295 %15:intregs = L2_loadri_io %stack.1.b, 0 :: (volatile dereferenceable load (s32) from %ir.b, !tbaa !3)
296 %16:predregs = C2_cmpgt %15, %2
297 J2_jumpt %16, %bb.2, implicit-def dead $pc
298 J2_jump %bb.1, implicit-def dead $pc
301 successors: %bb.5(0x80000000)
303 %18:predregs = C2_cmpgtui %17, 100
304 %24:intregs = L2_loadri_io %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a, !tbaa !3)
305 %25:intregs = L2_loadri_io %stack.1.b, 0 :: (volatile dereferenceable load (s32) from %ir.b, !tbaa !3)
306 %26:intregs = L2_loadri_io %stack.2.c, 0 :: (volatile dereferenceable load (s32) from %ir.c, !tbaa !3)
307 %3:intregs = nsw M2_acci %26, %25, %24
308 J2_jumpf %18, %bb.5, implicit-def dead $pc
309 J2_jump %bb.5, implicit-def dead $pc
312 successors: %bb.5(0x80000000)
314 %19:intregs = L2_loadri_io %stack.0.a, 0 :: (volatile dereferenceable load (s32) from %ir.a, !tbaa !3)
315 %20:intregs = L2_loadri_io %stack.1.b, 0 :: (volatile dereferenceable load (s32) from %ir.b, !tbaa !3)
316 %27:intregs = M2_macsin %19, %20, 6
317 %23:intregs = L2_loadri_io %stack.2.c, 0 :: (volatile dereferenceable load (s32) from %ir.c, !tbaa !3)
318 %4:intregs = nsw M2_macsip %27, %23, 3
321 %5:intregs = PHI %4, %bb.4, %3, %bb.3
323 PS_jmpret $r31, implicit-def dead $pc, implicit $r0