| blob | 47d18b9b5c533e9085162310b3e68e68ad0842fd |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 -relocation-model=pic | FileCheck %s \
3 ; RUN: -check-prefix=MIPS
4 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -relocation-model=pic | FileCheck %s \
5 ; RUN: -check-prefix=MIPS32
6 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \
7 ; RUN: -check-prefix=32R2
8 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \
9 ; RUN: -check-prefix=32R2
10 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \
11 ; RUN: -check-prefix=32R2
12 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \
13 ; RUN: -check-prefix=32R6
14 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 -relocation-model=pic | FileCheck %s \
15 ; RUN: -check-prefix=MIPS3
16 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 -relocation-model=pic | FileCheck %s \
17 ; RUN: -check-prefix=MIPS64
18 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 -relocation-model=pic | FileCheck %s \
19 ; RUN: -check-prefix=MIPS64
20 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \
21 ; RUN: -check-prefix=MIPS64R2
22 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \
23 ; RUN: -check-prefix=MIPS64R2
24 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \
25 ; RUN: -check-prefix=MIPS64R2
26 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
27 ; RUN: -check-prefix=MIPS64R6
28 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
29 ; RUN: -check-prefix=MMR3
30 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
31 ; RUN: -check-prefix=MMR6
33 define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) {
34 ; MIPS-LABEL: ashr_i1:
35 ; MIPS: # %bb.0: # %entry
36 ; MIPS-NEXT: jr $ra
37 ; MIPS-NEXT: move $2, $4
38 ;
39 ; MIPS32-LABEL: ashr_i1:
40 ; MIPS32: # %bb.0: # %entry
41 ; MIPS32-NEXT: jr $ra
42 ; MIPS32-NEXT: move $2, $4
43 ;
44 ; 32R2-LABEL: ashr_i1:
45 ; 32R2: # %bb.0: # %entry
46 ; 32R2-NEXT: jr $ra
47 ; 32R2-NEXT: move $2, $4
48 ;
49 ; 32R6-LABEL: ashr_i1:
50 ; 32R6: # %bb.0: # %entry
51 ; 32R6-NEXT: jr $ra
52 ; 32R6-NEXT: move $2, $4
53 ;
54 ; MIPS3-LABEL: ashr_i1:
55 ; MIPS3: # %bb.0: # %entry
56 ; MIPS3-NEXT: jr $ra
57 ; MIPS3-NEXT: move $2, $4
58 ;
59 ; MIPS64-LABEL: ashr_i1:
60 ; MIPS64: # %bb.0: # %entry
61 ; MIPS64-NEXT: jr $ra
62 ; MIPS64-NEXT: move $2, $4
63 ;
64 ; MIPS64R2-LABEL: ashr_i1:
65 ; MIPS64R2: # %bb.0: # %entry
66 ; MIPS64R2-NEXT: jr $ra
67 ; MIPS64R2-NEXT: move $2, $4
68 ;
69 ; MIPS64R6-LABEL: ashr_i1:
70 ; MIPS64R6: # %bb.0: # %entry
71 ; MIPS64R6-NEXT: jr $ra
72 ; MIPS64R6-NEXT: move $2, $4
73 ;
74 ; MMR3-LABEL: ashr_i1:
75 ; MMR3: # %bb.0: # %entry
76 ; MMR3-NEXT: move $2, $4
77 ; MMR3-NEXT: jrc $ra
78 ;
79 ; MMR6-LABEL: ashr_i1:
80 ; MMR6: # %bb.0: # %entry
81 ; MMR6-NEXT: move $2, $4
82 ; MMR6-NEXT: jrc $ra
83 entry:
84 %r = ashr i1 %a, %b
85 ret i1 %r
86 }
88 ; FIXME: The andi instruction is redundant.
89 define signext i8 @ashr_i8(i8 signext %a, i8 signext %b) {
90 ; MIPS-LABEL: ashr_i8:
91 ; MIPS: # %bb.0: # %entry
92 ; MIPS-NEXT: andi $1, $5, 255
93 ; MIPS-NEXT: jr $ra
94 ; MIPS-NEXT: srav $2, $4, $1
95 ;
96 ; MIPS32-LABEL: ashr_i8:
97 ; MIPS32: # %bb.0: # %entry
98 ; MIPS32-NEXT: andi $1, $5, 255
99 ; MIPS32-NEXT: jr $ra
100 ; MIPS32-NEXT: srav $2, $4, $1
101 ;
102 ; 32R2-LABEL: ashr_i8:
103 ; 32R2: # %bb.0: # %entry
104 ; 32R2-NEXT: andi $1, $5, 255
105 ; 32R2-NEXT: jr $ra
106 ; 32R2-NEXT: srav $2, $4, $1
107 ;
108 ; 32R6-LABEL: ashr_i8:
109 ; 32R6: # %bb.0: # %entry
110 ; 32R6-NEXT: andi $1, $5, 255
111 ; 32R6-NEXT: jr $ra
112 ; 32R6-NEXT: srav $2, $4, $1
113 ;
114 ; MIPS3-LABEL: ashr_i8:
115 ; MIPS3: # %bb.0: # %entry
116 ; MIPS3-NEXT: andi $1, $5, 255
117 ; MIPS3-NEXT: jr $ra
118 ; MIPS3-NEXT: srav $2, $4, $1
119 ;
120 ; MIPS64-LABEL: ashr_i8:
121 ; MIPS64: # %bb.0: # %entry
122 ; MIPS64-NEXT: andi $1, $5, 255
123 ; MIPS64-NEXT: jr $ra
124 ; MIPS64-NEXT: srav $2, $4, $1
125 ;
126 ; MIPS64R2-LABEL: ashr_i8:
127 ; MIPS64R2: # %bb.0: # %entry
128 ; MIPS64R2-NEXT: andi $1, $5, 255
129 ; MIPS64R2-NEXT: jr $ra
130 ; MIPS64R2-NEXT: srav $2, $4, $1
131 ;
132 ; MIPS64R6-LABEL: ashr_i8:
133 ; MIPS64R6: # %bb.0: # %entry
134 ; MIPS64R6-NEXT: andi $1, $5, 255
135 ; MIPS64R6-NEXT: jr $ra
136 ; MIPS64R6-NEXT: srav $2, $4, $1
137 ;
138 ; MMR3-LABEL: ashr_i8:
139 ; MMR3: # %bb.0: # %entry
140 ; MMR3-NEXT: andi16 $2, $5, 255
141 ; MMR3-NEXT: jr $ra
142 ; MMR3-NEXT: srav $2, $4, $2
143 ;
144 ; MMR6-LABEL: ashr_i8:
145 ; MMR6: # %bb.0: # %entry
146 ; MMR6-NEXT: andi16 $2, $5, 255
147 ; MMR6-NEXT: srav $2, $4, $2
148 ; MMR6-NEXT: jrc $ra
149 entry:
150 %r = ashr i8 %a, %b
151 ret i8 %r
152 }
154 ; FIXME: The andi instruction is redundant.
155 define signext i16 @ashr_i16(i16 signext %a, i16 signext %b) {
156 ; MIPS-LABEL: ashr_i16:
157 ; MIPS: # %bb.0: # %entry
158 ; MIPS-NEXT: andi $1, $5, 65535
159 ; MIPS-NEXT: jr $ra
160 ; MIPS-NEXT: srav $2, $4, $1
161 ;
162 ; MIPS32-LABEL: ashr_i16:
163 ; MIPS32: # %bb.0: # %entry
164 ; MIPS32-NEXT: andi $1, $5, 65535
165 ; MIPS32-NEXT: jr $ra
166 ; MIPS32-NEXT: srav $2, $4, $1
167 ;
168 ; 32R2-LABEL: ashr_i16:
169 ; 32R2: # %bb.0: # %entry
170 ; 32R2-NEXT: andi $1, $5, 65535
171 ; 32R2-NEXT: jr $ra
172 ; 32R2-NEXT: srav $2, $4, $1
173 ;
174 ; 32R6-LABEL: ashr_i16:
175 ; 32R6: # %bb.0: # %entry
176 ; 32R6-NEXT: andi $1, $5, 65535
177 ; 32R6-NEXT: jr $ra
178 ; 32R6-NEXT: srav $2, $4, $1
179 ;
180 ; MIPS3-LABEL: ashr_i16:
181 ; MIPS3: # %bb.0: # %entry
182 ; MIPS3-NEXT: andi $1, $5, 65535
183 ; MIPS3-NEXT: jr $ra
184 ; MIPS3-NEXT: srav $2, $4, $1
185 ;
186 ; MIPS64-LABEL: ashr_i16:
187 ; MIPS64: # %bb.0: # %entry
188 ; MIPS64-NEXT: andi $1, $5, 65535
189 ; MIPS64-NEXT: jr $ra
190 ; MIPS64-NEXT: srav $2, $4, $1
191 ;
192 ; MIPS64R2-LABEL: ashr_i16:
193 ; MIPS64R2: # %bb.0: # %entry
194 ; MIPS64R2-NEXT: andi $1, $5, 65535
195 ; MIPS64R2-NEXT: jr $ra
196 ; MIPS64R2-NEXT: srav $2, $4, $1
197 ;
198 ; MIPS64R6-LABEL: ashr_i16:
199 ; MIPS64R6: # %bb.0: # %entry
200 ; MIPS64R6-NEXT: andi $1, $5, 65535
201 ; MIPS64R6-NEXT: jr $ra
202 ; MIPS64R6-NEXT: srav $2, $4, $1
203 ;
204 ; MMR3-LABEL: ashr_i16:
205 ; MMR3: # %bb.0: # %entry
206 ; MMR3-NEXT: andi16 $2, $5, 65535
207 ; MMR3-NEXT: jr $ra
208 ; MMR3-NEXT: srav $2, $4, $2
209 ;
210 ; MMR6-LABEL: ashr_i16:
211 ; MMR6: # %bb.0: # %entry
212 ; MMR6-NEXT: andi16 $2, $5, 65535
213 ; MMR6-NEXT: srav $2, $4, $2
214 ; MMR6-NEXT: jrc $ra
215 entry:
216 %r = ashr i16 %a, %b
217 ret i16 %r
218 }
220 define signext i32 @ashr_i32(i32 signext %a, i32 signext %b) {
221 ; MIPS-LABEL: ashr_i32:
222 ; MIPS: # %bb.0: # %entry
223 ; MIPS-NEXT: jr $ra
224 ; MIPS-NEXT: srav $2, $4, $5
225 ;
226 ; MIPS32-LABEL: ashr_i32:
227 ; MIPS32: # %bb.0: # %entry
228 ; MIPS32-NEXT: jr $ra
229 ; MIPS32-NEXT: srav $2, $4, $5
230 ;
231 ; 32R2-LABEL: ashr_i32:
232 ; 32R2: # %bb.0: # %entry
233 ; 32R2-NEXT: jr $ra
234 ; 32R2-NEXT: srav $2, $4, $5
235 ;
236 ; 32R6-LABEL: ashr_i32:
237 ; 32R6: # %bb.0: # %entry
238 ; 32R6-NEXT: jr $ra
239 ; 32R6-NEXT: srav $2, $4, $5
240 ;
241 ; MIPS3-LABEL: ashr_i32:
242 ; MIPS3: # %bb.0: # %entry
243 ; MIPS3-NEXT: jr $ra
244 ; MIPS3-NEXT: srav $2, $4, $5
245 ;
246 ; MIPS64-LABEL: ashr_i32:
247 ; MIPS64: # %bb.0: # %entry
248 ; MIPS64-NEXT: jr $ra
249 ; MIPS64-NEXT: srav $2, $4, $5
250 ;
251 ; MIPS64R2-LABEL: ashr_i32:
252 ; MIPS64R2: # %bb.0: # %entry
253 ; MIPS64R2-NEXT: jr $ra
254 ; MIPS64R2-NEXT: srav $2, $4, $5
255 ;
256 ; MIPS64R6-LABEL: ashr_i32:
257 ; MIPS64R6: # %bb.0: # %entry
258 ; MIPS64R6-NEXT: jr $ra
259 ; MIPS64R6-NEXT: srav $2, $4, $5
260 ;
261 ; MMR3-LABEL: ashr_i32:
262 ; MMR3: # %bb.0: # %entry
263 ; MMR3-NEXT: jr $ra
264 ; MMR3-NEXT: srav $2, $4, $5
265 ;
266 ; MMR6-LABEL: ashr_i32:
267 ; MMR6: # %bb.0: # %entry
268 ; MMR6-NEXT: srav $2, $4, $5
269 ; MMR6-NEXT: jrc $ra
270 entry:
271 %r = ashr i32 %a, %b
272 ret i32 %r
273 }
275 define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) {
276 ; MIPS-LABEL: ashr_i64:
277 ; MIPS: # %bb.0: # %entry
278 ; MIPS-NEXT: andi $1, $7, 32
279 ; MIPS-NEXT: bnez $1, $BB4_2
280 ; MIPS-NEXT: srav $3, $4, $7
281 ; MIPS-NEXT: # %bb.1: # %entry
282 ; MIPS-NEXT: srlv $1, $5, $7
283 ; MIPS-NEXT: not $2, $7
284 ; MIPS-NEXT: sll $4, $4, 1
285 ; MIPS-NEXT: sllv $2, $4, $2
286 ; MIPS-NEXT: or $1, $2, $1
287 ; MIPS-NEXT: move $2, $3
288 ; MIPS-NEXT: jr $ra
289 ; MIPS-NEXT: move $3, $1
290 ; MIPS-NEXT: $BB4_2:
291 ; MIPS-NEXT: jr $ra
292 ; MIPS-NEXT: sra $2, $4, 31
293 ;
294 ; MIPS32-LABEL: ashr_i64:
295 ; MIPS32: # %bb.0: # %entry
296 ; MIPS32-NEXT: srlv $1, $5, $7
297 ; MIPS32-NEXT: not $2, $7
298 ; MIPS32-NEXT: sll $3, $4, 1
299 ; MIPS32-NEXT: sllv $2, $3, $2
300 ; MIPS32-NEXT: or $3, $2, $1
301 ; MIPS32-NEXT: srav $2, $4, $7
302 ; MIPS32-NEXT: andi $1, $7, 32
303 ; MIPS32-NEXT: movn $3, $2, $1
304 ; MIPS32-NEXT: sra $4, $4, 31
305 ; MIPS32-NEXT: jr $ra
306 ; MIPS32-NEXT: movn $2, $4, $1
307 ;
308 ; 32R2-LABEL: ashr_i64:
309 ; 32R2: # %bb.0: # %entry
310 ; 32R2-NEXT: srlv $1, $5, $7
311 ; 32R2-NEXT: not $2, $7
312 ; 32R2-NEXT: sll $3, $4, 1
313 ; 32R2-NEXT: sllv $2, $3, $2
314 ; 32R2-NEXT: or $3, $2, $1
315 ; 32R2-NEXT: srav $2, $4, $7
316 ; 32R2-NEXT: andi $1, $7, 32
317 ; 32R2-NEXT: movn $3, $2, $1
318 ; 32R2-NEXT: sra $4, $4, 31
319 ; 32R2-NEXT: jr $ra
320 ; 32R2-NEXT: movn $2, $4, $1
321 ;
322 ; 32R6-LABEL: ashr_i64:
323 ; 32R6: # %bb.0: # %entry
324 ; 32R6-NEXT: srav $1, $4, $7
325 ; 32R6-NEXT: andi $3, $7, 32
326 ; 32R6-NEXT: seleqz $2, $1, $3
327 ; 32R6-NEXT: sra $6, $4, 31
328 ; 32R6-NEXT: selnez $6, $6, $3
329 ; 32R6-NEXT: or $2, $6, $2
330 ; 32R6-NEXT: srlv $5, $5, $7
331 ; 32R6-NEXT: not $6, $7
332 ; 32R6-NEXT: sll $4, $4, 1
333 ; 32R6-NEXT: sllv $4, $4, $6
334 ; 32R6-NEXT: or $4, $4, $5
335 ; 32R6-NEXT: seleqz $4, $4, $3
336 ; 32R6-NEXT: selnez $1, $1, $3
337 ; 32R6-NEXT: jr $ra
338 ; 32R6-NEXT: or $3, $1, $4
339 ;
340 ; MIPS3-LABEL: ashr_i64:
341 ; MIPS3: # %bb.0: # %entry
342 ; MIPS3-NEXT: jr $ra
343 ; MIPS3-NEXT: dsrav $2, $4, $5
344 ;
345 ; MIPS64-LABEL: ashr_i64:
346 ; MIPS64: # %bb.0: # %entry
347 ; MIPS64-NEXT: jr $ra
348 ; MIPS64-NEXT: dsrav $2, $4, $5
349 ;
350 ; MIPS64R2-LABEL: ashr_i64:
351 ; MIPS64R2: # %bb.0: # %entry
352 ; MIPS64R2-NEXT: jr $ra
353 ; MIPS64R2-NEXT: dsrav $2, $4, $5
354 ;
355 ; MIPS64R6-LABEL: ashr_i64:
356 ; MIPS64R6: # %bb.0: # %entry
357 ; MIPS64R6-NEXT: jr $ra
358 ; MIPS64R6-NEXT: dsrav $2, $4, $5
359 ;
360 ; MMR3-LABEL: ashr_i64:
361 ; MMR3: # %bb.0: # %entry
362 ; MMR3-NEXT: srlv $2, $5, $7
363 ; MMR3-NEXT: not16 $3, $7
364 ; MMR3-NEXT: sll16 $5, $4, 1
365 ; MMR3-NEXT: sllv $3, $5, $3
366 ; MMR3-NEXT: or16 $3, $2
367 ; MMR3-NEXT: srav $2, $4, $7
368 ; MMR3-NEXT: andi16 $5, $7, 32
369 ; MMR3-NEXT: movn $3, $2, $5
370 ; MMR3-NEXT: sra $1, $4, 31
371 ; MMR3-NEXT: jr $ra
372 ; MMR3-NEXT: movn $2, $1, $5
373 ;
374 ; MMR6-LABEL: ashr_i64:
375 ; MMR6: # %bb.0: # %entry
376 ; MMR6-NEXT: srav $1, $4, $7
377 ; MMR6-NEXT: andi16 $3, $7, 32
378 ; MMR6-NEXT: seleqz $2, $1, $3
379 ; MMR6-NEXT: sra $6, $4, 31
380 ; MMR6-NEXT: selnez $6, $6, $3
381 ; MMR6-NEXT: or $2, $6, $2
382 ; MMR6-NEXT: srlv $5, $5, $7
383 ; MMR6-NEXT: not16 $6, $7
384 ; MMR6-NEXT: sll16 $4, $4, 1
385 ; MMR6-NEXT: sllv $4, $4, $6
386 ; MMR6-NEXT: or $4, $4, $5
387 ; MMR6-NEXT: seleqz $4, $4, $3
388 ; MMR6-NEXT: selnez $1, $1, $3
389 ; MMR6-NEXT: or $3, $1, $4
390 ; MMR6-NEXT: jrc $ra
391 entry:
392 %r = ashr i64 %a, %b
393 ret i64 %r
394 }
396 define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
397 ; MIPS-LABEL: ashr_i128:
398 ; MIPS: # %bb.0: # %entry
399 ; MIPS-NEXT: addiu $sp, $sp, -32
400 ; MIPS-NEXT: .cfi_def_cfa_offset 32
401 ; MIPS-NEXT: swl $7, 28($sp)
402 ; MIPS-NEXT: swl $6, 24($sp)
403 ; MIPS-NEXT: sra $1, $4, 31
404 ; MIPS-NEXT: swl $5, 20($sp)
405 ; MIPS-NEXT: swl $4, 16($sp)
406 ; MIPS-NEXT: swl $1, 12($sp)
407 ; MIPS-NEXT: swl $1, 8($sp)
408 ; MIPS-NEXT: swl $1, 4($sp)
409 ; MIPS-NEXT: swl $1, 0($sp)
410 ; MIPS-NEXT: addiu $2, $sp, 0
411 ; MIPS-NEXT: swr $7, 31($sp)
412 ; MIPS-NEXT: swr $6, 27($sp)
413 ; MIPS-NEXT: swr $5, 23($sp)
414 ; MIPS-NEXT: swr $4, 19($sp)
415 ; MIPS-NEXT: swr $1, 15($sp)
416 ; MIPS-NEXT: swr $1, 11($sp)
417 ; MIPS-NEXT: swr $1, 7($sp)
418 ; MIPS-NEXT: swr $1, 3($sp)
419 ; MIPS-NEXT: addiu $1, $2, 16
420 ; MIPS-NEXT: lw $2, 60($sp)
421 ; MIPS-NEXT: srl $3, $2, 3
422 ; MIPS-NEXT: andi $3, $3, 15
423 ; MIPS-NEXT: subu $1, $1, $3
424 ; MIPS-NEXT: lwl $3, 4($1)
425 ; MIPS-NEXT: lwr $3, 7($1)
426 ; MIPS-NEXT: sll $4, $3, 1
427 ; MIPS-NEXT: lwl $5, 8($1)
428 ; MIPS-NEXT: lwr $5, 11($1)
429 ; MIPS-NEXT: andi $2, $2, 7
430 ; MIPS-NEXT: not $6, $2
431 ; MIPS-NEXT: andi $6, $6, 31
432 ; MIPS-NEXT: srlv $7, $5, $2
433 ; MIPS-NEXT: sllv $4, $4, $6
434 ; MIPS-NEXT: srlv $3, $3, $2
435 ; MIPS-NEXT: lwl $6, 0($1)
436 ; MIPS-NEXT: lwr $6, 3($1)
437 ; MIPS-NEXT: sll $8, $6, 1
438 ; MIPS-NEXT: xori $9, $2, 31
439 ; MIPS-NEXT: sllv $8, $8, $9
440 ; MIPS-NEXT: or $3, $3, $8
441 ; MIPS-NEXT: or $4, $7, $4
442 ; MIPS-NEXT: lwl $7, 12($1)
443 ; MIPS-NEXT: lwr $7, 15($1)
444 ; MIPS-NEXT: srlv $1, $7, $2
445 ; MIPS-NEXT: sll $5, $5, 1
446 ; MIPS-NEXT: sllv $5, $5, $9
447 ; MIPS-NEXT: or $5, $1, $5
448 ; MIPS-NEXT: srav $2, $6, $2
449 ; MIPS-NEXT: jr $ra
450 ; MIPS-NEXT: addiu $sp, $sp, 32
451 ;
452 ; MIPS32-LABEL: ashr_i128:
453 ; MIPS32: # %bb.0: # %entry
454 ; MIPS32-NEXT: addiu $sp, $sp, -32
455 ; MIPS32-NEXT: .cfi_def_cfa_offset 32
456 ; MIPS32-NEXT: swl $7, 28($sp)
457 ; MIPS32-NEXT: swl $6, 24($sp)
458 ; MIPS32-NEXT: sra $1, $4, 31
459 ; MIPS32-NEXT: swl $5, 20($sp)
460 ; MIPS32-NEXT: swl $4, 16($sp)
461 ; MIPS32-NEXT: swl $1, 12($sp)
462 ; MIPS32-NEXT: swl $1, 8($sp)
463 ; MIPS32-NEXT: swl $1, 4($sp)
464 ; MIPS32-NEXT: swl $1, 0($sp)
465 ; MIPS32-NEXT: addiu $2, $sp, 0
466 ; MIPS32-NEXT: swr $7, 31($sp)
467 ; MIPS32-NEXT: swr $6, 27($sp)
468 ; MIPS32-NEXT: swr $5, 23($sp)
469 ; MIPS32-NEXT: swr $4, 19($sp)
470 ; MIPS32-NEXT: swr $1, 15($sp)
471 ; MIPS32-NEXT: swr $1, 11($sp)
472 ; MIPS32-NEXT: swr $1, 7($sp)
473 ; MIPS32-NEXT: swr $1, 3($sp)
474 ; MIPS32-NEXT: addiu $1, $2, 16
475 ; MIPS32-NEXT: lw $2, 60($sp)
476 ; MIPS32-NEXT: srl $3, $2, 3
477 ; MIPS32-NEXT: andi $3, $3, 15
478 ; MIPS32-NEXT: subu $1, $1, $3
479 ; MIPS32-NEXT: lwl $3, 4($1)
480 ; MIPS32-NEXT: lwr $3, 7($1)
481 ; MIPS32-NEXT: sll $4, $3, 1
482 ; MIPS32-NEXT: lwl $5, 8($1)
483 ; MIPS32-NEXT: lwr $5, 11($1)
484 ; MIPS32-NEXT: andi $2, $2, 7
485 ; MIPS32-NEXT: not $6, $2
486 ; MIPS32-NEXT: andi $6, $6, 31
487 ; MIPS32-NEXT: srlv $7, $5, $2
488 ; MIPS32-NEXT: sllv $4, $4, $6
489 ; MIPS32-NEXT: srlv $3, $3, $2
490 ; MIPS32-NEXT: lwl $6, 0($1)
491 ; MIPS32-NEXT: lwr $6, 3($1)
492 ; MIPS32-NEXT: sll $8, $6, 1
493 ; MIPS32-NEXT: xori $9, $2, 31
494 ; MIPS32-NEXT: sllv $8, $8, $9
495 ; MIPS32-NEXT: or $3, $3, $8
496 ; MIPS32-NEXT: or $4, $7, $4
497 ; MIPS32-NEXT: lwl $7, 12($1)
498 ; MIPS32-NEXT: lwr $7, 15($1)
499 ; MIPS32-NEXT: srlv $1, $7, $2
500 ; MIPS32-NEXT: sll $5, $5, 1
501 ; MIPS32-NEXT: sllv $5, $5, $9
502 ; MIPS32-NEXT: or $5, $1, $5
503 ; MIPS32-NEXT: srav $2, $6, $2
504 ; MIPS32-NEXT: jr $ra
505 ; MIPS32-NEXT: addiu $sp, $sp, 32
506 ;
507 ; 32R2-LABEL: ashr_i128:
508 ; 32R2: # %bb.0: # %entry
509 ; 32R2-NEXT: addiu $sp, $sp, -32
510 ; 32R2-NEXT: .cfi_def_cfa_offset 32
511 ; 32R2-NEXT: swl $7, 28($sp)
512 ; 32R2-NEXT: swl $6, 24($sp)
513 ; 32R2-NEXT: swl $5, 20($sp)
514 ; 32R2-NEXT: sra $1, $4, 31
515 ; 32R2-NEXT: swl $4, 16($sp)
516 ; 32R2-NEXT: swl $1, 12($sp)
517 ; 32R2-NEXT: swl $1, 8($sp)
518 ; 32R2-NEXT: swl $1, 4($sp)
519 ; 32R2-NEXT: swl $1, 0($sp)
520 ; 32R2-NEXT: swr $7, 31($sp)
521 ; 32R2-NEXT: swr $6, 27($sp)
522 ; 32R2-NEXT: swr $5, 23($sp)
523 ; 32R2-NEXT: swr $4, 19($sp)
524 ; 32R2-NEXT: swr $1, 15($sp)
525 ; 32R2-NEXT: swr $1, 11($sp)
526 ; 32R2-NEXT: swr $1, 7($sp)
527 ; 32R2-NEXT: swr $1, 3($sp)
528 ; 32R2-NEXT: addiu $1, $sp, 0
529 ; 32R2-NEXT: addiu $1, $1, 16
530 ; 32R2-NEXT: lw $2, 60($sp)
531 ; 32R2-NEXT: ext $3, $2, 3, 4
532 ; 32R2-NEXT: subu $1, $1, $3
533 ; 32R2-NEXT: lwl $3, 4($1)
534 ; 32R2-NEXT: lwr $3, 7($1)
535 ; 32R2-NEXT: sll $4, $3, 1
536 ; 32R2-NEXT: lwl $5, 8($1)
537 ; 32R2-NEXT: lwr $5, 11($1)
538 ; 32R2-NEXT: andi $2, $2, 7
539 ; 32R2-NEXT: not $6, $2
540 ; 32R2-NEXT: andi $6, $6, 31
541 ; 32R2-NEXT: srlv $7, $5, $2
542 ; 32R2-NEXT: sllv $4, $4, $6
543 ; 32R2-NEXT: srlv $3, $3, $2
544 ; 32R2-NEXT: lwl $6, 0($1)
545 ; 32R2-NEXT: lwr $6, 3($1)
546 ; 32R2-NEXT: sll $8, $6, 1
547 ; 32R2-NEXT: xori $9, $2, 31
548 ; 32R2-NEXT: sllv $8, $8, $9
549 ; 32R2-NEXT: or $3, $3, $8
550 ; 32R2-NEXT: or $4, $7, $4
551 ; 32R2-NEXT: lwl $7, 12($1)
552 ; 32R2-NEXT: lwr $7, 15($1)
553 ; 32R2-NEXT: srlv $1, $7, $2
554 ; 32R2-NEXT: sll $5, $5, 1
555 ; 32R2-NEXT: sllv $5, $5, $9
556 ; 32R2-NEXT: or $5, $1, $5
557 ; 32R2-NEXT: srav $2, $6, $2
558 ; 32R2-NEXT: jr $ra
559 ; 32R2-NEXT: addiu $sp, $sp, 32
560 ;
561 ; 32R6-LABEL: ashr_i128:
562 ; 32R6: # %bb.0: # %entry
563 ; 32R6-NEXT: addiu $sp, $sp, -32
564 ; 32R6-NEXT: .cfi_def_cfa_offset 32
565 ; 32R6-NEXT: sra $1, $4, 31
566 ; 32R6-NEXT: sw $7, 28($sp)
567 ; 32R6-NEXT: sw $6, 24($sp)
568 ; 32R6-NEXT: sw $5, 20($sp)
569 ; 32R6-NEXT: sw $4, 16($sp)
570 ; 32R6-NEXT: sw $1, 12($sp)
571 ; 32R6-NEXT: sw $1, 8($sp)
572 ; 32R6-NEXT: sw $1, 4($sp)
573 ; 32R6-NEXT: sw $1, 0($sp)
574 ; 32R6-NEXT: addiu $1, $sp, 0
575 ; 32R6-NEXT: addiu $1, $1, 16
576 ; 32R6-NEXT: lw $2, 60($sp)
577 ; 32R6-NEXT: ext $3, $2, 3, 4
578 ; 32R6-NEXT: subu $1, $1, $3
579 ; 32R6-NEXT: lw $3, 4($1)
580 ; 32R6-NEXT: sll $4, $3, 1
581 ; 32R6-NEXT: lw $5, 8($1)
582 ; 32R6-NEXT: andi $2, $2, 7
583 ; 32R6-NEXT: not $6, $2
584 ; 32R6-NEXT: andi $6, $6, 31
585 ; 32R6-NEXT: srlv $7, $5, $2
586 ; 32R6-NEXT: sllv $4, $4, $6
587 ; 32R6-NEXT: srlv $3, $3, $2
588 ; 32R6-NEXT: lw $6, 0($1)
589 ; 32R6-NEXT: sll $8, $6, 1
590 ; 32R6-NEXT: xori $9, $2, 31
591 ; 32R6-NEXT: sllv $8, $8, $9
592 ; 32R6-NEXT: or $3, $3, $8
593 ; 32R6-NEXT: or $4, $7, $4
594 ; 32R6-NEXT: lw $1, 12($1)
595 ; 32R6-NEXT: srlv $1, $1, $2
596 ; 32R6-NEXT: sll $5, $5, 1
597 ; 32R6-NEXT: sllv $5, $5, $9
598 ; 32R6-NEXT: or $5, $1, $5
599 ; 32R6-NEXT: srav $2, $6, $2
600 ; 32R6-NEXT: jr $ra
601 ; 32R6-NEXT: addiu $sp, $sp, 32
602 ;
603 ; MIPS3-LABEL: ashr_i128:
604 ; MIPS3: # %bb.0: # %entry
605 ; MIPS3-NEXT: sll $2, $7, 0
606 ; MIPS3-NEXT: andi $1, $2, 64
607 ; MIPS3-NEXT: bnez $1, .LBB5_2
608 ; MIPS3-NEXT: dsrav $3, $4, $7
609 ; MIPS3-NEXT: # %bb.1: # %entry
610 ; MIPS3-NEXT: dsrlv $1, $5, $7
611 ; MIPS3-NEXT: dsll $4, $4, 1
612 ; MIPS3-NEXT: not $2, $2
613 ; MIPS3-NEXT: dsllv $2, $4, $2
614 ; MIPS3-NEXT: or $1, $2, $1
615 ; MIPS3-NEXT: move $2, $3
616 ; MIPS3-NEXT: jr $ra
617 ; MIPS3-NEXT: move $3, $1
618 ; MIPS3-NEXT: .LBB5_2:
619 ; MIPS3-NEXT: jr $ra
620 ; MIPS3-NEXT: dsra $2, $4, 63
621 ;
622 ; MIPS64-LABEL: ashr_i128:
623 ; MIPS64: # %bb.0: # %entry
624 ; MIPS64-NEXT: dsrlv $1, $5, $7
625 ; MIPS64-NEXT: dsll $2, $4, 1
626 ; MIPS64-NEXT: sll $5, $7, 0
627 ; MIPS64-NEXT: not $3, $5
628 ; MIPS64-NEXT: dsllv $2, $2, $3
629 ; MIPS64-NEXT: or $3, $2, $1
630 ; MIPS64-NEXT: dsrav $2, $4, $7
631 ; MIPS64-NEXT: andi $1, $5, 64
632 ; MIPS64-NEXT: movn $3, $2, $1
633 ; MIPS64-NEXT: dsra $4, $4, 63
634 ; MIPS64-NEXT: jr $ra
635 ; MIPS64-NEXT: movn $2, $4, $1
636 ;
637 ; MIPS64R2-LABEL: ashr_i128:
638 ; MIPS64R2: # %bb.0: # %entry
639 ; MIPS64R2-NEXT: dsrlv $1, $5, $7
640 ; MIPS64R2-NEXT: dsll $2, $4, 1
641 ; MIPS64R2-NEXT: sll $5, $7, 0
642 ; MIPS64R2-NEXT: not $3, $5
643 ; MIPS64R2-NEXT: dsllv $2, $2, $3
644 ; MIPS64R2-NEXT: or $3, $2, $1
645 ; MIPS64R2-NEXT: dsrav $2, $4, $7
646 ; MIPS64R2-NEXT: andi $1, $5, 64
647 ; MIPS64R2-NEXT: movn $3, $2, $1
648 ; MIPS64R2-NEXT: dsra $4, $4, 63
649 ; MIPS64R2-NEXT: jr $ra
650 ; MIPS64R2-NEXT: movn $2, $4, $1
651 ;
652 ; MIPS64R6-LABEL: ashr_i128:
653 ; MIPS64R6: # %bb.0: # %entry
654 ; MIPS64R6-NEXT: dsrav $1, $4, $7
655 ; MIPS64R6-NEXT: sll $3, $7, 0
656 ; MIPS64R6-NEXT: andi $2, $3, 64
657 ; MIPS64R6-NEXT: sll $6, $2, 0
658 ; MIPS64R6-NEXT: seleqz $2, $1, $6
659 ; MIPS64R6-NEXT: dsra $8, $4, 63
660 ; MIPS64R6-NEXT: selnez $8, $8, $6
661 ; MIPS64R6-NEXT: or $2, $8, $2
662 ; MIPS64R6-NEXT: dsrlv $5, $5, $7
663 ; MIPS64R6-NEXT: dsll $4, $4, 1
664 ; MIPS64R6-NEXT: not $3, $3
665 ; MIPS64R6-NEXT: dsllv $3, $4, $3
666 ; MIPS64R6-NEXT: or $3, $3, $5
667 ; MIPS64R6-NEXT: seleqz $3, $3, $6
668 ; MIPS64R6-NEXT: selnez $1, $1, $6
669 ; MIPS64R6-NEXT: jr $ra
670 ; MIPS64R6-NEXT: or $3, $1, $3
671 ;
672 ; MMR3-LABEL: ashr_i128:
673 ; MMR3: # %bb.0: # %entry
674 ; MMR3-NEXT: addiusp -40
675 ; MMR3-NEXT: .cfi_def_cfa_offset 40
676 ; MMR3-NEXT: swp $16, 32($sp)
677 ; MMR3-NEXT: .cfi_offset 17, -4
678 ; MMR3-NEXT: .cfi_offset 16, -8
679 ; MMR3-NEXT: swl $7, 28($sp)
680 ; MMR3-NEXT: swl $6, 24($sp)
681 ; MMR3-NEXT: swl $5, 20($sp)
682 ; MMR3-NEXT: sra $1, $4, 31
683 ; MMR3-NEXT: swl $4, 16($sp)
684 ; MMR3-NEXT: swl $1, 12($sp)
685 ; MMR3-NEXT: swl $1, 8($sp)
686 ; MMR3-NEXT: swl $1, 4($sp)
687 ; MMR3-NEXT: swl $1, 0($sp)
688 ; MMR3-NEXT: swr $7, 31($sp)
689 ; MMR3-NEXT: swr $6, 27($sp)
690 ; MMR3-NEXT: swr $5, 23($sp)
691 ; MMR3-NEXT: swr $4, 19($sp)
692 ; MMR3-NEXT: swr $1, 15($sp)
693 ; MMR3-NEXT: swr $1, 11($sp)
694 ; MMR3-NEXT: swr $1, 7($sp)
695 ; MMR3-NEXT: swr $1, 3($sp)
696 ; MMR3-NEXT: addiur1sp $2, 0
697 ; MMR3-NEXT: addiur2 $2, $2, 16
698 ; MMR3-NEXT: lw $3, 68($sp)
699 ; MMR3-NEXT: ext $4, $3, 3, 4
700 ; MMR3-NEXT: subu16 $2, $2, $4
701 ; MMR3-NEXT: lwl $7, 4($2)
702 ; MMR3-NEXT: lwr $7, 7($2)
703 ; MMR3-NEXT: sll16 $4, $7, 1
704 ; MMR3-NEXT: lwl $5, 8($2)
705 ; MMR3-NEXT: lwr $5, 11($2)
706 ; MMR3-NEXT: andi16 $6, $3, 7
707 ; MMR3-NEXT: not16 $3, $6
708 ; MMR3-NEXT: andi16 $3, $3, 31
709 ; MMR3-NEXT: srlv $16, $5, $6
710 ; MMR3-NEXT: sllv $4, $4, $3
711 ; MMR3-NEXT: srlv $17, $7, $6
712 ; MMR3-NEXT: lwl $7, 0($2)
713 ; MMR3-NEXT: lwr $7, 3($2)
714 ; MMR3-NEXT: sll16 $3, $7, 1
715 ; MMR3-NEXT: xori $1, $6, 31
716 ; MMR3-NEXT: sllv $3, $3, $1
717 ; MMR3-NEXT: or16 $3, $17
718 ; MMR3-NEXT: or16 $4, $16
719 ; MMR3-NEXT: lwl $8, 12($2)
720 ; MMR3-NEXT: lwr $8, 15($2)
721 ; MMR3-NEXT: srlv $2, $8, $6
722 ; MMR3-NEXT: sll16 $5, $5, 1
723 ; MMR3-NEXT: sllv $5, $5, $1
724 ; MMR3-NEXT: or16 $5, $2
725 ; MMR3-NEXT: srav $2, $7, $6
726 ; MMR3-NEXT: lwp $16, 32($sp)
727 ; MMR3-NEXT: addiusp 40
728 ; MMR3-NEXT: jrc $ra
729 ;
730 ; MMR6-LABEL: ashr_i128:
731 ; MMR6: # %bb.0: # %entry
732 ; MMR6-NEXT: addiu $sp, $sp, -40
733 ; MMR6-NEXT: .cfi_def_cfa_offset 40
734 ; MMR6-NEXT: sw $16, 36($sp) # 4-byte Folded Spill
735 ; MMR6-NEXT: .cfi_offset 16, -4
736 ; MMR6-NEXT: sra $1, $4, 31
737 ; MMR6-NEXT: sw $7, 32($sp)
738 ; MMR6-NEXT: sw $6, 28($sp)
739 ; MMR6-NEXT: sw $5, 24($sp)
740 ; MMR6-NEXT: sw $4, 20($sp)
741 ; MMR6-NEXT: sw $1, 16($sp)
742 ; MMR6-NEXT: sw $1, 12($sp)
743 ; MMR6-NEXT: sw $1, 8($sp)
744 ; MMR6-NEXT: sw $1, 4($sp)
745 ; MMR6-NEXT: addiu $2, $sp, 4
746 ; MMR6-NEXT: addiur2 $2, $2, 16
747 ; MMR6-NEXT: lw $3, 68($sp)
748 ; MMR6-NEXT: ext $4, $3, 3, 4
749 ; MMR6-NEXT: subu16 $5, $2, $4
750 ; MMR6-NEXT: lw16 $4, 4($5)
751 ; MMR6-NEXT: sll16 $6, $4, 1
752 ; MMR6-NEXT: lw16 $7, 8($5)
753 ; MMR6-NEXT: andi16 $2, $3, 7
754 ; MMR6-NEXT: not16 $3, $2
755 ; MMR6-NEXT: andi16 $3, $3, 31
756 ; MMR6-NEXT: srlv $1, $7, $2
757 ; MMR6-NEXT: sllv $6, $6, $3
758 ; MMR6-NEXT: srlv $3, $4, $2
759 ; MMR6-NEXT: lw16 $16, 0($5)
760 ; MMR6-NEXT: sll16 $4, $16, 1
761 ; MMR6-NEXT: xori $8, $2, 31
762 ; MMR6-NEXT: sllv $4, $4, $8
763 ; MMR6-NEXT: or $3, $3, $4
764 ; MMR6-NEXT: or $4, $1, $6
765 ; MMR6-NEXT: lw16 $5, 12($5)
766 ; MMR6-NEXT: srlv $1, $5, $2
767 ; MMR6-NEXT: sll16 $5, $7, 1
768 ; MMR6-NEXT: sllv $5, $5, $8
769 ; MMR6-NEXT: or $5, $1, $5
770 ; MMR6-NEXT: srav $2, $16, $2
771 ; MMR6-NEXT: lw $16, 36($sp) # 4-byte Folded Reload
772 ; MMR6-NEXT: addiu $sp, $sp, 40
773 ; MMR6-NEXT: jrc $ra
774 entry:
775 %r = ashr i128 %a, %b
776 ret i128 %r
777 }