| blob | 77f9f0ed646ee2e09d90df42d4c3d28b0d876552 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips2 -relocation-model=pic | FileCheck %s \
3 ; RUN: -check-prefix=MIPS2
4 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 -relocation-model=pic | FileCheck %s \
5 ; RUN: -check-prefix=MIPS32
6 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \
7 ; RUN: -check-prefix=MIPS32R2
8 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \
9 ; RUN: -check-prefix=MIPS32R2
10 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \
11 ; RUN: -check-prefix=MIPS32R2
12 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \
13 ; RUN: -check-prefix=MIPS32R6
14 ; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips3 -relocation-model=pic | FileCheck %s \
15 ; RUN: -check-prefix=MIPS3
16 ; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips4 -relocation-model=pic | FileCheck %s \
17 ; RUN: -check-prefix=MIPS4
18 ; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64 -relocation-model=pic | FileCheck %s \
19 ; RUN: -check-prefix=MIPS64
20 ; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \
21 ; RUN: -check-prefix=MIPS64R2
22 ; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \
23 ; RUN: -check-prefix=MIPS64R2
24 ; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \
25 ; RUN: -check-prefix=MIPS64R2
26 ; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \
27 ; RUN: -check-prefix=MIPS64R6
28 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \
29 ; RUN: -check-prefix=MMR3
30 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
31 ; RUN: -check-prefix=MMR6
33 define signext i1 @shl_i1(i1 signext %a, i1 signext %b) {
34 ; MIPS2-LABEL: shl_i1:
35 ; MIPS2: # %bb.0: # %entry
36 ; MIPS2-NEXT: jr $ra
37 ; MIPS2-NEXT: move $2, $4
38 ;
39 ; MIPS32-LABEL: shl_i1:
40 ; MIPS32: # %bb.0: # %entry
41 ; MIPS32-NEXT: jr $ra
42 ; MIPS32-NEXT: move $2, $4
43 ;
44 ; MIPS32R2-LABEL: shl_i1:
45 ; MIPS32R2: # %bb.0: # %entry
46 ; MIPS32R2-NEXT: jr $ra
47 ; MIPS32R2-NEXT: move $2, $4
48 ;
49 ; MIPS32R6-LABEL: shl_i1:
50 ; MIPS32R6: # %bb.0: # %entry
51 ; MIPS32R6-NEXT: jr $ra
52 ; MIPS32R6-NEXT: move $2, $4
53 ;
54 ; MIPS3-LABEL: shl_i1:
55 ; MIPS3: # %bb.0: # %entry
56 ; MIPS3-NEXT: jr $ra
57 ; MIPS3-NEXT: move $2, $4
58 ;
59 ; MIPS4-LABEL: shl_i1:
60 ; MIPS4: # %bb.0: # %entry
61 ; MIPS4-NEXT: jr $ra
62 ; MIPS4-NEXT: move $2, $4
63 ;
64 ; MIPS64-LABEL: shl_i1:
65 ; MIPS64: # %bb.0: # %entry
66 ; MIPS64-NEXT: jr $ra
67 ; MIPS64-NEXT: move $2, $4
68 ;
69 ; MIPS64R2-LABEL: shl_i1:
70 ; MIPS64R2: # %bb.0: # %entry
71 ; MIPS64R2-NEXT: jr $ra
72 ; MIPS64R2-NEXT: move $2, $4
73 ;
74 ; MIPS64R6-LABEL: shl_i1:
75 ; MIPS64R6: # %bb.0: # %entry
76 ; MIPS64R6-NEXT: jr $ra
77 ; MIPS64R6-NEXT: move $2, $4
78 ;
79 ; MMR3-LABEL: shl_i1:
80 ; MMR3: # %bb.0: # %entry
81 ; MMR3-NEXT: move $2, $4
82 ; MMR3-NEXT: jrc $ra
83 ;
84 ; MMR6-LABEL: shl_i1:
85 ; MMR6: # %bb.0: # %entry
86 ; MMR6-NEXT: move $2, $4
87 ; MMR6-NEXT: jrc $ra
88 entry:
90 %r = shl i1 %a, %b
91 ret i1 %r
92 }
94 define signext i8 @shl_i8(i8 signext %a, i8 signext %b) {
95 ; MIPS2-LABEL: shl_i8:
96 ; MIPS2: # %bb.0: # %entry
97 ; MIPS2-NEXT: andi $1, $5, 255
98 ; MIPS2-NEXT: sllv $1, $4, $1
99 ; MIPS2-NEXT: sll $1, $1, 24
100 ; MIPS2-NEXT: jr $ra
101 ; MIPS2-NEXT: sra $2, $1, 24
102 ;
103 ; MIPS32-LABEL: shl_i8:
104 ; MIPS32: # %bb.0: # %entry
105 ; MIPS32-NEXT: andi $1, $5, 255
106 ; MIPS32-NEXT: sllv $1, $4, $1
107 ; MIPS32-NEXT: sll $1, $1, 24
108 ; MIPS32-NEXT: jr $ra
109 ; MIPS32-NEXT: sra $2, $1, 24
110 ;
111 ; MIPS32R2-LABEL: shl_i8:
112 ; MIPS32R2: # %bb.0: # %entry
113 ; MIPS32R2-NEXT: andi $1, $5, 255
114 ; MIPS32R2-NEXT: sllv $1, $4, $1
115 ; MIPS32R2-NEXT: jr $ra
116 ; MIPS32R2-NEXT: seb $2, $1
117 ;
118 ; MIPS32R6-LABEL: shl_i8:
119 ; MIPS32R6: # %bb.0: # %entry
120 ; MIPS32R6-NEXT: andi $1, $5, 255
121 ; MIPS32R6-NEXT: sllv $1, $4, $1
122 ; MIPS32R6-NEXT: jr $ra
123 ; MIPS32R6-NEXT: seb $2, $1
124 ;
125 ; MIPS3-LABEL: shl_i8:
126 ; MIPS3: # %bb.0: # %entry
127 ; MIPS3-NEXT: andi $1, $5, 255
128 ; MIPS3-NEXT: sllv $1, $4, $1
129 ; MIPS3-NEXT: sll $1, $1, 24
130 ; MIPS3-NEXT: jr $ra
131 ; MIPS3-NEXT: sra $2, $1, 24
132 ;
133 ; MIPS4-LABEL: shl_i8:
134 ; MIPS4: # %bb.0: # %entry
135 ; MIPS4-NEXT: andi $1, $5, 255
136 ; MIPS4-NEXT: sllv $1, $4, $1
137 ; MIPS4-NEXT: sll $1, $1, 24
138 ; MIPS4-NEXT: jr $ra
139 ; MIPS4-NEXT: sra $2, $1, 24
140 ;
141 ; MIPS64-LABEL: shl_i8:
142 ; MIPS64: # %bb.0: # %entry
143 ; MIPS64-NEXT: andi $1, $5, 255
144 ; MIPS64-NEXT: sllv $1, $4, $1
145 ; MIPS64-NEXT: sll $1, $1, 24
146 ; MIPS64-NEXT: jr $ra
147 ; MIPS64-NEXT: sra $2, $1, 24
148 ;
149 ; MIPS64R2-LABEL: shl_i8:
150 ; MIPS64R2: # %bb.0: # %entry
151 ; MIPS64R2-NEXT: andi $1, $5, 255
152 ; MIPS64R2-NEXT: sllv $1, $4, $1
153 ; MIPS64R2-NEXT: jr $ra
154 ; MIPS64R2-NEXT: seb $2, $1
155 ;
156 ; MIPS64R6-LABEL: shl_i8:
157 ; MIPS64R6: # %bb.0: # %entry
158 ; MIPS64R6-NEXT: andi $1, $5, 255
159 ; MIPS64R6-NEXT: sllv $1, $4, $1
160 ; MIPS64R6-NEXT: jr $ra
161 ; MIPS64R6-NEXT: seb $2, $1
162 ;
163 ; MMR3-LABEL: shl_i8:
164 ; MMR3: # %bb.0: # %entry
165 ; MMR3-NEXT: andi16 $2, $5, 255
166 ; MMR3-NEXT: sllv $1, $4, $2
167 ; MMR3-NEXT: jr $ra
168 ; MMR3-NEXT: seb $2, $1
169 ;
170 ; MMR6-LABEL: shl_i8:
171 ; MMR6: # %bb.0: # %entry
172 ; MMR6-NEXT: andi16 $2, $5, 255
173 ; MMR6-NEXT: sllv $1, $4, $2
174 ; MMR6-NEXT: seb $2, $1
175 ; MMR6-NEXT: jrc $ra
176 entry:
178 %r = shl i8 %a, %b
179 ret i8 %r
180 }
182 define signext i16 @shl_i16(i16 signext %a, i16 signext %b) {
183 ; MIPS2-LABEL: shl_i16:
184 ; MIPS2: # %bb.0: # %entry
185 ; MIPS2-NEXT: andi $1, $5, 65535
186 ; MIPS2-NEXT: sllv $1, $4, $1
187 ; MIPS2-NEXT: sll $1, $1, 16
188 ; MIPS2-NEXT: jr $ra
189 ; MIPS2-NEXT: sra $2, $1, 16
190 ;
191 ; MIPS32-LABEL: shl_i16:
192 ; MIPS32: # %bb.0: # %entry
193 ; MIPS32-NEXT: andi $1, $5, 65535
194 ; MIPS32-NEXT: sllv $1, $4, $1
195 ; MIPS32-NEXT: sll $1, $1, 16
196 ; MIPS32-NEXT: jr $ra
197 ; MIPS32-NEXT: sra $2, $1, 16
198 ;
199 ; MIPS32R2-LABEL: shl_i16:
200 ; MIPS32R2: # %bb.0: # %entry
201 ; MIPS32R2-NEXT: andi $1, $5, 65535
202 ; MIPS32R2-NEXT: sllv $1, $4, $1
203 ; MIPS32R2-NEXT: jr $ra
204 ; MIPS32R2-NEXT: seh $2, $1
205 ;
206 ; MIPS32R6-LABEL: shl_i16:
207 ; MIPS32R6: # %bb.0: # %entry
208 ; MIPS32R6-NEXT: andi $1, $5, 65535
209 ; MIPS32R6-NEXT: sllv $1, $4, $1
210 ; MIPS32R6-NEXT: jr $ra
211 ; MIPS32R6-NEXT: seh $2, $1
212 ;
213 ; MIPS3-LABEL: shl_i16:
214 ; MIPS3: # %bb.0: # %entry
215 ; MIPS3-NEXT: andi $1, $5, 65535
216 ; MIPS3-NEXT: sllv $1, $4, $1
217 ; MIPS3-NEXT: sll $1, $1, 16
218 ; MIPS3-NEXT: jr $ra
219 ; MIPS3-NEXT: sra $2, $1, 16
220 ;
221 ; MIPS4-LABEL: shl_i16:
222 ; MIPS4: # %bb.0: # %entry
223 ; MIPS4-NEXT: andi $1, $5, 65535
224 ; MIPS4-NEXT: sllv $1, $4, $1
225 ; MIPS4-NEXT: sll $1, $1, 16
226 ; MIPS4-NEXT: jr $ra
227 ; MIPS4-NEXT: sra $2, $1, 16
228 ;
229 ; MIPS64-LABEL: shl_i16:
230 ; MIPS64: # %bb.0: # %entry
231 ; MIPS64-NEXT: andi $1, $5, 65535
232 ; MIPS64-NEXT: sllv $1, $4, $1
233 ; MIPS64-NEXT: sll $1, $1, 16
234 ; MIPS64-NEXT: jr $ra
235 ; MIPS64-NEXT: sra $2, $1, 16
236 ;
237 ; MIPS64R2-LABEL: shl_i16:
238 ; MIPS64R2: # %bb.0: # %entry
239 ; MIPS64R2-NEXT: andi $1, $5, 65535
240 ; MIPS64R2-NEXT: sllv $1, $4, $1
241 ; MIPS64R2-NEXT: jr $ra
242 ; MIPS64R2-NEXT: seh $2, $1
243 ;
244 ; MIPS64R6-LABEL: shl_i16:
245 ; MIPS64R6: # %bb.0: # %entry
246 ; MIPS64R6-NEXT: andi $1, $5, 65535
247 ; MIPS64R6-NEXT: sllv $1, $4, $1
248 ; MIPS64R6-NEXT: jr $ra
249 ; MIPS64R6-NEXT: seh $2, $1
250 ;
251 ; MMR3-LABEL: shl_i16:
252 ; MMR3: # %bb.0: # %entry
253 ; MMR3-NEXT: andi16 $2, $5, 65535
254 ; MMR3-NEXT: sllv $1, $4, $2
255 ; MMR3-NEXT: jr $ra
256 ; MMR3-NEXT: seh $2, $1
257 ;
258 ; MMR6-LABEL: shl_i16:
259 ; MMR6: # %bb.0: # %entry
260 ; MMR6-NEXT: andi16 $2, $5, 65535
261 ; MMR6-NEXT: sllv $1, $4, $2
262 ; MMR6-NEXT: seh $2, $1
263 ; MMR6-NEXT: jrc $ra
264 entry:
266 %r = shl i16 %a, %b
267 ret i16 %r
268 }
270 define signext i32 @shl_i32(i32 signext %a, i32 signext %b) {
271 ; MIPS2-LABEL: shl_i32:
272 ; MIPS2: # %bb.0: # %entry
273 ; MIPS2-NEXT: jr $ra
274 ; MIPS2-NEXT: sllv $2, $4, $5
275 ;
276 ; MIPS32-LABEL: shl_i32:
277 ; MIPS32: # %bb.0: # %entry
278 ; MIPS32-NEXT: jr $ra
279 ; MIPS32-NEXT: sllv $2, $4, $5
280 ;
281 ; MIPS32R2-LABEL: shl_i32:
282 ; MIPS32R2: # %bb.0: # %entry
283 ; MIPS32R2-NEXT: jr $ra
284 ; MIPS32R2-NEXT: sllv $2, $4, $5
285 ;
286 ; MIPS32R6-LABEL: shl_i32:
287 ; MIPS32R6: # %bb.0: # %entry
288 ; MIPS32R6-NEXT: jr $ra
289 ; MIPS32R6-NEXT: sllv $2, $4, $5
290 ;
291 ; MIPS3-LABEL: shl_i32:
292 ; MIPS3: # %bb.0: # %entry
293 ; MIPS3-NEXT: jr $ra
294 ; MIPS3-NEXT: sllv $2, $4, $5
295 ;
296 ; MIPS4-LABEL: shl_i32:
297 ; MIPS4: # %bb.0: # %entry
298 ; MIPS4-NEXT: jr $ra
299 ; MIPS4-NEXT: sllv $2, $4, $5
300 ;
301 ; MIPS64-LABEL: shl_i32:
302 ; MIPS64: # %bb.0: # %entry
303 ; MIPS64-NEXT: jr $ra
304 ; MIPS64-NEXT: sllv $2, $4, $5
305 ;
306 ; MIPS64R2-LABEL: shl_i32:
307 ; MIPS64R2: # %bb.0: # %entry
308 ; MIPS64R2-NEXT: jr $ra
309 ; MIPS64R2-NEXT: sllv $2, $4, $5
310 ;
311 ; MIPS64R6-LABEL: shl_i32:
312 ; MIPS64R6: # %bb.0: # %entry
313 ; MIPS64R6-NEXT: jr $ra
314 ; MIPS64R6-NEXT: sllv $2, $4, $5
315 ;
316 ; MMR3-LABEL: shl_i32:
317 ; MMR3: # %bb.0: # %entry
318 ; MMR3-NEXT: jr $ra
319 ; MMR3-NEXT: sllv $2, $4, $5
320 ;
321 ; MMR6-LABEL: shl_i32:
322 ; MMR6: # %bb.0: # %entry
323 ; MMR6-NEXT: sllv $2, $4, $5
324 ; MMR6-NEXT: jrc $ra
325 entry:
327 %r = shl i32 %a, %b
328 ret i32 %r
329 }
331 define signext i64 @shl_i64(i64 signext %a, i64 signext %b) {
332 ; MIPS2-LABEL: shl_i64:
333 ; MIPS2: # %bb.0: # %entry
334 ; MIPS2-NEXT: sllv $6, $5, $7
335 ; MIPS2-NEXT: andi $8, $7, 32
336 ; MIPS2-NEXT: beqz $8, $BB4_3
337 ; MIPS2-NEXT: move $2, $6
338 ; MIPS2-NEXT: # %bb.1: # %entry
339 ; MIPS2-NEXT: beqz $8, $BB4_4
340 ; MIPS2-NEXT: addiu $3, $zero, 0
341 ; MIPS2-NEXT: $BB4_2: # %entry
342 ; MIPS2-NEXT: jr $ra
343 ; MIPS2-NEXT: nop
344 ; MIPS2-NEXT: $BB4_3: # %entry
345 ; MIPS2-NEXT: sllv $1, $4, $7
346 ; MIPS2-NEXT: not $2, $7
347 ; MIPS2-NEXT: srl $3, $5, 1
348 ; MIPS2-NEXT: srlv $2, $3, $2
349 ; MIPS2-NEXT: or $2, $1, $2
350 ; MIPS2-NEXT: bnez $8, $BB4_2
351 ; MIPS2-NEXT: addiu $3, $zero, 0
352 ; MIPS2-NEXT: $BB4_4: # %entry
353 ; MIPS2-NEXT: jr $ra
354 ; MIPS2-NEXT: move $3, $6
355 ;
356 ; MIPS32-LABEL: shl_i64:
357 ; MIPS32: # %bb.0: # %entry
358 ; MIPS32-NEXT: sllv $1, $4, $7
359 ; MIPS32-NEXT: not $2, $7
360 ; MIPS32-NEXT: srl $3, $5, 1
361 ; MIPS32-NEXT: srlv $2, $3, $2
362 ; MIPS32-NEXT: or $2, $1, $2
363 ; MIPS32-NEXT: sllv $3, $5, $7
364 ; MIPS32-NEXT: andi $1, $7, 32
365 ; MIPS32-NEXT: movn $2, $3, $1
366 ; MIPS32-NEXT: jr $ra
367 ; MIPS32-NEXT: movn $3, $zero, $1
368 ;
369 ; MIPS32R2-LABEL: shl_i64:
370 ; MIPS32R2: # %bb.0: # %entry
371 ; MIPS32R2-NEXT: sllv $1, $4, $7
372 ; MIPS32R2-NEXT: not $2, $7
373 ; MIPS32R2-NEXT: srl $3, $5, 1
374 ; MIPS32R2-NEXT: srlv $2, $3, $2
375 ; MIPS32R2-NEXT: or $2, $1, $2
376 ; MIPS32R2-NEXT: sllv $3, $5, $7
377 ; MIPS32R2-NEXT: andi $1, $7, 32
378 ; MIPS32R2-NEXT: movn $2, $3, $1
379 ; MIPS32R2-NEXT: jr $ra
380 ; MIPS32R2-NEXT: movn $3, $zero, $1
381 ;
382 ; MIPS32R6-LABEL: shl_i64:
383 ; MIPS32R6: # %bb.0: # %entry
384 ; MIPS32R6-NEXT: sllv $1, $4, $7
385 ; MIPS32R6-NEXT: not $2, $7
386 ; MIPS32R6-NEXT: srl $3, $5, 1
387 ; MIPS32R6-NEXT: srlv $2, $3, $2
388 ; MIPS32R6-NEXT: or $1, $1, $2
389 ; MIPS32R6-NEXT: andi $3, $7, 32
390 ; MIPS32R6-NEXT: seleqz $1, $1, $3
391 ; MIPS32R6-NEXT: sllv $4, $5, $7
392 ; MIPS32R6-NEXT: selnez $2, $4, $3
393 ; MIPS32R6-NEXT: or $2, $2, $1
394 ; MIPS32R6-NEXT: jr $ra
395 ; MIPS32R6-NEXT: seleqz $3, $4, $3
396 ;
397 ; MIPS3-LABEL: shl_i64:
398 ; MIPS3: # %bb.0: # %entry
399 ; MIPS3-NEXT: jr $ra
400 ; MIPS3-NEXT: dsllv $2, $4, $5
401 ;
402 ; MIPS4-LABEL: shl_i64:
403 ; MIPS4: # %bb.0: # %entry
404 ; MIPS4-NEXT: jr $ra
405 ; MIPS4-NEXT: dsllv $2, $4, $5
406 ;
407 ; MIPS64-LABEL: shl_i64:
408 ; MIPS64: # %bb.0: # %entry
409 ; MIPS64-NEXT: jr $ra
410 ; MIPS64-NEXT: dsllv $2, $4, $5
411 ;
412 ; MIPS64R2-LABEL: shl_i64:
413 ; MIPS64R2: # %bb.0: # %entry
414 ; MIPS64R2-NEXT: jr $ra
415 ; MIPS64R2-NEXT: dsllv $2, $4, $5
416 ;
417 ; MIPS64R6-LABEL: shl_i64:
418 ; MIPS64R6: # %bb.0: # %entry
419 ; MIPS64R6-NEXT: jr $ra
420 ; MIPS64R6-NEXT: dsllv $2, $4, $5
421 ;
422 ; MMR3-LABEL: shl_i64:
423 ; MMR3: # %bb.0: # %entry
424 ; MMR3-NEXT: sllv $3, $4, $7
425 ; MMR3-NEXT: not16 $2, $7
426 ; MMR3-NEXT: srl16 $4, $5, 1
427 ; MMR3-NEXT: srlv $2, $4, $2
428 ; MMR3-NEXT: or16 $2, $3
429 ; MMR3-NEXT: sllv $3, $5, $7
430 ; MMR3-NEXT: andi16 $4, $7, 32
431 ; MMR3-NEXT: movn $2, $3, $4
432 ; MMR3-NEXT: li16 $5, 0
433 ; MMR3-NEXT: jr $ra
434 ; MMR3-NEXT: movn $3, $5, $4
435 ;
436 ; MMR6-LABEL: shl_i64:
437 ; MMR6: # %bb.0: # %entry
438 ; MMR6-NEXT: sllv $1, $4, $7
439 ; MMR6-NEXT: not16 $2, $7
440 ; MMR6-NEXT: srl16 $3, $5, 1
441 ; MMR6-NEXT: srlv $2, $3, $2
442 ; MMR6-NEXT: or $1, $1, $2
443 ; MMR6-NEXT: andi16 $3, $7, 32
444 ; MMR6-NEXT: seleqz $1, $1, $3
445 ; MMR6-NEXT: sllv $4, $5, $7
446 ; MMR6-NEXT: selnez $2, $4, $3
447 ; MMR6-NEXT: or $2, $2, $1
448 ; MMR6-NEXT: seleqz $3, $4, $3
449 ; MMR6-NEXT: jrc $ra
450 entry:
452 %r = shl i64 %a, %b
453 ret i64 %r
454 }
456 define signext i128 @shl_i128(i128 signext %a, i128 signext %b) {
457 ; MIPS2-LABEL: shl_i128:
458 ; MIPS2: # %bb.0: # %entry
459 ; MIPS2-NEXT: addiu $sp, $sp, -32
460 ; MIPS2-NEXT: .cfi_def_cfa_offset 32
461 ; MIPS2-NEXT: swl $zero, 28($sp)
462 ; MIPS2-NEXT: swl $zero, 24($sp)
463 ; MIPS2-NEXT: swl $zero, 20($sp)
464 ; MIPS2-NEXT: swl $zero, 16($sp)
465 ; MIPS2-NEXT: swl $7, 12($sp)
466 ; MIPS2-NEXT: swl $6, 8($sp)
467 ; MIPS2-NEXT: swl $5, 4($sp)
468 ; MIPS2-NEXT: swl $4, 0($sp)
469 ; MIPS2-NEXT: swr $zero, 31($sp)
470 ; MIPS2-NEXT: swr $zero, 27($sp)
471 ; MIPS2-NEXT: swr $zero, 23($sp)
472 ; MIPS2-NEXT: swr $zero, 19($sp)
473 ; MIPS2-NEXT: swr $7, 15($sp)
474 ; MIPS2-NEXT: swr $6, 11($sp)
475 ; MIPS2-NEXT: swr $5, 7($sp)
476 ; MIPS2-NEXT: swr $4, 3($sp)
477 ; MIPS2-NEXT: lw $1, 60($sp)
478 ; MIPS2-NEXT: srl $2, $1, 3
479 ; MIPS2-NEXT: andi $2, $2, 15
480 ; MIPS2-NEXT: addiu $3, $sp, 0
481 ; MIPS2-NEXT: addu $4, $3, $2
482 ; MIPS2-NEXT: lwl $5, 8($4)
483 ; MIPS2-NEXT: lwr $5, 11($4)
484 ; MIPS2-NEXT: srl $2, $5, 1
485 ; MIPS2-NEXT: lwl $3, 4($4)
486 ; MIPS2-NEXT: lwr $3, 7($4)
487 ; MIPS2-NEXT: andi $1, $1, 7
488 ; MIPS2-NEXT: not $6, $1
489 ; MIPS2-NEXT: andi $6, $6, 31
490 ; MIPS2-NEXT: sllv $7, $3, $1
491 ; MIPS2-NEXT: srlv $6, $2, $6
492 ; MIPS2-NEXT: lwl $2, 0($4)
493 ; MIPS2-NEXT: lwr $2, 3($4)
494 ; MIPS2-NEXT: sllv $2, $2, $1
495 ; MIPS2-NEXT: srl $3, $3, 1
496 ; MIPS2-NEXT: xori $8, $1, 31
497 ; MIPS2-NEXT: srlv $3, $3, $8
498 ; MIPS2-NEXT: or $2, $2, $3
499 ; MIPS2-NEXT: or $3, $7, $6
500 ; MIPS2-NEXT: sllv $5, $5, $1
501 ; MIPS2-NEXT: lwl $6, 12($4)
502 ; MIPS2-NEXT: lwr $6, 15($4)
503 ; MIPS2-NEXT: srl $4, $6, 1
504 ; MIPS2-NEXT: srlv $4, $4, $8
505 ; MIPS2-NEXT: or $4, $5, $4
506 ; MIPS2-NEXT: sllv $5, $6, $1
507 ; MIPS2-NEXT: jr $ra
508 ; MIPS2-NEXT: addiu $sp, $sp, 32
509 ;
510 ; MIPS32-LABEL: shl_i128:
511 ; MIPS32: # %bb.0: # %entry
512 ; MIPS32-NEXT: addiu $sp, $sp, -32
513 ; MIPS32-NEXT: .cfi_def_cfa_offset 32
514 ; MIPS32-NEXT: swl $zero, 28($sp)
515 ; MIPS32-NEXT: swl $zero, 24($sp)
516 ; MIPS32-NEXT: swl $zero, 20($sp)
517 ; MIPS32-NEXT: swl $zero, 16($sp)
518 ; MIPS32-NEXT: swl $7, 12($sp)
519 ; MIPS32-NEXT: swl $6, 8($sp)
520 ; MIPS32-NEXT: swl $5, 4($sp)
521 ; MIPS32-NEXT: swl $4, 0($sp)
522 ; MIPS32-NEXT: swr $zero, 31($sp)
523 ; MIPS32-NEXT: swr $zero, 27($sp)
524 ; MIPS32-NEXT: swr $zero, 23($sp)
525 ; MIPS32-NEXT: swr $zero, 19($sp)
526 ; MIPS32-NEXT: swr $7, 15($sp)
527 ; MIPS32-NEXT: swr $6, 11($sp)
528 ; MIPS32-NEXT: swr $5, 7($sp)
529 ; MIPS32-NEXT: swr $4, 3($sp)
530 ; MIPS32-NEXT: lw $1, 60($sp)
531 ; MIPS32-NEXT: srl $2, $1, 3
532 ; MIPS32-NEXT: andi $2, $2, 15
533 ; MIPS32-NEXT: addiu $3, $sp, 0
534 ; MIPS32-NEXT: addu $4, $3, $2
535 ; MIPS32-NEXT: lwl $5, 8($4)
536 ; MIPS32-NEXT: lwr $5, 11($4)
537 ; MIPS32-NEXT: srl $2, $5, 1
538 ; MIPS32-NEXT: lwl $3, 4($4)
539 ; MIPS32-NEXT: lwr $3, 7($4)
540 ; MIPS32-NEXT: andi $1, $1, 7
541 ; MIPS32-NEXT: not $6, $1
542 ; MIPS32-NEXT: andi $6, $6, 31
543 ; MIPS32-NEXT: sllv $7, $3, $1
544 ; MIPS32-NEXT: srlv $6, $2, $6
545 ; MIPS32-NEXT: lwl $2, 0($4)
546 ; MIPS32-NEXT: lwr $2, 3($4)
547 ; MIPS32-NEXT: sllv $2, $2, $1
548 ; MIPS32-NEXT: srl $3, $3, 1
549 ; MIPS32-NEXT: xori $8, $1, 31
550 ; MIPS32-NEXT: srlv $3, $3, $8
551 ; MIPS32-NEXT: or $2, $2, $3
552 ; MIPS32-NEXT: or $3, $7, $6
553 ; MIPS32-NEXT: sllv $5, $5, $1
554 ; MIPS32-NEXT: lwl $6, 12($4)
555 ; MIPS32-NEXT: lwr $6, 15($4)
556 ; MIPS32-NEXT: srl $4, $6, 1
557 ; MIPS32-NEXT: srlv $4, $4, $8
558 ; MIPS32-NEXT: or $4, $5, $4
559 ; MIPS32-NEXT: sllv $5, $6, $1
560 ; MIPS32-NEXT: jr $ra
561 ; MIPS32-NEXT: addiu $sp, $sp, 32
562 ;
563 ; MIPS32R2-LABEL: shl_i128:
564 ; MIPS32R2: # %bb.0: # %entry
565 ; MIPS32R2-NEXT: addiu $sp, $sp, -32
566 ; MIPS32R2-NEXT: .cfi_def_cfa_offset 32
567 ; MIPS32R2-NEXT: swl $zero, 28($sp)
568 ; MIPS32R2-NEXT: swl $zero, 24($sp)
569 ; MIPS32R2-NEXT: swl $zero, 20($sp)
570 ; MIPS32R2-NEXT: swl $zero, 16($sp)
571 ; MIPS32R2-NEXT: swl $7, 12($sp)
572 ; MIPS32R2-NEXT: swl $6, 8($sp)
573 ; MIPS32R2-NEXT: swl $5, 4($sp)
574 ; MIPS32R2-NEXT: swl $4, 0($sp)
575 ; MIPS32R2-NEXT: swr $zero, 31($sp)
576 ; MIPS32R2-NEXT: swr $zero, 27($sp)
577 ; MIPS32R2-NEXT: swr $zero, 23($sp)
578 ; MIPS32R2-NEXT: swr $zero, 19($sp)
579 ; MIPS32R2-NEXT: swr $7, 15($sp)
580 ; MIPS32R2-NEXT: swr $6, 11($sp)
581 ; MIPS32R2-NEXT: swr $5, 7($sp)
582 ; MIPS32R2-NEXT: swr $4, 3($sp)
583 ; MIPS32R2-NEXT: lw $1, 60($sp)
584 ; MIPS32R2-NEXT: ext $2, $1, 3, 4
585 ; MIPS32R2-NEXT: addiu $3, $sp, 0
586 ; MIPS32R2-NEXT: addu $4, $3, $2
587 ; MIPS32R2-NEXT: lwl $5, 8($4)
588 ; MIPS32R2-NEXT: lwr $5, 11($4)
589 ; MIPS32R2-NEXT: srl $2, $5, 1
590 ; MIPS32R2-NEXT: lwl $3, 4($4)
591 ; MIPS32R2-NEXT: lwr $3, 7($4)
592 ; MIPS32R2-NEXT: andi $1, $1, 7
593 ; MIPS32R2-NEXT: not $6, $1
594 ; MIPS32R2-NEXT: andi $6, $6, 31
595 ; MIPS32R2-NEXT: sllv $7, $3, $1
596 ; MIPS32R2-NEXT: srlv $6, $2, $6
597 ; MIPS32R2-NEXT: lwl $2, 0($4)
598 ; MIPS32R2-NEXT: lwr $2, 3($4)
599 ; MIPS32R2-NEXT: sllv $2, $2, $1
600 ; MIPS32R2-NEXT: srl $3, $3, 1
601 ; MIPS32R2-NEXT: xori $8, $1, 31
602 ; MIPS32R2-NEXT: srlv $3, $3, $8
603 ; MIPS32R2-NEXT: or $2, $2, $3
604 ; MIPS32R2-NEXT: or $3, $7, $6
605 ; MIPS32R2-NEXT: sllv $5, $5, $1
606 ; MIPS32R2-NEXT: lwl $6, 12($4)
607 ; MIPS32R2-NEXT: lwr $6, 15($4)
608 ; MIPS32R2-NEXT: srl $4, $6, 1
609 ; MIPS32R2-NEXT: srlv $4, $4, $8
610 ; MIPS32R2-NEXT: or $4, $5, $4
611 ; MIPS32R2-NEXT: sllv $5, $6, $1
612 ; MIPS32R2-NEXT: jr $ra
613 ; MIPS32R2-NEXT: addiu $sp, $sp, 32
614 ;
615 ; MIPS32R6-LABEL: shl_i128:
616 ; MIPS32R6: # %bb.0: # %entry
617 ; MIPS32R6-NEXT: addiu $sp, $sp, -32
618 ; MIPS32R6-NEXT: .cfi_def_cfa_offset 32
619 ; MIPS32R6-NEXT: lw $1, 60($sp)
620 ; MIPS32R6-NEXT: sw $7, 12($sp)
621 ; MIPS32R6-NEXT: sw $6, 8($sp)
622 ; MIPS32R6-NEXT: sw $5, 4($sp)
623 ; MIPS32R6-NEXT: sw $4, 0($sp)
624 ; MIPS32R6-NEXT: ext $2, $1, 3, 4
625 ; MIPS32R6-NEXT: addiu $3, $sp, 0
626 ; MIPS32R6-NEXT: addu $4, $3, $2
627 ; MIPS32R6-NEXT: sw $zero, 28($sp)
628 ; MIPS32R6-NEXT: sw $zero, 24($sp)
629 ; MIPS32R6-NEXT: sw $zero, 20($sp)
630 ; MIPS32R6-NEXT: sw $zero, 16($sp)
631 ; MIPS32R6-NEXT: lw $5, 8($4)
632 ; MIPS32R6-NEXT: srl $2, $5, 1
633 ; MIPS32R6-NEXT: lw $3, 4($4)
634 ; MIPS32R6-NEXT: andi $1, $1, 7
635 ; MIPS32R6-NEXT: not $6, $1
636 ; MIPS32R6-NEXT: andi $6, $6, 31
637 ; MIPS32R6-NEXT: sllv $7, $3, $1
638 ; MIPS32R6-NEXT: srlv $6, $2, $6
639 ; MIPS32R6-NEXT: lw $2, 0($4)
640 ; MIPS32R6-NEXT: sllv $2, $2, $1
641 ; MIPS32R6-NEXT: srl $3, $3, 1
642 ; MIPS32R6-NEXT: xori $8, $1, 31
643 ; MIPS32R6-NEXT: srlv $3, $3, $8
644 ; MIPS32R6-NEXT: or $2, $2, $3
645 ; MIPS32R6-NEXT: or $3, $7, $6
646 ; MIPS32R6-NEXT: sllv $5, $5, $1
647 ; MIPS32R6-NEXT: lw $6, 12($4)
648 ; MIPS32R6-NEXT: srl $4, $6, 1
649 ; MIPS32R6-NEXT: srlv $4, $4, $8
650 ; MIPS32R6-NEXT: or $4, $5, $4
651 ; MIPS32R6-NEXT: sllv $5, $6, $1
652 ; MIPS32R6-NEXT: jr $ra
653 ; MIPS32R6-NEXT: addiu $sp, $sp, 32
654 ;
655 ; MIPS3-LABEL: shl_i128:
656 ; MIPS3: # %bb.0: # %entry
657 ; MIPS3-NEXT: sll $3, $7, 0
658 ; MIPS3-NEXT: dsllv $6, $5, $7
659 ; MIPS3-NEXT: andi $8, $3, 64
660 ; MIPS3-NEXT: beqz $8, .LBB5_3
661 ; MIPS3-NEXT: move $2, $6
662 ; MIPS3-NEXT: # %bb.1: # %entry
663 ; MIPS3-NEXT: beqz $8, .LBB5_4
664 ; MIPS3-NEXT: daddiu $3, $zero, 0
665 ; MIPS3-NEXT: .LBB5_2: # %entry
666 ; MIPS3-NEXT: jr $ra
667 ; MIPS3-NEXT: nop
668 ; MIPS3-NEXT: .LBB5_3: # %entry
669 ; MIPS3-NEXT: dsllv $1, $4, $7
670 ; MIPS3-NEXT: dsrl $2, $5, 1
671 ; MIPS3-NEXT: not $3, $3
672 ; MIPS3-NEXT: dsrlv $2, $2, $3
673 ; MIPS3-NEXT: or $2, $1, $2
674 ; MIPS3-NEXT: bnez $8, .LBB5_2
675 ; MIPS3-NEXT: daddiu $3, $zero, 0
676 ; MIPS3-NEXT: .LBB5_4: # %entry
677 ; MIPS3-NEXT: jr $ra
678 ; MIPS3-NEXT: move $3, $6
679 ;
680 ; MIPS4-LABEL: shl_i128:
681 ; MIPS4: # %bb.0: # %entry
682 ; MIPS4-NEXT: dsllv $1, $4, $7
683 ; MIPS4-NEXT: dsrl $2, $5, 1
684 ; MIPS4-NEXT: sll $4, $7, 0
685 ; MIPS4-NEXT: not $3, $4
686 ; MIPS4-NEXT: dsrlv $2, $2, $3
687 ; MIPS4-NEXT: or $2, $1, $2
688 ; MIPS4-NEXT: dsllv $3, $5, $7
689 ; MIPS4-NEXT: andi $1, $4, 64
690 ; MIPS4-NEXT: movn $2, $3, $1
691 ; MIPS4-NEXT: jr $ra
692 ; MIPS4-NEXT: movn $3, $zero, $1
693 ;
694 ; MIPS64-LABEL: shl_i128:
695 ; MIPS64: # %bb.0: # %entry
696 ; MIPS64-NEXT: dsllv $1, $4, $7
697 ; MIPS64-NEXT: dsrl $2, $5, 1
698 ; MIPS64-NEXT: sll $4, $7, 0
699 ; MIPS64-NEXT: not $3, $4
700 ; MIPS64-NEXT: dsrlv $2, $2, $3
701 ; MIPS64-NEXT: or $2, $1, $2
702 ; MIPS64-NEXT: dsllv $3, $5, $7
703 ; MIPS64-NEXT: andi $1, $4, 64
704 ; MIPS64-NEXT: movn $2, $3, $1
705 ; MIPS64-NEXT: jr $ra
706 ; MIPS64-NEXT: movn $3, $zero, $1
707 ;
708 ; MIPS64R2-LABEL: shl_i128:
709 ; MIPS64R2: # %bb.0: # %entry
710 ; MIPS64R2-NEXT: dsllv $1, $4, $7
711 ; MIPS64R2-NEXT: dsrl $2, $5, 1
712 ; MIPS64R2-NEXT: sll $4, $7, 0
713 ; MIPS64R2-NEXT: not $3, $4
714 ; MIPS64R2-NEXT: dsrlv $2, $2, $3
715 ; MIPS64R2-NEXT: or $2, $1, $2
716 ; MIPS64R2-NEXT: dsllv $3, $5, $7
717 ; MIPS64R2-NEXT: andi $1, $4, 64
718 ; MIPS64R2-NEXT: movn $2, $3, $1
719 ; MIPS64R2-NEXT: jr $ra
720 ; MIPS64R2-NEXT: movn $3, $zero, $1
721 ;
722 ; MIPS64R6-LABEL: shl_i128:
723 ; MIPS64R6: # %bb.0: # %entry
724 ; MIPS64R6-NEXT: dsllv $1, $4, $7
725 ; MIPS64R6-NEXT: dsrl $2, $5, 1
726 ; MIPS64R6-NEXT: sll $3, $7, 0
727 ; MIPS64R6-NEXT: not $4, $3
728 ; MIPS64R6-NEXT: dsrlv $2, $2, $4
729 ; MIPS64R6-NEXT: or $1, $1, $2
730 ; MIPS64R6-NEXT: andi $2, $3, 64
731 ; MIPS64R6-NEXT: sll $3, $2, 0
732 ; MIPS64R6-NEXT: seleqz $1, $1, $3
733 ; MIPS64R6-NEXT: dsllv $4, $5, $7
734 ; MIPS64R6-NEXT: selnez $2, $4, $3
735 ; MIPS64R6-NEXT: or $2, $2, $1
736 ; MIPS64R6-NEXT: jr $ra
737 ; MIPS64R6-NEXT: seleqz $3, $4, $3
738 ;
739 ; MMR3-LABEL: shl_i128:
740 ; MMR3: # %bb.0: # %entry
741 ; MMR3-NEXT: addiusp -40
742 ; MMR3-NEXT: .cfi_def_cfa_offset 40
743 ; MMR3-NEXT: swp $16, 32($sp)
744 ; MMR3-NEXT: .cfi_offset 17, -4
745 ; MMR3-NEXT: .cfi_offset 16, -8
746 ; MMR3-NEXT: li16 $2, 0
747 ; MMR3-NEXT: swl $2, 28($sp)
748 ; MMR3-NEXT: swl $2, 24($sp)
749 ; MMR3-NEXT: swl $2, 20($sp)
750 ; MMR3-NEXT: swl $2, 16($sp)
751 ; MMR3-NEXT: swl $7, 12($sp)
752 ; MMR3-NEXT: swl $6, 8($sp)
753 ; MMR3-NEXT: swl $5, 4($sp)
754 ; MMR3-NEXT: swl $4, 0($sp)
755 ; MMR3-NEXT: swr $2, 31($sp)
756 ; MMR3-NEXT: swr $2, 27($sp)
757 ; MMR3-NEXT: swr $2, 23($sp)
758 ; MMR3-NEXT: swr $2, 19($sp)
759 ; MMR3-NEXT: swr $7, 15($sp)
760 ; MMR3-NEXT: swr $6, 11($sp)
761 ; MMR3-NEXT: swr $5, 7($sp)
762 ; MMR3-NEXT: swr $4, 3($sp)
763 ; MMR3-NEXT: lw $2, 68($sp)
764 ; MMR3-NEXT: ext $3, $2, 3, 4
765 ; MMR3-NEXT: addiur1sp $4, 0
766 ; MMR3-NEXT: addu16 $4, $4, $3
767 ; MMR3-NEXT: lwl $6, 8($4)
768 ; MMR3-NEXT: lwr $6, 11($4)
769 ; MMR3-NEXT: srl16 $3, $6, 1
770 ; MMR3-NEXT: lwl $7, 4($4)
771 ; MMR3-NEXT: lwr $7, 7($4)
772 ; MMR3-NEXT: andi16 $5, $2, 7
773 ; MMR3-NEXT: not16 $2, $5
774 ; MMR3-NEXT: andi16 $2, $2, 31
775 ; MMR3-NEXT: sllv $16, $7, $5
776 ; MMR3-NEXT: srlv $3, $3, $2
777 ; MMR3-NEXT: lwl $1, 0($4)
778 ; MMR3-NEXT: lwr $1, 3($4)
779 ; MMR3-NEXT: sllv $17, $1, $5
780 ; MMR3-NEXT: srl16 $2, $7, 1
781 ; MMR3-NEXT: xori $1, $5, 31
782 ; MMR3-NEXT: srlv $2, $2, $1
783 ; MMR3-NEXT: or16 $2, $17
784 ; MMR3-NEXT: or16 $3, $16
785 ; MMR3-NEXT: sllv $6, $6, $5
786 ; MMR3-NEXT: lwl $7, 12($4)
787 ; MMR3-NEXT: lwr $7, 15($4)
788 ; MMR3-NEXT: srl16 $4, $7, 1
789 ; MMR3-NEXT: srlv $4, $4, $1
790 ; MMR3-NEXT: or16 $4, $6
791 ; MMR3-NEXT: sllv $5, $7, $5
792 ; MMR3-NEXT: lwp $16, 32($sp)
793 ; MMR3-NEXT: addiusp 40
794 ; MMR3-NEXT: jrc $ra
795 ;
796 ; MMR6-LABEL: shl_i128:
797 ; MMR6: # %bb.0: # %entry
798 ; MMR6-NEXT: addiu $sp, $sp, -32
799 ; MMR6-NEXT: .cfi_def_cfa_offset 32
800 ; MMR6-NEXT: li16 $2, 0
801 ; MMR6-NEXT: sw $2, 28($sp)
802 ; MMR6-NEXT: sw $2, 24($sp)
803 ; MMR6-NEXT: sw $2, 20($sp)
804 ; MMR6-NEXT: sw $2, 16($sp)
805 ; MMR6-NEXT: sw $7, 12($sp)
806 ; MMR6-NEXT: sw $6, 8($sp)
807 ; MMR6-NEXT: sw $5, 4($sp)
808 ; MMR6-NEXT: sw $4, 0($sp)
809 ; MMR6-NEXT: lw $2, 60($sp)
810 ; MMR6-NEXT: ext $3, $2, 3, 4
811 ; MMR6-NEXT: addiu $4, $sp, 0
812 ; MMR6-NEXT: addu16 $4, $4, $3
813 ; MMR6-NEXT: lw16 $6, 8($4)
814 ; MMR6-NEXT: srl16 $3, $6, 1
815 ; MMR6-NEXT: lw16 $7, 4($4)
816 ; MMR6-NEXT: andi16 $5, $2, 7
817 ; MMR6-NEXT: not16 $2, $5
818 ; MMR6-NEXT: andi16 $2, $2, 31
819 ; MMR6-NEXT: sllv $1, $7, $5
820 ; MMR6-NEXT: srlv $3, $3, $2
821 ; MMR6-NEXT: lw16 $2, 0($4)
822 ; MMR6-NEXT: sllv $2, $2, $5
823 ; MMR6-NEXT: srl16 $7, $7, 1
824 ; MMR6-NEXT: xori $8, $5, 31
825 ; MMR6-NEXT: srlv $7, $7, $8
826 ; MMR6-NEXT: or $2, $2, $7
827 ; MMR6-NEXT: or $3, $1, $3
828 ; MMR6-NEXT: sllv $1, $6, $5
829 ; MMR6-NEXT: lw16 $6, 12($4)
830 ; MMR6-NEXT: srl16 $4, $6, 1
831 ; MMR6-NEXT: srlv $4, $4, $8
832 ; MMR6-NEXT: or $4, $1, $4
833 ; MMR6-NEXT: sllv $5, $6, $5
834 ; MMR6-NEXT: addiu $sp, $sp, 32
835 ; MMR6-NEXT: jrc $ra
836 entry:
838 ; o32 shouldn't use TImode helpers.
839 ; GP32-NOT: lw $25, %call16(__ashlti3)($gp)
840 ; MM-NOT: lw $25, %call16(__ashlti3)($2)
842 %r = shl i128 %a, %b
843 ret i128 %r
844 }