| blob | 691738c298d8a4afa970aebed5fbf9e798169df3 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
3 ; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
4 ; RUN: -check-prefix=P9BE -implicit-check-not frsp
5 ; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
6 ; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
7 ; RUN: -check-prefix=P9LE -implicit-check-not frsp
8 ; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
9 ; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
10 ; RUN: -check-prefix=P8BE -implicit-check-not frsp
11 ; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
12 ; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
13 ; RUN: -check-prefix=P8LE -implicit-check-not frsp
15 ; This test case comes from the following C test case (included as it may be
16 ; slightly more readable than the LLVM IR.
18 ;/* This test case provides various ways of building vectors to ensure we
19 ; produce optimal code for all cases. The cases are (for each type):
20 ; - All zeros
21 ; - All ones - split to build-vector-allones.ll
22 ; - Splat of a constant
23 ; - From different values already in registers
24 ; - From different constants
25 ; - From different values in memory
26 ; - Splat of a value in register
27 ; - Splat of a value in memory
28 ; - Inserting element into existing vector
29 ; - Inserting element from existing vector into existing vector
30 ;
31 ; With conversions (float <-> int)
32 ; - Splat of a constant
33 ; - From different values already in registers
34 ; - From different constants
35 ; - From different values in memory
36 ; - Splat of a value in register
37 ; - Splat of a value in memory
38 ; - Inserting element into existing vector
39 ; - Inserting element from existing vector into existing vector
40 ;*/
41 ;
42 ;/*=================================== int ===================================*/
43 ;// P8: xxlxor //
44 ;// P9: xxlxor //
45 ;vector int allZeroi() { //
46 ; return (vector int)0; //
47 ;} //
48 ;// P8: vspltisb -1 //
49 ;// P9: xxspltisb 255 //
50 ;vector int spltConst1i() { //
51 ; return (vector int)1; //
52 ;} //
53 ;// P8: vspltisw -15; vsrw //
54 ;// P9: vspltisw -15; vsrw //
55 ;vector int spltConst16ki() { //
56 ; return (vector int)((1<<15) - 1); //
57 ;} //
58 ;// P8: vspltisw -16; vsrw //
59 ;// P9: vspltisw -16; vsrw //
60 ;vector int spltConst32ki() { //
61 ; return (vector int)((1<<16) - 1); //
62 ;} //
63 ;// P8: 4 x mtvsrwz, 2 x xxmrgh, vmrgow //
64 ;// P9: 2 x mtvsrdd, vmrgow //
65 ;vector int fromRegsi(int a, int b, int c, int d) { //
66 ; return (vector int){ a, b, c, d }; //
67 ;} //
68 ;// P8: lxvd2x, xxswapd //
69 ;// P9: lxvx (or even lxv) //
70 ;vector int fromDiffConstsi() { //
71 ; return (vector int) { 242, -113, 889, 19 }; //
72 ;} //
73 ;// P8: lxvd2x, xxswapd //
74 ;// P9: lxvx //
75 ;vector int fromDiffMemConsAi(int *arr) { //
76 ; return (vector int) { arr[0], arr[1], arr[2], arr[3] }; //
77 ;} //
78 ;// P8: 2 x lxvd2x, 2 x xxswapd, vperm //
79 ;// P9: 2 x lxvx, vperm //
80 ;vector int fromDiffMemConsDi(int *arr) { //
81 ; return (vector int) { arr[3], arr[2], arr[1], arr[0] }; //
82 ;} //
83 ;// P8: sldi 2, lxvd2x, xxswapd //
84 ;// P9: sldi 2, lxvx //
85 ;vector int fromDiffMemVarAi(int *arr, int elem) { //
86 ; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; //
87 ;} //
88 ;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm //
89 ;// P9: sldi 2, 2 x lxvx, vperm //
90 ;vector int fromDiffMemVarDi(int *arr, int elem) { //
91 ; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; //
92 ;} //
93 ;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow //
94 ;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow //
95 ;vector int fromRandMemConsi(int *arr) { //
96 ; return (vector int) { arr[4], arr[18], arr[2], arr[88] }; //
97 ;} //
98 ;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow //
99 ;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow //
100 ;vector int fromRandMemVari(int *arr, int elem) { //
101 ; return (vector int) { arr[elem+4], arr[elem+1], arr[elem+2], arr[elem+8] };//
102 ;} //
103 ;// P8: mtvsrwz, xxspltw //
104 ;// P9: mtvsrws //
105 ;vector int spltRegVali(int val) { //
106 ; return (vector int) val; //
107 ;} //
108 ;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw //
109 ;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw //
110 ;vector int spltMemVali(int *ptr) { //
111 ; return (vector int)*ptr; //
112 ;} //
113 ;// P8: vspltisw //
114 ;// P9: vspltisw //
115 ;vector int spltCnstConvftoi() { //
116 ; return (vector int) 4.74f; //
117 ;} //
118 ;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
119 ;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
120 ;vector int fromRegsConvftoi(float a, float b, float c, float d) { //
121 ; return (vector int) { a, b, c, d }; //
122 ;} //
123 ;// P8: lxvd2x, xxswapd //
124 ;// P9: lxvx (even lxv) //
125 ;vector int fromDiffConstsConvftoi() { //
126 ; return (vector int) { 24.46f, 234.f, 988.19f, 422.39f }; //
127 ;} //
128 ;// P8: lxvd2x, xxswapd, xvcvspsxws //
129 ;// P9: lxvx, xvcvspsxws //
130 ;vector int fromDiffMemConsAConvftoi(ptr ptr) { //
131 ; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; //
132 ;} //
133 ;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspsxws //
134 ;// P9: 2 x lxvx, vperm, xvcvspsxws //
135 ;vector int fromDiffMemConsDConvftoi(ptr ptr) { //
136 ; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //
137 ;} //
138 ;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
139 ;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
140 ;// Note: if the consecutive loads learns to handle pre-inc, this can be: //
141 ;// sldi 2, load, xvcvspuxws //
142 ;vector int fromDiffMemVarAConvftoi(ptr arr, int elem) { //
143 ; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; //
144 ;} //
145 ;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
146 ;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
147 ;// Note: if the consecutive loads learns to handle pre-inc, this can be: //
148 ;// sldi 2, 2 x load, vperm, xvcvspuxws //
149 ;vector int fromDiffMemVarDConvftoi(ptr arr, int elem) { //
150 ; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; //
151 ;} //
152 ;// P8: xscvdpsxws, xxspltw //
153 ;// P9: xscvdpsxws, xxspltw //
154 ;vector int spltRegValConvftoi(float val) { //
155 ; return (vector int) val; //
156 ;} //
157 ;// P8: lxsspx, xscvdpsxws, xxspltw //
158 ;// P9: lxvwsx, xvcvspsxws //
159 ;vector int spltMemValConvftoi(ptr ptr) { //
160 ; return (vector int)*ptr; //
161 ;} //
162 ;// P8: vspltisw //
163 ;// P9: vspltisw //
164 ;vector int spltCnstConvdtoi() { //
165 ; return (vector int) 4.74; //
166 ;} //
167 ;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
168 ;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
169 ;vector int fromRegsConvdtoi(double a, double b, double c, double d) { //
170 ; return (vector int) { a, b, c, d }; //
171 ;} //
172 ;// P8: lxvd2x, xxswapd //
173 ;// P9: lxvx (even lxv) //
174 ;vector int fromDiffConstsConvdtoi() { //
175 ; return (vector int) { 24.46, 234., 988.19, 422.39 }; //
176 ;} //
177 ;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew //
178 ;// P9: 2 x lxvx, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew //
179 ;vector int fromDiffMemConsAConvdtoi(ptr ptr) { //
180 ; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; //
181 ;} //
182 ;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
183 ;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
184 ;vector int fromDiffMemConsDConvdtoi(ptr ptr) { //
185 ; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //
186 ;} //
187 ;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
188 ;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
189 ;vector int fromDiffMemVarAConvdtoi(ptr arr, int elem) { //
190 ; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; //
191 ;} //
192 ;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
193 ;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
194 ;vector int fromDiffMemVarDConvdtoi(ptr arr, int elem) { //
195 ; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; //
196 ;} //
197 ;// P8: xscvdpsxws, xxspltw //
198 ;// P9: xscvdpsxws, xxspltw //
199 ;vector int spltRegValConvdtoi(double val) { //
200 ; return (vector int) val; //
201 ;} //
202 ;// P8: lxsdx, xscvdpsxws, xxspltw //
203 ;// P9: lxssp, xscvdpsxws, xxspltw //
204 ;vector int spltMemValConvdtoi(ptr ptr) { //
205 ; return (vector int)*ptr; //
206 ;} //
207 ;/*=================================== int ===================================*/
208 ;/*=============================== unsigned int ==============================*/
209 ;// P8: xxlxor //
210 ;// P9: xxlxor //
211 ;vector unsigned int allZeroui() { //
212 ; return (vector unsigned int)0; //
213 ;} //
214 ;// P8: vspltisb -1 //
215 ;// P9: xxspltisb 255 //
216 ;vector unsigned int spltConst1ui() { //
217 ; return (vector unsigned int)1; //
218 ;} //
219 ;// P8: vspltisw -15; vsrw //
220 ;// P9: vspltisw -15; vsrw //
221 ;vector unsigned int spltConst16kui() { //
222 ; return (vector unsigned int)((1<<15) - 1); //
223 ;} //
224 ;// P8: vspltisw -16; vsrw //
225 ;// P9: vspltisw -16; vsrw //
226 ;vector unsigned int spltConst32kui() { //
227 ; return (vector unsigned int)((1<<16) - 1); //
228 ;} //
229 ;// P8: 4 x mtvsrwz, 2 x xxmrghd, vmrgow //
230 ;// P9: 2 x mtvsrdd, vmrgow //
231 ;vector unsigned int fromRegsui(unsigned int a, unsigned int b, //
232 ; unsigned int c, unsigned int d) { //
233 ; return (vector unsigned int){ a, b, c, d }; //
234 ;} //
235 ;// P8: lxvd2x, xxswapd //
236 ;// P9: lxvx (or even lxv) //
237 ;vector unsigned int fromDiffConstsui() { //
238 ; return (vector unsigned int) { 242, -113, 889, 19 }; //
239 ;} //
240 ;// P8: lxvd2x, xxswapd //
241 ;// P9: lxvx //
242 ;vector unsigned int fromDiffMemConsAui(unsigned int *arr) { //
243 ; return (vector unsigned int) { arr[0], arr[1], arr[2], arr[3] }; //
244 ;} //
245 ;// P8: 2 x lxvd2x, 2 x xxswapd, vperm //
246 ;// P9: 2 x lxvx, vperm //
247 ;vector unsigned int fromDiffMemConsDui(unsigned int *arr) { //
248 ; return (vector unsigned int) { arr[3], arr[2], arr[1], arr[0] }; //
249 ;} //
250 ;// P8: sldi 2, lxvd2x, xxswapd //
251 ;// P9: sldi 2, lxvx //
252 ;vector unsigned int fromDiffMemVarAui(unsigned int *arr, int elem) { //
253 ; return (vector unsigned int) { arr[elem], arr[elem+1], //
254 ; arr[elem+2], arr[elem+3] }; //
255 ;} //
256 ;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm //
257 ;// P9: sldi 2, 2 x lxvx, vperm //
258 ;vector unsigned int fromDiffMemVarDui(unsigned int *arr, int elem) { //
259 ; return (vector unsigned int) { arr[elem], arr[elem-1], //
260 ; arr[elem-2], arr[elem-3] }; //
261 ;} //
262 ;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow //
263 ;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow //
264 ;vector unsigned int fromRandMemConsui(unsigned int *arr) { //
265 ; return (vector unsigned int) { arr[4], arr[18], arr[2], arr[88] }; //
266 ;} //
267 ;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow //
268 ;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow //
269 ;vector unsigned int fromRandMemVarui(unsigned int *arr, int elem) { //
270 ; return (vector unsigned int) { arr[elem+4], arr[elem+1], //
271 ; arr[elem+2], arr[elem+8] }; //
272 ;} //
273 ;// P8: mtvsrwz, xxspltw //
274 ;// P9: mtvsrws //
275 ;vector unsigned int spltRegValui(unsigned int val) { //
276 ; return (vector unsigned int) val; //
277 ;} //
278 ;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw //
279 ;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw //
280 ;vector unsigned int spltMemValui(unsigned int *ptr) { //
281 ; return (vector unsigned int)*ptr; //
282 ;} //
283 ;// P8: vspltisw //
284 ;// P9: vspltisw //
285 ;vector unsigned int spltCnstConvftoui() { //
286 ; return (vector unsigned int) 4.74f; //
287 ;} //
288 ;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
289 ;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
290 ;vector unsigned int fromRegsConvftoui(float a, float b, float c, float d) { //
291 ; return (vector unsigned int) { a, b, c, d }; //
292 ;} //
293 ;// P8: lxvd2x, xxswapd //
294 ;// P9: lxvx (even lxv) //
295 ;vector unsigned int fromDiffConstsConvftoui() { //
296 ; return (vector unsigned int) { 24.46f, 234.f, 988.19f, 422.39f }; //
297 ;} //
298 ;// P8: lxvd2x, xxswapd, xvcvspuxws //
299 ;// P9: lxvx, xvcvspuxws //
300 ;vector unsigned int fromDiffMemConsAConvftoui(ptr ptr) { //
301 ; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; //
302 ;} //
303 ;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspuxws //
304 ;// P9: 2 x lxvx, vperm, xvcvspuxws //
305 ;vector unsigned int fromDiffMemConsDConvftoui(ptr ptr) { //
306 ; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //
307 ;} //
308 ;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
309 ;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
310 ;// Note: if the consecutive loads learns to handle pre-inc, this can be: //
311 ;// sldi 2, load, xvcvspuxws //
312 ;vector unsigned int fromDiffMemVarAConvftoui(ptr arr, int elem) { //
313 ; return (vector unsigned int) { arr[elem], arr[elem+1], //
314 ; arr[elem+2], arr[elem+3] }; //
315 ;} //
316 ;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
317 ;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
318 ;// Note: if the consecutive loads learns to handle pre-inc, this can be: //
319 ;// sldi 2, 2 x load, vperm, xvcvspuxws //
320 ;vector unsigned int fromDiffMemVarDConvftoui(ptr arr, int elem) { //
321 ; return (vector unsigned int) { arr[elem], arr[elem-1], //
322 ; arr[elem-2], arr[elem-3] }; //
323 ;} //
324 ;// P8: xscvdpuxws, xxspltw //
325 ;// P9: xscvdpuxws, xxspltw //
326 ;vector unsigned int spltRegValConvftoui(float val) { //
327 ; return (vector unsigned int) val; //
328 ;} //
329 ;// P8: lxsspx, xscvdpuxws, xxspltw //
330 ;// P9: lxvwsx, xvcvspuxws //
331 ;vector unsigned int spltMemValConvftoui(ptr ptr) { //
332 ; return (vector unsigned int)*ptr; //
333 ;} //
334 ;// P8: vspltisw //
335 ;// P9: vspltisw //
336 ;vector unsigned int spltCnstConvdtoui() { //
337 ; return (vector unsigned int) 4.74; //
338 ;} //
339 ;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
340 ;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
341 ;vector unsigned int fromRegsConvdtoui(double a, double b, //
342 ; double c, double d) { //
343 ; return (vector unsigned int) { a, b, c, d }; //
344 ;} //
345 ;// P8: lxvd2x, xxswapd //
346 ;// P9: lxvx (even lxv) //
347 ;vector unsigned int fromDiffConstsConvdtoui() { //
348 ; return (vector unsigned int) { 24.46, 234., 988.19, 422.39 }; //
349 ;} //
350 ;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew //
351 ;// P9: 2 x lxvx, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew //
352 ;vector unsigned int fromDiffMemConsAConvdtoui(ptr ptr) { //
353 ; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; //
354 ;} //
355 ;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
356 ;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
357 ;vector unsigned int fromDiffMemConsDConvdtoui(ptr ptr) { //
358 ; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //
359 ;} //
360 ;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
361 ;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
362 ;vector unsigned int fromDiffMemVarAConvdtoui(ptr arr, int elem) { //
363 ; return (vector unsigned int) { arr[elem], arr[elem+1], //
364 ; arr[elem+2], arr[elem+3] }; //
365 ;} //
366 ;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
367 ;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
368 ;vector unsigned int fromDiffMemVarDConvdtoui(ptr arr, int elem) { //
369 ; return (vector unsigned int) { arr[elem], arr[elem-1], //
370 ; arr[elem-2], arr[elem-3] }; //
371 ;} //
372 ;// P8: xscvdpuxws, xxspltw //
373 ;// P9: xscvdpuxws, xxspltw //
374 ;vector unsigned int spltRegValConvdtoui(double val) { //
375 ; return (vector unsigned int) val; //
376 ;} //
377 ;// P8: lxsspx, xscvdpuxws, xxspltw //
378 ;// P9: lfd, xscvdpuxws, xxspltw //
379 ;vector unsigned int spltMemValConvdtoui(ptr ptr) { //
380 ; return (vector unsigned int)*ptr; //
381 ;} //
382 ;/*=============================== unsigned int ==============================*/
383 ;/*=============================== long long =================================*/
384 ;// P8: xxlxor //
385 ;// P9: xxlxor //
386 ;vector long long allZeroll() { //
387 ; return (vector long long)0; //
388 ;} //
389 ;// P8: vspltisb -1 //
390 ;// P9: xxspltisb 255 //
391 ;vector long long spltConst1ll() { //
392 ; return (vector long long)1; //
393 ;} //
394 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
395 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
396 ;vector long long spltConst16kll() { //
397 ; return (vector long long)((1<<15) - 1); //
398 ;} //
399 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
400 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
401 ;vector long long spltConst32kll() { //
402 ; return (vector long long)((1<<16) - 1); //
403 ;} //
404 ;// P8: 2 x mtvsrd, xxmrghd //
405 ;// P9: mtvsrdd //
406 ;vector long long fromRegsll(long long a, long long b) { //
407 ; return (vector long long){ a, b }; //
408 ;} //
409 ;// P8: lxvd2x, xxswapd //
410 ;// P9: lxvx (or even lxv) //
411 ;vector long long fromDiffConstsll() { //
412 ; return (vector long long) { 242, -113 }; //
413 ;} //
414 ;// P8: lxvd2x, xxswapd //
415 ;// P9: lxvx //
416 ;vector long long fromDiffMemConsAll(long long *arr) { //
417 ; return (vector long long) { arr[0], arr[1] }; //
418 ;} //
419 ;// P8: lxvd2x //
420 ;// P9: lxvx, xxswapd (maybe just use lxvd2x) //
421 ;vector long long fromDiffMemConsDll(long long *arr) { //
422 ; return (vector long long) { arr[3], arr[2] }; //
423 ;} //
424 ;// P8: sldi 3, lxvd2x, xxswapd //
425 ;// P9: sldi 3, lxvx //
426 ;vector long long fromDiffMemVarAll(long long *arr, int elem) { //
427 ; return (vector long long) { arr[elem], arr[elem+1] }; //
428 ;} //
429 ;// P8: sldi 3, lxvd2x //
430 ;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) //
431 ;vector long long fromDiffMemVarDll(long long *arr, int elem) { //
432 ; return (vector long long) { arr[elem], arr[elem-1] }; //
433 ;} //
434 ;// P8: 2 x ld, 2 x mtvsrd, xxmrghd //
435 ;// P9: 2 x ld, mtvsrdd //
436 ;vector long long fromRandMemConsll(long long *arr) { //
437 ; return (vector long long) { arr[4], arr[18] }; //
438 ;} //
439 ;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd //
440 ;// P9: sldi 3, add, 2 x ld, mtvsrdd //
441 ;vector long long fromRandMemVarll(long long *arr, int elem) { //
442 ; return (vector long long) { arr[elem+4], arr[elem+1] }; //
443 ;} //
444 ;// P8: mtvsrd, xxspltd //
445 ;// P9: mtvsrdd //
446 ;vector long long spltRegValll(long long val) { //
447 ; return (vector long long) val; //
448 ;} //
449 ;// P8: lxvdsx //
450 ;// P9: lxvdsx //
451 ;vector long long spltMemValll(long long *ptr) { //
452 ; return (vector long long)*ptr; //
453 ;} //
454 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
455 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
456 ;vector long long spltCnstConvftoll() { //
457 ; return (vector long long) 4.74f; //
458 ;} //
459 ;// P8: xxmrghd, xvcvdpsxds //
460 ;// P9: xxmrghd, xvcvdpsxds //
461 ;vector long long fromRegsConvftoll(float a, float b) { //
462 ; return (vector long long) { a, b }; //
463 ;} //
464 ;// P8: lxvd2x, xxswapd //
465 ;// P9: lxvx (even lxv) //
466 ;vector long long fromDiffConstsConvftoll() { //
467 ; return (vector long long) { 24.46f, 234.f }; //
468 ;} //
469 ;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds //
470 ;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds //
471 ;vector long long fromDiffMemConsAConvftoll(ptr ptr) { //
472 ; return (vector long long) { ptr[0], ptr[1] }; //
473 ;} //
474 ;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds //
475 ;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds //
476 ;vector long long fromDiffMemConsDConvftoll(ptr ptr) { //
477 ; return (vector long long) { ptr[3], ptr[2] }; //
478 ;} //
479 ;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds //
480 ;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds //
481 ;vector long long fromDiffMemVarAConvftoll(ptr arr, int elem) { //
482 ; return (vector long long) { arr[elem], arr[elem+1] }; //
483 ;} //
484 ;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds //
485 ;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds //
486 ;vector long long fromDiffMemVarDConvftoll(ptr arr, int elem) { //
487 ; return (vector long long) { arr[elem], arr[elem-1] }; //
488 ;} //
489 ;// P8: xscvdpsxds, xxspltd //
490 ;// P9: xscvdpsxds, xxspltd //
491 ;vector long long spltRegValConvftoll(float val) { //
492 ; return (vector long long) val; //
493 ;} //
494 ;// P8: lxsspx, xscvdpsxds, xxspltd //
495 ;// P9: lfs, xscvdpsxds, xxspltd //
496 ;vector long long spltMemValConvftoll(ptr ptr) { //
497 ; return (vector long long)*ptr; //
498 ;} //
499 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
500 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
501 ;vector long long spltCnstConvdtoll() { //
502 ; return (vector long long) 4.74; //
503 ;} //
504 ;// P8: xxmrghd, xvcvdpsxds //
505 ;// P9: xxmrghd, xvcvdpsxds //
506 ;vector long long fromRegsConvdtoll(double a, double b) { //
507 ; return (vector long long) { a, b }; //
508 ;} //
509 ;// P8: lxvd2x, xxswapd //
510 ;// P9: lxvx (even lxv) //
511 ;vector long long fromDiffConstsConvdtoll() { //
512 ; return (vector long long) { 24.46, 234. }; //
513 ;} //
514 ;// P8: lxvd2x, xxswapd, xvcvdpsxds //
515 ;// P9: lxvx, xvcvdpsxds //
516 ;vector long long fromDiffMemConsAConvdtoll(ptr ptr) { //
517 ; return (vector long long) { ptr[0], ptr[1] }; //
518 ;} //
519 ;// P8: lxvd2x, xvcvdpsxds //
520 ;// P9: lxvx, xxswapd, xvcvdpsxds //
521 ;vector long long fromDiffMemConsDConvdtoll(ptr ptr) { //
522 ; return (vector long long) { ptr[3], ptr[2] }; //
523 ;} //
524 ;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpsxds //
525 ;// P9: sldi 3, lxvx, xvcvdpsxds //
526 ;vector long long fromDiffMemVarAConvdtoll(ptr arr, int elem) { //
527 ; return (vector long long) { arr[elem], arr[elem+1] }; //
528 ;} //
529 ;// P8: sldi 3, lxvd2x, xvcvdpsxds //
530 ;// P9: sldi 3, lxvx, xxswapd, xvcvdpsxds //
531 ;vector long long fromDiffMemVarDConvdtoll(ptr arr, int elem) { //
532 ; return (vector long long) { arr[elem], arr[elem-1] }; //
533 ;} //
534 ;// P8: xscvdpsxds, xxspltd //
535 ;// P9: xscvdpsxds, xxspltd //
536 ;vector long long spltRegValConvdtoll(double val) { //
537 ; return (vector long long) val; //
538 ;} //
539 ;// P8: lxvdsx, xvcvdpsxds //
540 ;// P9: lxvdsx, xvcvdpsxds //
541 ;vector long long spltMemValConvdtoll(ptr ptr) { //
542 ; return (vector long long)*ptr; //
543 ;} //
544 ;/*=============================== long long =================================*/
545 ;/*========================== unsigned long long =============================*/
546 ;// P8: xxlxor //
547 ;// P9: xxlxor //
548 ;vector unsigned long long allZeroull() { //
549 ; return (vector unsigned long long)0; //
550 ;} //
551 ;// P8: vspltisb -1 //
552 ;// P9: xxspltisb 255 //
553 ;vector unsigned long long spltConst1ull() { //
554 ; return (vector unsigned long long)1; //
555 ;} //
556 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
557 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
558 ;vector unsigned long long spltConst16kull() { //
559 ; return (vector unsigned long long)((1<<15) - 1); //
560 ;} //
561 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
562 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
563 ;vector unsigned long long spltConst32kull() { //
564 ; return (vector unsigned long long)((1<<16) - 1); //
565 ;} //
566 ;// P8: 2 x mtvsrd, xxmrghd //
567 ;// P9: mtvsrdd //
568 ;vector unsigned long long fromRegsull(unsigned long long a, //
569 ; unsigned long long b) { //
570 ; return (vector unsigned long long){ a, b }; //
571 ;} //
572 ;// P8: lxvd2x, xxswapd //
573 ;// P9: lxvx (or even lxv) //
574 ;vector unsigned long long fromDiffConstsull() { //
575 ; return (vector unsigned long long) { 242, -113 }; //
576 ;} //
577 ;// P8: lxvd2x, xxswapd //
578 ;// P9: lxvx //
579 ;vector unsigned long long fromDiffMemConsAull(unsigned long long *arr) { //
580 ; return (vector unsigned long long) { arr[0], arr[1] }; //
581 ;} //
582 ;// P8: lxvd2x //
583 ;// P9: lxvx, xxswapd (maybe just use lxvd2x) //
584 ;vector unsigned long long fromDiffMemConsDull(unsigned long long *arr) { //
585 ; return (vector unsigned long long) { arr[3], arr[2] }; //
586 ;} //
587 ;// P8: sldi 3, lxvd2x, xxswapd //
588 ;// P9: sldi 3, lxvx //
589 ;vector unsigned long long fromDiffMemVarAull(unsigned long long *arr, //
590 ; int elem) { //
591 ; return (vector unsigned long long) { arr[elem], arr[elem+1] }; //
592 ;} //
593 ;// P8: sldi 3, lxvd2x //
594 ;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) //
595 ;vector unsigned long long fromDiffMemVarDull(unsigned long long *arr, //
596 ; int elem) { //
597 ; return (vector unsigned long long) { arr[elem], arr[elem-1] }; //
598 ;} //
599 ;// P8: 2 x ld, 2 x mtvsrd, xxmrghd //
600 ;// P9: 2 x ld, mtvsrdd //
601 ;vector unsigned long long fromRandMemConsull(unsigned long long *arr) { //
602 ; return (vector unsigned long long) { arr[4], arr[18] }; //
603 ;} //
604 ;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd //
605 ;// P9: sldi 3, add, 2 x ld, mtvsrdd //
606 ;vector unsigned long long fromRandMemVarull(unsigned long long *arr, //
607 ; int elem) { //
608 ; return (vector unsigned long long) { arr[elem+4], arr[elem+1] }; //
609 ;} //
610 ;// P8: mtvsrd, xxspltd //
611 ;// P9: mtvsrdd //
612 ;vector unsigned long long spltRegValull(unsigned long long val) { //
613 ; return (vector unsigned long long) val; //
614 ;} //
615 ;// P8: lxvdsx //
616 ;// P9: lxvdsx //
617 ;vector unsigned long long spltMemValull(unsigned long long *ptr) { //
618 ; return (vector unsigned long long)*ptr; //
619 ;} //
620 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
621 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
622 ;vector unsigned long long spltCnstConvftoull() { //
623 ; return (vector unsigned long long) 4.74f; //
624 ;} //
625 ;// P8: xxmrghd, xvcvdpuxds //
626 ;// P9: xxmrghd, xvcvdpuxds //
627 ;vector unsigned long long fromRegsConvftoull(float a, float b) { //
628 ; return (vector unsigned long long) { a, b }; //
629 ;} //
630 ;// P8: lxvd2x, xxswapd //
631 ;// P9: lxvx (even lxv) //
632 ;vector unsigned long long fromDiffConstsConvftoull() { //
633 ; return (vector unsigned long long) { 24.46f, 234.f }; //
634 ;} //
635 ;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds //
636 ;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds //
637 ;vector unsigned long long fromDiffMemConsAConvftoull(ptr ptr) { //
638 ; return (vector unsigned long long) { ptr[0], ptr[1] }; //
639 ;} //
640 ;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds //
641 ;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds //
642 ;vector unsigned long long fromDiffMemConsDConvftoull(ptr ptr) { //
643 ; return (vector unsigned long long) { ptr[3], ptr[2] }; //
644 ;} //
645 ;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds //
646 ;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds //
647 ;vector unsigned long long fromDiffMemVarAConvftoull(ptr arr, int elem) { //
648 ; return (vector unsigned long long) { arr[elem], arr[elem+1] }; //
649 ;} //
650 ;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds //
651 ;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds //
652 ;vector unsigned long long fromDiffMemVarDConvftoull(ptr arr, int elem) { //
653 ; return (vector unsigned long long) { arr[elem], arr[elem-1] }; //
654 ;} //
655 ;// P8: xscvdpuxds, xxspltd //
656 ;// P9: xscvdpuxds, xxspltd //
657 ;vector unsigned long long spltRegValConvftoull(float val) { //
658 ; return (vector unsigned long long) val; //
659 ;} //
660 ;// P8: lxsspx, xscvdpuxds, xxspltd //
661 ;// P9: lfs, xscvdpuxds, xxspltd //
662 ;vector unsigned long long spltMemValConvftoull(ptr ptr) { //
663 ; return (vector unsigned long long)*ptr; //
664 ;} //
665 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
666 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
667 ;vector unsigned long long spltCnstConvdtoull() { //
668 ; return (vector unsigned long long) 4.74; //
669 ;} //
670 ;// P8: xxmrghd, xvcvdpuxds //
671 ;// P9: xxmrghd, xvcvdpuxds //
672 ;vector unsigned long long fromRegsConvdtoull(double a, double b) { //
673 ; return (vector unsigned long long) { a, b }; //
674 ;} //
675 ;// P8: lxvd2x, xxswapd //
676 ;// P9: lxvx (even lxv) //
677 ;vector unsigned long long fromDiffConstsConvdtoull() { //
678 ; return (vector unsigned long long) { 24.46, 234. }; //
679 ;} //
680 ;// P8: lxvd2x, xxswapd, xvcvdpuxds //
681 ;// P9: lxvx, xvcvdpuxds //
682 ;vector unsigned long long fromDiffMemConsAConvdtoull(ptr ptr) { //
683 ; return (vector unsigned long long) { ptr[0], ptr[1] }; //
684 ;} //
685 ;// P8: lxvd2x, xvcvdpuxds //
686 ;// P9: lxvx, xxswapd, xvcvdpuxds //
687 ;vector unsigned long long fromDiffMemConsDConvdtoull(ptr ptr) { //
688 ; return (vector unsigned long long) { ptr[3], ptr[2] }; //
689 ;} //
690 ;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpuxds //
691 ;// P9: sldi 3, lxvx, xvcvdpuxds //
692 ;vector unsigned long long fromDiffMemVarAConvdtoull(ptr arr, int elem) { //
693 ; return (vector unsigned long long) { arr[elem], arr[elem+1] }; //
694 ;} //
695 ;// P8: sldi 3, lxvd2x, xvcvdpuxds //
696 ;// P9: sldi 3, lxvx, xxswapd, xvcvdpuxds //
697 ;vector unsigned long long fromDiffMemVarDConvdtoull(ptr arr, int elem) { //
698 ; return (vector unsigned long long) { arr[elem], arr[elem-1] }; //
699 ;} //
700 ;// P8: xscvdpuxds, xxspltd //
701 ;// P9: xscvdpuxds, xxspltd //
702 ;vector unsigned long long spltRegValConvdtoull(double val) { //
703 ; return (vector unsigned long long) val; //
704 ;} //
705 ;// P8: lxvdsx, xvcvdpuxds //
706 ;// P9: lxvdsx, xvcvdpuxds //
707 ;vector unsigned long long spltMemValConvdtoull(ptr ptr) { //
708 ; return (vector unsigned long long)*ptr; //
709 ;} //
710 ;/*========================== unsigned long long ==============================*/
712 define <4 x i32> @allZeroi() {
713 ; P9BE-LABEL: allZeroi:
714 ; P9BE: # %bb.0: # %entry
715 ; P9BE-NEXT: xxlxor v2, v2, v2
716 ; P9BE-NEXT: blr
717 ;
718 ; P9LE-LABEL: allZeroi:
719 ; P9LE: # %bb.0: # %entry
720 ; P9LE-NEXT: xxlxor v2, v2, v2
721 ; P9LE-NEXT: blr
722 ;
723 ; P8BE-LABEL: allZeroi:
724 ; P8BE: # %bb.0: # %entry
725 ; P8BE-NEXT: xxlxor v2, v2, v2
726 ; P8BE-NEXT: blr
727 ;
728 ; P8LE-LABEL: allZeroi:
729 ; P8LE: # %bb.0: # %entry
730 ; P8LE-NEXT: xxlxor v2, v2, v2
731 ; P8LE-NEXT: blr
732 entry:
733 ret <4 x i32> zeroinitializer
734 }
736 define <4 x i32> @spltConst1i() {
737 ; P9BE-LABEL: spltConst1i:
738 ; P9BE: # %bb.0: # %entry
739 ; P9BE-NEXT: vspltisw v2, 1
740 ; P9BE-NEXT: blr
741 ;
742 ; P9LE-LABEL: spltConst1i:
743 ; P9LE: # %bb.0: # %entry
744 ; P9LE-NEXT: vspltisw v2, 1
745 ; P9LE-NEXT: blr
746 ;
747 ; P8BE-LABEL: spltConst1i:
748 ; P8BE: # %bb.0: # %entry
749 ; P8BE-NEXT: vspltisw v2, 1
750 ; P8BE-NEXT: blr
751 ;
752 ; P8LE-LABEL: spltConst1i:
753 ; P8LE: # %bb.0: # %entry
754 ; P8LE-NEXT: vspltisw v2, 1
755 ; P8LE-NEXT: blr
756 entry:
757 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1>
758 }
760 define <4 x i32> @spltConst16ki() {
761 ; P9BE-LABEL: spltConst16ki:
762 ; P9BE: # %bb.0: # %entry
763 ; P9BE-NEXT: vspltisw v2, -15
764 ; P9BE-NEXT: vsrw v2, v2, v2
765 ; P9BE-NEXT: blr
766 ;
767 ; P9LE-LABEL: spltConst16ki:
768 ; P9LE: # %bb.0: # %entry
769 ; P9LE-NEXT: vspltisw v2, -15
770 ; P9LE-NEXT: vsrw v2, v2, v2
771 ; P9LE-NEXT: blr
772 ;
773 ; P8BE-LABEL: spltConst16ki:
774 ; P8BE: # %bb.0: # %entry
775 ; P8BE-NEXT: vspltisw v2, -15
776 ; P8BE-NEXT: vsrw v2, v2, v2
777 ; P8BE-NEXT: blr
778 ;
779 ; P8LE-LABEL: spltConst16ki:
780 ; P8LE: # %bb.0: # %entry
781 ; P8LE-NEXT: vspltisw v2, -15
782 ; P8LE-NEXT: vsrw v2, v2, v2
783 ; P8LE-NEXT: blr
784 entry:
785 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
786 }
788 define <4 x i32> @spltConst32ki() {
789 ; P9BE-LABEL: spltConst32ki:
790 ; P9BE: # %bb.0: # %entry
791 ; P9BE-NEXT: vspltisw v2, -16
792 ; P9BE-NEXT: vsrw v2, v2, v2
793 ; P9BE-NEXT: blr
794 ;
795 ; P9LE-LABEL: spltConst32ki:
796 ; P9LE: # %bb.0: # %entry
797 ; P9LE-NEXT: vspltisw v2, -16
798 ; P9LE-NEXT: vsrw v2, v2, v2
799 ; P9LE-NEXT: blr
800 ;
801 ; P8BE-LABEL: spltConst32ki:
802 ; P8BE: # %bb.0: # %entry
803 ; P8BE-NEXT: vspltisw v2, -16
804 ; P8BE-NEXT: vsrw v2, v2, v2
805 ; P8BE-NEXT: blr
806 ;
807 ; P8LE-LABEL: spltConst32ki:
808 ; P8LE: # %bb.0: # %entry
809 ; P8LE-NEXT: vspltisw v2, -16
810 ; P8LE-NEXT: vsrw v2, v2, v2
811 ; P8LE-NEXT: blr
812 entry:
813 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
814 }
816 define <4 x i32> @fromRegsi(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) {
817 ; P9BE-LABEL: fromRegsi:
818 ; P9BE: # %bb.0: # %entry
819 ; P9BE-NEXT: rldimi r6, r5, 32, 0
820 ; P9BE-NEXT: rldimi r4, r3, 32, 0
821 ; P9BE-NEXT: mtvsrdd v2, r4, r6
822 ; P9BE-NEXT: blr
823 ;
824 ; P9LE-LABEL: fromRegsi:
825 ; P9LE: # %bb.0: # %entry
826 ; P9LE-NEXT: rldimi r3, r4, 32, 0
827 ; P9LE-NEXT: rldimi r5, r6, 32, 0
828 ; P9LE-NEXT: mtvsrdd v2, r5, r3
829 ; P9LE-NEXT: blr
830 ;
831 ; P8BE-LABEL: fromRegsi:
832 ; P8BE: # %bb.0: # %entry
833 ; P8BE-NEXT: rldimi r6, r5, 32, 0
834 ; P8BE-NEXT: rldimi r4, r3, 32, 0
835 ; P8BE-NEXT: mtfprd f0, r6
836 ; P8BE-NEXT: mtfprd f1, r4
837 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
838 ; P8BE-NEXT: blr
839 ;
840 ; P8LE-LABEL: fromRegsi:
841 ; P8LE: # %bb.0: # %entry
842 ; P8LE-NEXT: rldimi r3, r4, 32, 0
843 ; P8LE-NEXT: rldimi r5, r6, 32, 0
844 ; P8LE-NEXT: mtfprd f0, r3
845 ; P8LE-NEXT: mtfprd f1, r5
846 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
847 ; P8LE-NEXT: blr
848 entry:
849 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0
850 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
851 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2
852 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3
853 ret <4 x i32> %vecinit3
854 }
856 define <4 x i32> @fromDiffConstsi() {
857 ; P9BE-LABEL: fromDiffConstsi:
858 ; P9BE: # %bb.0: # %entry
859 ; P9BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha
860 ; P9BE-NEXT: addi r3, r3, .LCPI5_0@toc@l
861 ; P9BE-NEXT: lxv v2, 0(r3)
862 ; P9BE-NEXT: blr
863 ;
864 ; P9LE-LABEL: fromDiffConstsi:
865 ; P9LE: # %bb.0: # %entry
866 ; P9LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha
867 ; P9LE-NEXT: addi r3, r3, .LCPI5_0@toc@l
868 ; P9LE-NEXT: lxv v2, 0(r3)
869 ; P9LE-NEXT: blr
870 ;
871 ; P8BE-LABEL: fromDiffConstsi:
872 ; P8BE: # %bb.0: # %entry
873 ; P8BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha
874 ; P8BE-NEXT: addi r3, r3, .LCPI5_0@toc@l
875 ; P8BE-NEXT: lxvw4x v2, 0, r3
876 ; P8BE-NEXT: blr
877 ;
878 ; P8LE-LABEL: fromDiffConstsi:
879 ; P8LE: # %bb.0: # %entry
880 ; P8LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha
881 ; P8LE-NEXT: addi r3, r3, .LCPI5_0@toc@l
882 ; P8LE-NEXT: lxvd2x vs0, 0, r3
883 ; P8LE-NEXT: xxswapd v2, vs0
884 ; P8LE-NEXT: blr
885 entry:
886 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19>
887 }
889 define <4 x i32> @fromDiffMemConsAi(ptr nocapture readonly %arr) {
890 ; P9BE-LABEL: fromDiffMemConsAi:
891 ; P9BE: # %bb.0: # %entry
892 ; P9BE-NEXT: lxv v2, 0(r3)
893 ; P9BE-NEXT: blr
894 ;
895 ; P9LE-LABEL: fromDiffMemConsAi:
896 ; P9LE: # %bb.0: # %entry
897 ; P9LE-NEXT: lxv v2, 0(r3)
898 ; P9LE-NEXT: blr
899 ;
900 ; P8BE-LABEL: fromDiffMemConsAi:
901 ; P8BE: # %bb.0: # %entry
902 ; P8BE-NEXT: lxvw4x v2, 0, r3
903 ; P8BE-NEXT: blr
904 ;
905 ; P8LE-LABEL: fromDiffMemConsAi:
906 ; P8LE: # %bb.0: # %entry
907 ; P8LE-NEXT: lxvd2x vs0, 0, r3
908 ; P8LE-NEXT: xxswapd v2, vs0
909 ; P8LE-NEXT: blr
910 entry:
911 %0 = load i32, ptr %arr, align 4
912 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
913 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 1
914 %1 = load i32, ptr %arrayidx1, align 4
915 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
916 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 2
917 %2 = load i32, ptr %arrayidx3, align 4
918 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
919 %arrayidx5 = getelementptr inbounds i32, ptr %arr, i64 3
920 %3 = load i32, ptr %arrayidx5, align 4
921 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
922 ret <4 x i32> %vecinit6
923 }
925 define <4 x i32> @fromDiffMemConsDi(ptr nocapture readonly %arr) {
926 ; P9BE-LABEL: fromDiffMemConsDi:
927 ; P9BE: # %bb.0: # %entry
928 ; P9BE-NEXT: lxv v2, 0(r3)
929 ; P9BE-NEXT: addis r3, r2, .LCPI7_0@toc@ha
930 ; P9BE-NEXT: addi r3, r3, .LCPI7_0@toc@l
931 ; P9BE-NEXT: lxv vs0, 0(r3)
932 ; P9BE-NEXT: xxperm v2, v2, vs0
933 ; P9BE-NEXT: blr
934 ;
935 ; P9LE-LABEL: fromDiffMemConsDi:
936 ; P9LE: # %bb.0: # %entry
937 ; P9LE-NEXT: lxvw4x v2, 0, r3
938 ; P9LE-NEXT: blr
939 ;
940 ; P8BE-LABEL: fromDiffMemConsDi:
941 ; P8BE: # %bb.0: # %entry
942 ; P8BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha
943 ; P8BE-NEXT: lxvw4x v2, 0, r3
944 ; P8BE-NEXT: addi r4, r4, .LCPI7_0@toc@l
945 ; P8BE-NEXT: lxvw4x v3, 0, r4
946 ; P8BE-NEXT: vperm v2, v2, v2, v3
947 ; P8BE-NEXT: blr
948 ;
949 ; P8LE-LABEL: fromDiffMemConsDi:
950 ; P8LE: # %bb.0: # %entry
951 ; P8LE-NEXT: addis r4, r2, .LCPI7_0@toc@ha
952 ; P8LE-NEXT: lxvd2x vs0, 0, r3
953 ; P8LE-NEXT: addi r4, r4, .LCPI7_0@toc@l
954 ; P8LE-NEXT: lxvd2x vs1, 0, r4
955 ; P8LE-NEXT: xxswapd v2, vs0
956 ; P8LE-NEXT: xxswapd v3, vs1
957 ; P8LE-NEXT: vperm v2, v2, v2, v3
958 ; P8LE-NEXT: blr
959 entry:
960 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 3
961 %0 = load i32, ptr %arrayidx, align 4
962 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
963 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 2
964 %1 = load i32, ptr %arrayidx1, align 4
965 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
966 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 1
967 %2 = load i32, ptr %arrayidx3, align 4
968 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
969 %3 = load i32, ptr %arr, align 4
970 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
971 ret <4 x i32> %vecinit6
972 }
974 define <4 x i32> @fromDiffMemVarAi(ptr nocapture readonly %arr, i32 signext %elem) {
975 ; P9BE-LABEL: fromDiffMemVarAi:
976 ; P9BE: # %bb.0: # %entry
977 ; P9BE-NEXT: sldi r4, r4, 2
978 ; P9BE-NEXT: lxvx v2, r3, r4
979 ; P9BE-NEXT: blr
980 ;
981 ; P9LE-LABEL: fromDiffMemVarAi:
982 ; P9LE: # %bb.0: # %entry
983 ; P9LE-NEXT: sldi r4, r4, 2
984 ; P9LE-NEXT: lxvx v2, r3, r4
985 ; P9LE-NEXT: blr
986 ;
987 ; P8BE-LABEL: fromDiffMemVarAi:
988 ; P8BE: # %bb.0: # %entry
989 ; P8BE-NEXT: sldi r4, r4, 2
990 ; P8BE-NEXT: lxvw4x v2, r3, r4
991 ; P8BE-NEXT: blr
992 ;
993 ; P8LE-LABEL: fromDiffMemVarAi:
994 ; P8LE: # %bb.0: # %entry
995 ; P8LE-NEXT: sldi r4, r4, 2
996 ; P8LE-NEXT: lxvd2x vs0, r3, r4
997 ; P8LE-NEXT: xxswapd v2, vs0
998 ; P8LE-NEXT: blr
999 entry:
1000 %idxprom = sext i32 %elem to i64
1001 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom
1002 %0 = load i32, ptr %arrayidx, align 4
1003 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
1004 %add = add nsw i32 %elem, 1
1005 %idxprom1 = sext i32 %add to i64
1006 %arrayidx2 = getelementptr inbounds i32, ptr %arr, i64 %idxprom1
1007 %1 = load i32, ptr %arrayidx2, align 4
1008 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
1009 %add4 = add nsw i32 %elem, 2
1010 %idxprom5 = sext i32 %add4 to i64
1011 %arrayidx6 = getelementptr inbounds i32, ptr %arr, i64 %idxprom5
1012 %2 = load i32, ptr %arrayidx6, align 4
1013 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2
1014 %add8 = add nsw i32 %elem, 3
1015 %idxprom9 = sext i32 %add8 to i64
1016 %arrayidx10 = getelementptr inbounds i32, ptr %arr, i64 %idxprom9
1017 %3 = load i32, ptr %arrayidx10, align 4
1018 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3
1019 ret <4 x i32> %vecinit11
1020 }
1022 define <4 x i32> @fromDiffMemVarDi(ptr nocapture readonly %arr, i32 signext %elem) {
1023 ; P9BE-LABEL: fromDiffMemVarDi:
1024 ; P9BE: # %bb.0: # %entry
1025 ; P9BE-NEXT: sldi r4, r4, 2
1026 ; P9BE-NEXT: add r3, r3, r4
1027 ; P9BE-NEXT: li r4, -12
1028 ; P9BE-NEXT: lxvx v2, r3, r4
1029 ; P9BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha
1030 ; P9BE-NEXT: addi r3, r3, .LCPI9_0@toc@l
1031 ; P9BE-NEXT: lxv vs0, 0(r3)
1032 ; P9BE-NEXT: xxperm v2, v2, vs0
1033 ; P9BE-NEXT: blr
1034 ;
1035 ; P9LE-LABEL: fromDiffMemVarDi:
1036 ; P9LE: # %bb.0: # %entry
1037 ; P9LE-NEXT: sldi r4, r4, 2
1038 ; P9LE-NEXT: add r3, r3, r4
1039 ; P9LE-NEXT: li r4, -12
1040 ; P9LE-NEXT: lxvx v2, r3, r4
1041 ; P9LE-NEXT: addis r3, r2, .LCPI9_0@toc@ha
1042 ; P9LE-NEXT: addi r3, r3, .LCPI9_0@toc@l
1043 ; P9LE-NEXT: lxv vs0, 0(r3)
1044 ; P9LE-NEXT: xxperm v2, v2, vs0
1045 ; P9LE-NEXT: blr
1046 ;
1047 ; P8BE-LABEL: fromDiffMemVarDi:
1048 ; P8BE: # %bb.0: # %entry
1049 ; P8BE-NEXT: sldi r4, r4, 2
1050 ; P8BE-NEXT: addis r5, r2, .LCPI9_0@toc@ha
1051 ; P8BE-NEXT: add r3, r3, r4
1052 ; P8BE-NEXT: addi r4, r5, .LCPI9_0@toc@l
1053 ; P8BE-NEXT: addi r3, r3, -12
1054 ; P8BE-NEXT: lxvw4x v3, 0, r4
1055 ; P8BE-NEXT: lxvw4x v2, 0, r3
1056 ; P8BE-NEXT: vperm v2, v2, v2, v3
1057 ; P8BE-NEXT: blr
1058 ;
1059 ; P8LE-LABEL: fromDiffMemVarDi:
1060 ; P8LE: # %bb.0: # %entry
1061 ; P8LE-NEXT: sldi r4, r4, 2
1062 ; P8LE-NEXT: addis r5, r2, .LCPI9_0@toc@ha
1063 ; P8LE-NEXT: add r3, r3, r4
1064 ; P8LE-NEXT: addi r4, r5, .LCPI9_0@toc@l
1065 ; P8LE-NEXT: addi r3, r3, -12
1066 ; P8LE-NEXT: lxvd2x vs1, 0, r4
1067 ; P8LE-NEXT: lxvd2x vs0, 0, r3
1068 ; P8LE-NEXT: xxswapd v3, vs1
1069 ; P8LE-NEXT: xxswapd v2, vs0
1070 ; P8LE-NEXT: vperm v2, v2, v2, v3
1071 ; P8LE-NEXT: blr
1072 entry:
1073 %idxprom = sext i32 %elem to i64
1074 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom
1075 %0 = load i32, ptr %arrayidx, align 4
1076 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
1077 %sub = add nsw i32 %elem, -1
1078 %idxprom1 = sext i32 %sub to i64
1079 %arrayidx2 = getelementptr inbounds i32, ptr %arr, i64 %idxprom1
1080 %1 = load i32, ptr %arrayidx2, align 4
1081 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
1082 %sub4 = add nsw i32 %elem, -2
1083 %idxprom5 = sext i32 %sub4 to i64
1084 %arrayidx6 = getelementptr inbounds i32, ptr %arr, i64 %idxprom5
1085 %2 = load i32, ptr %arrayidx6, align 4
1086 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2
1087 %sub8 = add nsw i32 %elem, -3
1088 %idxprom9 = sext i32 %sub8 to i64
1089 %arrayidx10 = getelementptr inbounds i32, ptr %arr, i64 %idxprom9
1090 %3 = load i32, ptr %arrayidx10, align 4
1091 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3
1092 ret <4 x i32> %vecinit11
1093 }
1095 define <4 x i32> @fromRandMemConsi(ptr nocapture readonly %arr) {
1096 ; P9BE-LABEL: fromRandMemConsi:
1097 ; P9BE: # %bb.0: # %entry
1098 ; P9BE-NEXT: lwz r4, 16(r3)
1099 ; P9BE-NEXT: lwz r5, 72(r3)
1100 ; P9BE-NEXT: lwz r6, 8(r3)
1101 ; P9BE-NEXT: lwz r3, 352(r3)
1102 ; P9BE-NEXT: rldimi r3, r6, 32, 0
1103 ; P9BE-NEXT: rldimi r5, r4, 32, 0
1104 ; P9BE-NEXT: mtvsrdd v2, r5, r3
1105 ; P9BE-NEXT: blr
1106 ;
1107 ; P9LE-LABEL: fromRandMemConsi:
1108 ; P9LE: # %bb.0: # %entry
1109 ; P9LE-NEXT: lwz r4, 16(r3)
1110 ; P9LE-NEXT: lwz r5, 72(r3)
1111 ; P9LE-NEXT: lwz r6, 8(r3)
1112 ; P9LE-NEXT: lwz r3, 352(r3)
1113 ; P9LE-NEXT: rldimi r4, r5, 32, 0
1114 ; P9LE-NEXT: rldimi r6, r3, 32, 0
1115 ; P9LE-NEXT: mtvsrdd v2, r6, r4
1116 ; P9LE-NEXT: blr
1117 ;
1118 ; P8BE-LABEL: fromRandMemConsi:
1119 ; P8BE: # %bb.0: # %entry
1120 ; P8BE-NEXT: lwz r4, 8(r3)
1121 ; P8BE-NEXT: lwz r5, 352(r3)
1122 ; P8BE-NEXT: lwz r6, 16(r3)
1123 ; P8BE-NEXT: lwz r3, 72(r3)
1124 ; P8BE-NEXT: rldimi r5, r4, 32, 0
1125 ; P8BE-NEXT: rldimi r3, r6, 32, 0
1126 ; P8BE-NEXT: mtfprd f0, r5
1127 ; P8BE-NEXT: mtfprd f1, r3
1128 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
1129 ; P8BE-NEXT: blr
1130 ;
1131 ; P8LE-LABEL: fromRandMemConsi:
1132 ; P8LE: # %bb.0: # %entry
1133 ; P8LE-NEXT: lwz r4, 16(r3)
1134 ; P8LE-NEXT: lwz r5, 72(r3)
1135 ; P8LE-NEXT: lwz r6, 8(r3)
1136 ; P8LE-NEXT: lwz r3, 352(r3)
1137 ; P8LE-NEXT: rldimi r4, r5, 32, 0
1138 ; P8LE-NEXT: rldimi r6, r3, 32, 0
1139 ; P8LE-NEXT: mtfprd f0, r4
1140 ; P8LE-NEXT: mtfprd f1, r6
1141 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
1142 ; P8LE-NEXT: blr
1143 entry:
1144 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 4
1145 %0 = load i32, ptr %arrayidx, align 4
1146 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
1147 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 18
1148 %1 = load i32, ptr %arrayidx1, align 4
1149 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
1150 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 2
1151 %2 = load i32, ptr %arrayidx3, align 4
1152 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
1153 %arrayidx5 = getelementptr inbounds i32, ptr %arr, i64 88
1154 %3 = load i32, ptr %arrayidx5, align 4
1155 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
1156 ret <4 x i32> %vecinit6
1157 }
1159 define <4 x i32> @fromRandMemVari(ptr nocapture readonly %arr, i32 signext %elem) {
1160 ; P9BE-LABEL: fromRandMemVari:
1161 ; P9BE: # %bb.0: # %entry
1162 ; P9BE-NEXT: sldi r4, r4, 2
1163 ; P9BE-NEXT: add r3, r3, r4
1164 ; P9BE-NEXT: lwz r4, 16(r3)
1165 ; P9BE-NEXT: lwz r5, 4(r3)
1166 ; P9BE-NEXT: lwz r6, 8(r3)
1167 ; P9BE-NEXT: lwz r3, 32(r3)
1168 ; P9BE-NEXT: rldimi r3, r6, 32, 0
1169 ; P9BE-NEXT: rldimi r5, r4, 32, 0
1170 ; P9BE-NEXT: mtvsrdd v2, r5, r3
1171 ; P9BE-NEXT: blr
1172 ;
1173 ; P9LE-LABEL: fromRandMemVari:
1174 ; P9LE: # %bb.0: # %entry
1175 ; P9LE-NEXT: sldi r4, r4, 2
1176 ; P9LE-NEXT: add r3, r3, r4
1177 ; P9LE-NEXT: lwz r4, 16(r3)
1178 ; P9LE-NEXT: lwz r5, 4(r3)
1179 ; P9LE-NEXT: lwz r6, 8(r3)
1180 ; P9LE-NEXT: lwz r3, 32(r3)
1181 ; P9LE-NEXT: rldimi r4, r5, 32, 0
1182 ; P9LE-NEXT: rldimi r6, r3, 32, 0
1183 ; P9LE-NEXT: mtvsrdd v2, r6, r4
1184 ; P9LE-NEXT: blr
1185 ;
1186 ; P8BE-LABEL: fromRandMemVari:
1187 ; P8BE: # %bb.0: # %entry
1188 ; P8BE-NEXT: sldi r4, r4, 2
1189 ; P8BE-NEXT: add r3, r3, r4
1190 ; P8BE-NEXT: lwz r4, 8(r3)
1191 ; P8BE-NEXT: lwz r5, 32(r3)
1192 ; P8BE-NEXT: lwz r6, 16(r3)
1193 ; P8BE-NEXT: lwz r3, 4(r3)
1194 ; P8BE-NEXT: rldimi r5, r4, 32, 0
1195 ; P8BE-NEXT: rldimi r3, r6, 32, 0
1196 ; P8BE-NEXT: mtfprd f0, r5
1197 ; P8BE-NEXT: mtfprd f1, r3
1198 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
1199 ; P8BE-NEXT: blr
1200 ;
1201 ; P8LE-LABEL: fromRandMemVari:
1202 ; P8LE: # %bb.0: # %entry
1203 ; P8LE-NEXT: sldi r4, r4, 2
1204 ; P8LE-NEXT: add r3, r3, r4
1205 ; P8LE-NEXT: lwz r4, 16(r3)
1206 ; P8LE-NEXT: lwz r5, 4(r3)
1207 ; P8LE-NEXT: lwz r6, 8(r3)
1208 ; P8LE-NEXT: lwz r3, 32(r3)
1209 ; P8LE-NEXT: rldimi r4, r5, 32, 0
1210 ; P8LE-NEXT: rldimi r6, r3, 32, 0
1211 ; P8LE-NEXT: mtfprd f0, r4
1212 ; P8LE-NEXT: mtfprd f1, r6
1213 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
1214 ; P8LE-NEXT: blr
1215 entry:
1216 %add = add nsw i32 %elem, 4
1217 %idxprom = sext i32 %add to i64
1218 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom
1219 %0 = load i32, ptr %arrayidx, align 4
1220 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
1221 %add1 = add nsw i32 %elem, 1
1222 %idxprom2 = sext i32 %add1 to i64
1223 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 %idxprom2
1224 %1 = load i32, ptr %arrayidx3, align 4
1225 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
1226 %add5 = add nsw i32 %elem, 2
1227 %idxprom6 = sext i32 %add5 to i64
1228 %arrayidx7 = getelementptr inbounds i32, ptr %arr, i64 %idxprom6
1229 %2 = load i32, ptr %arrayidx7, align 4
1230 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2
1231 %add9 = add nsw i32 %elem, 8
1232 %idxprom10 = sext i32 %add9 to i64
1233 %arrayidx11 = getelementptr inbounds i32, ptr %arr, i64 %idxprom10
1234 %3 = load i32, ptr %arrayidx11, align 4
1235 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3
1236 ret <4 x i32> %vecinit12
1237 }
1239 define <4 x i32> @spltRegVali(i32 signext %val) {
1240 ; P9BE-LABEL: spltRegVali:
1241 ; P9BE: # %bb.0: # %entry
1242 ; P9BE-NEXT: mtvsrws v2, r3
1243 ; P9BE-NEXT: blr
1244 ;
1245 ; P9LE-LABEL: spltRegVali:
1246 ; P9LE: # %bb.0: # %entry
1247 ; P9LE-NEXT: mtvsrws v2, r3
1248 ; P9LE-NEXT: blr
1249 ;
1250 ; P8BE-LABEL: spltRegVali:
1251 ; P8BE: # %bb.0: # %entry
1252 ; P8BE-NEXT: mtfprwz f0, r3
1253 ; P8BE-NEXT: xxspltw v2, vs0, 1
1254 ; P8BE-NEXT: blr
1255 ;
1256 ; P8LE-LABEL: spltRegVali:
1257 ; P8LE: # %bb.0: # %entry
1258 ; P8LE-NEXT: mtfprwz f0, r3
1259 ; P8LE-NEXT: xxspltw v2, vs0, 1
1260 ; P8LE-NEXT: blr
1261 entry:
1262 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0
1263 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
1264 ret <4 x i32> %splat.splat
1265 }
1267 define <4 x i32> @spltMemVali(ptr nocapture readonly %ptr) {
1268 ; P9BE-LABEL: spltMemVali:
1269 ; P9BE: # %bb.0: # %entry
1270 ; P9BE-NEXT: lxvwsx v2, 0, r3
1271 ; P9BE-NEXT: blr
1272 ;
1273 ; P9LE-LABEL: spltMemVali:
1274 ; P9LE: # %bb.0: # %entry
1275 ; P9LE-NEXT: lxvwsx v2, 0, r3
1276 ; P9LE-NEXT: blr
1277 ;
1278 ; P8BE-LABEL: spltMemVali:
1279 ; P8BE: # %bb.0: # %entry
1280 ; P8BE-NEXT: lfiwzx f0, 0, r3
1281 ; P8BE-NEXT: xxspltw v2, vs0, 1
1282 ; P8BE-NEXT: blr
1283 ;
1284 ; P8LE-LABEL: spltMemVali:
1285 ; P8LE: # %bb.0: # %entry
1286 ; P8LE-NEXT: lfiwzx f0, 0, r3
1287 ; P8LE-NEXT: xxspltw v2, vs0, 1
1288 ; P8LE-NEXT: blr
1289 entry:
1290 %0 = load i32, ptr %ptr, align 4
1291 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
1292 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
1293 ret <4 x i32> %splat.splat
1294 }
1296 define <4 x i32> @spltCnstConvftoi() {
1297 ; P9BE-LABEL: spltCnstConvftoi:
1298 ; P9BE: # %bb.0: # %entry
1299 ; P9BE-NEXT: vspltisw v2, 4
1300 ; P9BE-NEXT: blr
1301 ;
1302 ; P9LE-LABEL: spltCnstConvftoi:
1303 ; P9LE: # %bb.0: # %entry
1304 ; P9LE-NEXT: vspltisw v2, 4
1305 ; P9LE-NEXT: blr
1306 ;
1307 ; P8BE-LABEL: spltCnstConvftoi:
1308 ; P8BE: # %bb.0: # %entry
1309 ; P8BE-NEXT: vspltisw v2, 4
1310 ; P8BE-NEXT: blr
1311 ;
1312 ; P8LE-LABEL: spltCnstConvftoi:
1313 ; P8LE: # %bb.0: # %entry
1314 ; P8LE-NEXT: vspltisw v2, 4
1315 ; P8LE-NEXT: blr
1316 entry:
1317 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4>
1318 }
1320 define <4 x i32> @fromRegsConvftoi(float %a, float %b, float %c, float %d) {
1321 ; P9BE-LABEL: fromRegsConvftoi:
1322 ; P9BE: # %bb.0: # %entry
1323 ; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1324 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1325 ; P9BE-NEXT: xxmrghd vs0, vs2, vs4
1326 ; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1327 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1328 ; P9BE-NEXT: xvcvdpsxws v2, vs0
1329 ; P9BE-NEXT: xxmrghd vs0, vs1, vs3
1330 ; P9BE-NEXT: xvcvdpsxws v3, vs0
1331 ; P9BE-NEXT: vmrgew v2, v3, v2
1332 ; P9BE-NEXT: blr
1333 ;
1334 ; P9LE-LABEL: fromRegsConvftoi:
1335 ; P9LE: # %bb.0: # %entry
1336 ; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1337 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1338 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
1339 ; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1340 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1341 ; P9LE-NEXT: xvcvdpsxws v2, vs0
1342 ; P9LE-NEXT: xxmrghd vs0, vs4, vs2
1343 ; P9LE-NEXT: xvcvdpsxws v3, vs0
1344 ; P9LE-NEXT: vmrgew v2, v3, v2
1345 ; P9LE-NEXT: blr
1346 ;
1347 ; P8BE-LABEL: fromRegsConvftoi:
1348 ; P8BE: # %bb.0: # %entry
1349 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1350 ; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1351 ; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1352 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1353 ; P8BE-NEXT: xxmrghd vs0, vs2, vs4
1354 ; P8BE-NEXT: xxmrghd vs1, vs1, vs3
1355 ; P8BE-NEXT: xvcvdpsxws v2, vs0
1356 ; P8BE-NEXT: xvcvdpsxws v3, vs1
1357 ; P8BE-NEXT: vmrgew v2, v3, v2
1358 ; P8BE-NEXT: blr
1359 ;
1360 ; P8LE-LABEL: fromRegsConvftoi:
1361 ; P8LE: # %bb.0: # %entry
1362 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1363 ; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1364 ; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1365 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1366 ; P8LE-NEXT: xxmrghd vs0, vs3, vs1
1367 ; P8LE-NEXT: xxmrghd vs1, vs4, vs2
1368 ; P8LE-NEXT: xvcvdpsxws v2, vs0
1369 ; P8LE-NEXT: xvcvdpsxws v3, vs1
1370 ; P8LE-NEXT: vmrgew v2, v3, v2
1371 ; P8LE-NEXT: blr
1372 entry:
1373 %conv = fptosi float %a to i32
1374 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1375 %conv1 = fptosi float %b to i32
1376 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1
1377 %conv3 = fptosi float %c to i32
1378 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2
1379 %conv5 = fptosi float %d to i32
1380 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
1381 ret <4 x i32> %vecinit6
1382 }
1384 define <4 x i32> @fromDiffConstsConvftoi() {
1385 ; P9BE-LABEL: fromDiffConstsConvftoi:
1386 ; P9BE: # %bb.0: # %entry
1387 ; P9BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha
1388 ; P9BE-NEXT: addi r3, r3, .LCPI16_0@toc@l
1389 ; P9BE-NEXT: lxv v2, 0(r3)
1390 ; P9BE-NEXT: blr
1391 ;
1392 ; P9LE-LABEL: fromDiffConstsConvftoi:
1393 ; P9LE: # %bb.0: # %entry
1394 ; P9LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha
1395 ; P9LE-NEXT: addi r3, r3, .LCPI16_0@toc@l
1396 ; P9LE-NEXT: lxv v2, 0(r3)
1397 ; P9LE-NEXT: blr
1398 ;
1399 ; P8BE-LABEL: fromDiffConstsConvftoi:
1400 ; P8BE: # %bb.0: # %entry
1401 ; P8BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha
1402 ; P8BE-NEXT: addi r3, r3, .LCPI16_0@toc@l
1403 ; P8BE-NEXT: lxvw4x v2, 0, r3
1404 ; P8BE-NEXT: blr
1405 ;
1406 ; P8LE-LABEL: fromDiffConstsConvftoi:
1407 ; P8LE: # %bb.0: # %entry
1408 ; P8LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha
1409 ; P8LE-NEXT: addi r3, r3, .LCPI16_0@toc@l
1410 ; P8LE-NEXT: lxvd2x vs0, 0, r3
1411 ; P8LE-NEXT: xxswapd v2, vs0
1412 ; P8LE-NEXT: blr
1413 entry:
1414 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
1415 }
1417 define <4 x i32> @fromDiffMemConsAConvftoi(ptr nocapture readonly %ptr) {
1418 ; P9BE-LABEL: fromDiffMemConsAConvftoi:
1419 ; P9BE: # %bb.0: # %entry
1420 ; P9BE-NEXT: lxv vs0, 0(r3)
1421 ; P9BE-NEXT: xvcvspsxws v2, vs0
1422 ; P9BE-NEXT: blr
1423 ;
1424 ; P9LE-LABEL: fromDiffMemConsAConvftoi:
1425 ; P9LE: # %bb.0: # %entry
1426 ; P9LE-NEXT: lxv vs0, 0(r3)
1427 ; P9LE-NEXT: xvcvspsxws v2, vs0
1428 ; P9LE-NEXT: blr
1429 ;
1430 ; P8BE-LABEL: fromDiffMemConsAConvftoi:
1431 ; P8BE: # %bb.0: # %entry
1432 ; P8BE-NEXT: lxvw4x vs0, 0, r3
1433 ; P8BE-NEXT: xvcvspsxws v2, vs0
1434 ; P8BE-NEXT: blr
1435 ;
1436 ; P8LE-LABEL: fromDiffMemConsAConvftoi:
1437 ; P8LE: # %bb.0: # %entry
1438 ; P8LE-NEXT: lxvd2x vs0, 0, r3
1439 ; P8LE-NEXT: xxswapd v2, vs0
1440 ; P8LE-NEXT: xvcvspsxws v2, v2
1441 ; P8LE-NEXT: blr
1442 entry:
1443 %0 = load <4 x float>, ptr %ptr, align 4
1444 %1 = fptosi <4 x float> %0 to <4 x i32>
1445 ret <4 x i32> %1
1446 }
1448 define <4 x i32> @fromDiffMemConsDConvftoi(ptr nocapture readonly %ptr) {
1449 ; P9BE-LABEL: fromDiffMemConsDConvftoi:
1450 ; P9BE: # %bb.0: # %entry
1451 ; P9BE-NEXT: lxv vs0, 0(r3)
1452 ; P9BE-NEXT: addis r3, r2, .LCPI18_0@toc@ha
1453 ; P9BE-NEXT: addi r3, r3, .LCPI18_0@toc@l
1454 ; P9BE-NEXT: lxv vs1, 0(r3)
1455 ; P9BE-NEXT: xxperm vs0, vs0, vs1
1456 ; P9BE-NEXT: xvcvspsxws v2, vs0
1457 ; P9BE-NEXT: blr
1458 ;
1459 ; P9LE-LABEL: fromDiffMemConsDConvftoi:
1460 ; P9LE: # %bb.0: # %entry
1461 ; P9LE-NEXT: lxv vs0, 0(r3)
1462 ; P9LE-NEXT: addis r3, r2, .LCPI18_0@toc@ha
1463 ; P9LE-NEXT: addi r3, r3, .LCPI18_0@toc@l
1464 ; P9LE-NEXT: lxv vs1, 0(r3)
1465 ; P9LE-NEXT: xxperm vs0, vs0, vs1
1466 ; P9LE-NEXT: xvcvspsxws v2, vs0
1467 ; P9LE-NEXT: blr
1468 ;
1469 ; P8BE-LABEL: fromDiffMemConsDConvftoi:
1470 ; P8BE: # %bb.0: # %entry
1471 ; P8BE-NEXT: addis r4, r2, .LCPI18_0@toc@ha
1472 ; P8BE-NEXT: lxvw4x v2, 0, r3
1473 ; P8BE-NEXT: addi r4, r4, .LCPI18_0@toc@l
1474 ; P8BE-NEXT: lxvw4x v3, 0, r4
1475 ; P8BE-NEXT: vperm v2, v2, v2, v3
1476 ; P8BE-NEXT: xvcvspsxws v2, v2
1477 ; P8BE-NEXT: blr
1478 ;
1479 ; P8LE-LABEL: fromDiffMemConsDConvftoi:
1480 ; P8LE: # %bb.0: # %entry
1481 ; P8LE-NEXT: addis r4, r2, .LCPI18_0@toc@ha
1482 ; P8LE-NEXT: lxvd2x vs0, 0, r3
1483 ; P8LE-NEXT: addi r4, r4, .LCPI18_0@toc@l
1484 ; P8LE-NEXT: lxvd2x vs1, 0, r4
1485 ; P8LE-NEXT: xxswapd v2, vs0
1486 ; P8LE-NEXT: xxswapd v3, vs1
1487 ; P8LE-NEXT: vperm v2, v2, v2, v3
1488 ; P8LE-NEXT: xvcvspsxws v2, v2
1489 ; P8LE-NEXT: blr
1490 entry:
1491 %arrayidx = getelementptr inbounds float, ptr %ptr, i64 3
1492 %0 = load float, ptr %arrayidx, align 4
1493 %conv = fptosi float %0 to i32
1494 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1495 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 2
1496 %1 = load float, ptr %arrayidx1, align 4
1497 %conv2 = fptosi float %1 to i32
1498 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
1499 %arrayidx4 = getelementptr inbounds float, ptr %ptr, i64 1
1500 %2 = load float, ptr %arrayidx4, align 4
1501 %conv5 = fptosi float %2 to i32
1502 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
1503 %3 = load float, ptr %ptr, align 4
1504 %conv8 = fptosi float %3 to i32
1505 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
1506 ret <4 x i32> %vecinit9
1507 }
1509 define <4 x i32> @fromDiffMemVarAConvftoi(ptr nocapture readonly %arr, i32 signext %elem) {
1510 ; P9BE-LABEL: fromDiffMemVarAConvftoi:
1511 ; P9BE: # %bb.0: # %entry
1512 ; P9BE-NEXT: sldi r4, r4, 2
1513 ; P9BE-NEXT: lfsux f0, r3, r4
1514 ; P9BE-NEXT: lfs f1, 12(r3)
1515 ; P9BE-NEXT: lfs f2, 4(r3)
1516 ; P9BE-NEXT: xxmrghd vs1, vs2, vs1
1517 ; P9BE-NEXT: xvcvdpsp v2, vs1
1518 ; P9BE-NEXT: lfs f1, 8(r3)
1519 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
1520 ; P9BE-NEXT: xvcvdpsp v3, vs0
1521 ; P9BE-NEXT: vmrgew v2, v3, v2
1522 ; P9BE-NEXT: xvcvspsxws v2, v2
1523 ; P9BE-NEXT: blr
1524 ;
1525 ; P9LE-LABEL: fromDiffMemVarAConvftoi:
1526 ; P9LE: # %bb.0: # %entry
1527 ; P9LE-NEXT: sldi r4, r4, 2
1528 ; P9LE-NEXT: lfsux f0, r3, r4
1529 ; P9LE-NEXT: lfs f1, 8(r3)
1530 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
1531 ; P9LE-NEXT: lfs f1, 12(r3)
1532 ; P9LE-NEXT: xvcvdpsp v2, vs0
1533 ; P9LE-NEXT: lfs f0, 4(r3)
1534 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
1535 ; P9LE-NEXT: xvcvdpsp v3, vs0
1536 ; P9LE-NEXT: vmrgew v2, v3, v2
1537 ; P9LE-NEXT: xvcvspsxws v2, v2
1538 ; P9LE-NEXT: blr
1539 ;
1540 ; P8BE-LABEL: fromDiffMemVarAConvftoi:
1541 ; P8BE: # %bb.0: # %entry
1542 ; P8BE-NEXT: sldi r4, r4, 2
1543 ; P8BE-NEXT: lfsux f0, r3, r4
1544 ; P8BE-NEXT: lfs f1, 12(r3)
1545 ; P8BE-NEXT: lfs f2, 4(r3)
1546 ; P8BE-NEXT: lfs f3, 8(r3)
1547 ; P8BE-NEXT: xxmrghd vs1, vs2, vs1
1548 ; P8BE-NEXT: xxmrghd vs0, vs0, vs3
1549 ; P8BE-NEXT: xvcvdpsp v2, vs1
1550 ; P8BE-NEXT: xvcvdpsp v3, vs0
1551 ; P8BE-NEXT: vmrgew v2, v3, v2
1552 ; P8BE-NEXT: xvcvspsxws v2, v2
1553 ; P8BE-NEXT: blr
1554 ;
1555 ; P8LE-LABEL: fromDiffMemVarAConvftoi:
1556 ; P8LE: # %bb.0: # %entry
1557 ; P8LE-NEXT: sldi r4, r4, 2
1558 ; P8LE-NEXT: lfsux f0, r3, r4
1559 ; P8LE-NEXT: lfs f1, 8(r3)
1560 ; P8LE-NEXT: lfs f2, 4(r3)
1561 ; P8LE-NEXT: lfs f3, 12(r3)
1562 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
1563 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2
1564 ; P8LE-NEXT: xvcvdpsp v2, vs0
1565 ; P8LE-NEXT: xvcvdpsp v3, vs1
1566 ; P8LE-NEXT: vmrgew v2, v3, v2
1567 ; P8LE-NEXT: xvcvspsxws v2, v2
1568 ; P8LE-NEXT: blr
1569 entry:
1570 %idxprom = sext i32 %elem to i64
1571 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom
1572 %0 = load float, ptr %arrayidx, align 4
1573 %conv = fptosi float %0 to i32
1574 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1575 %add = add nsw i32 %elem, 1
1576 %idxprom1 = sext i32 %add to i64
1577 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1
1578 %1 = load float, ptr %arrayidx2, align 4
1579 %conv3 = fptosi float %1 to i32
1580 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
1581 %add5 = add nsw i32 %elem, 2
1582 %idxprom6 = sext i32 %add5 to i64
1583 %arrayidx7 = getelementptr inbounds float, ptr %arr, i64 %idxprom6
1584 %2 = load float, ptr %arrayidx7, align 4
1585 %conv8 = fptosi float %2 to i32
1586 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
1587 %add10 = add nsw i32 %elem, 3
1588 %idxprom11 = sext i32 %add10 to i64
1589 %arrayidx12 = getelementptr inbounds float, ptr %arr, i64 %idxprom11
1590 %3 = load float, ptr %arrayidx12, align 4
1591 %conv13 = fptosi float %3 to i32
1592 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
1593 ret <4 x i32> %vecinit14
1594 }
1596 define <4 x i32> @fromDiffMemVarDConvftoi(ptr nocapture readonly %arr, i32 signext %elem) {
1597 ; P9BE-LABEL: fromDiffMemVarDConvftoi:
1598 ; P9BE: # %bb.0: # %entry
1599 ; P9BE-NEXT: sldi r4, r4, 2
1600 ; P9BE-NEXT: lfsux f0, r3, r4
1601 ; P9BE-NEXT: lfs f1, -12(r3)
1602 ; P9BE-NEXT: lfs f2, -4(r3)
1603 ; P9BE-NEXT: xxmrghd vs1, vs2, vs1
1604 ; P9BE-NEXT: xvcvdpsp v2, vs1
1605 ; P9BE-NEXT: lfs f1, -8(r3)
1606 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
1607 ; P9BE-NEXT: xvcvdpsp v3, vs0
1608 ; P9BE-NEXT: vmrgew v2, v3, v2
1609 ; P9BE-NEXT: xvcvspsxws v2, v2
1610 ; P9BE-NEXT: blr
1611 ;
1612 ; P9LE-LABEL: fromDiffMemVarDConvftoi:
1613 ; P9LE: # %bb.0: # %entry
1614 ; P9LE-NEXT: sldi r4, r4, 2
1615 ; P9LE-NEXT: lfsux f0, r3, r4
1616 ; P9LE-NEXT: lfs f1, -8(r3)
1617 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
1618 ; P9LE-NEXT: lfs f1, -12(r3)
1619 ; P9LE-NEXT: xvcvdpsp v2, vs0
1620 ; P9LE-NEXT: lfs f0, -4(r3)
1621 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
1622 ; P9LE-NEXT: xvcvdpsp v3, vs0
1623 ; P9LE-NEXT: vmrgew v2, v3, v2
1624 ; P9LE-NEXT: xvcvspsxws v2, v2
1625 ; P9LE-NEXT: blr
1626 ;
1627 ; P8BE-LABEL: fromDiffMemVarDConvftoi:
1628 ; P8BE: # %bb.0: # %entry
1629 ; P8BE-NEXT: sldi r4, r4, 2
1630 ; P8BE-NEXT: lfsux f0, r3, r4
1631 ; P8BE-NEXT: lfs f1, -12(r3)
1632 ; P8BE-NEXT: lfs f2, -4(r3)
1633 ; P8BE-NEXT: lfs f3, -8(r3)
1634 ; P8BE-NEXT: xxmrghd vs1, vs2, vs1
1635 ; P8BE-NEXT: xxmrghd vs0, vs0, vs3
1636 ; P8BE-NEXT: xvcvdpsp v2, vs1
1637 ; P8BE-NEXT: xvcvdpsp v3, vs0
1638 ; P8BE-NEXT: vmrgew v2, v3, v2
1639 ; P8BE-NEXT: xvcvspsxws v2, v2
1640 ; P8BE-NEXT: blr
1641 ;
1642 ; P8LE-LABEL: fromDiffMemVarDConvftoi:
1643 ; P8LE: # %bb.0: # %entry
1644 ; P8LE-NEXT: sldi r4, r4, 2
1645 ; P8LE-NEXT: lfsux f0, r3, r4
1646 ; P8LE-NEXT: lfs f1, -8(r3)
1647 ; P8LE-NEXT: lfs f2, -4(r3)
1648 ; P8LE-NEXT: lfs f3, -12(r3)
1649 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
1650 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2
1651 ; P8LE-NEXT: xvcvdpsp v2, vs0
1652 ; P8LE-NEXT: xvcvdpsp v3, vs1
1653 ; P8LE-NEXT: vmrgew v2, v3, v2
1654 ; P8LE-NEXT: xvcvspsxws v2, v2
1655 ; P8LE-NEXT: blr
1656 entry:
1657 %idxprom = sext i32 %elem to i64
1658 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom
1659 %0 = load float, ptr %arrayidx, align 4
1660 %conv = fptosi float %0 to i32
1661 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1662 %sub = add nsw i32 %elem, -1
1663 %idxprom1 = sext i32 %sub to i64
1664 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1
1665 %1 = load float, ptr %arrayidx2, align 4
1666 %conv3 = fptosi float %1 to i32
1667 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
1668 %sub5 = add nsw i32 %elem, -2
1669 %idxprom6 = sext i32 %sub5 to i64
1670 %arrayidx7 = getelementptr inbounds float, ptr %arr, i64 %idxprom6
1671 %2 = load float, ptr %arrayidx7, align 4
1672 %conv8 = fptosi float %2 to i32
1673 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
1674 %sub10 = add nsw i32 %elem, -3
1675 %idxprom11 = sext i32 %sub10 to i64
1676 %arrayidx12 = getelementptr inbounds float, ptr %arr, i64 %idxprom11
1677 %3 = load float, ptr %arrayidx12, align 4
1678 %conv13 = fptosi float %3 to i32
1679 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
1680 ret <4 x i32> %vecinit14
1681 ; FIXME: implement finding consecutive loads with pre-inc
1682 }
1684 define <4 x i32> @spltRegValConvftoi(float %val) {
1685 ; P9BE-LABEL: spltRegValConvftoi:
1686 ; P9BE: # %bb.0: # %entry
1687 ; P9BE-NEXT: xscvdpsxws f0, f1
1688 ; P9BE-NEXT: xxspltw v2, vs0, 1
1689 ; P9BE-NEXT: blr
1690 ;
1691 ; P9LE-LABEL: spltRegValConvftoi:
1692 ; P9LE: # %bb.0: # %entry
1693 ; P9LE-NEXT: xscvdpsxws f0, f1
1694 ; P9LE-NEXT: xxspltw v2, vs0, 1
1695 ; P9LE-NEXT: blr
1696 ;
1697 ; P8BE-LABEL: spltRegValConvftoi:
1698 ; P8BE: # %bb.0: # %entry
1699 ; P8BE-NEXT: xscvdpsxws f0, f1
1700 ; P8BE-NEXT: xxspltw v2, vs0, 1
1701 ; P8BE-NEXT: blr
1702 ;
1703 ; P8LE-LABEL: spltRegValConvftoi:
1704 ; P8LE: # %bb.0: # %entry
1705 ; P8LE-NEXT: xscvdpsxws f0, f1
1706 ; P8LE-NEXT: xxspltw v2, vs0, 1
1707 ; P8LE-NEXT: blr
1708 entry:
1709 %conv = fptosi float %val to i32
1710 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
1711 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
1712 ret <4 x i32> %splat.splat
1713 }
1715 define <4 x i32> @spltMemValConvftoi(ptr nocapture readonly %ptr) {
1716 ; P9BE-LABEL: spltMemValConvftoi:
1717 ; P9BE: # %bb.0: # %entry
1718 ; P9BE-NEXT: lfiwzx f0, 0, r3
1719 ; P9BE-NEXT: xvcvspsxws vs0, vs0
1720 ; P9BE-NEXT: xxspltw v2, vs0, 1
1721 ; P9BE-NEXT: blr
1722 ;
1723 ; P9LE-LABEL: spltMemValConvftoi:
1724 ; P9LE: # %bb.0: # %entry
1725 ; P9LE-NEXT: lfiwzx f0, 0, r3
1726 ; P9LE-NEXT: xvcvspsxws vs0, vs0
1727 ; P9LE-NEXT: xxspltw v2, vs0, 1
1728 ; P9LE-NEXT: blr
1729 ;
1730 ; P8BE-LABEL: spltMemValConvftoi:
1731 ; P8BE: # %bb.0: # %entry
1732 ; P8BE-NEXT: lfsx f0, 0, r3
1733 ; P8BE-NEXT: xscvdpsxws f0, f0
1734 ; P8BE-NEXT: xxspltw v2, vs0, 1
1735 ; P8BE-NEXT: blr
1736 ;
1737 ; P8LE-LABEL: spltMemValConvftoi:
1738 ; P8LE: # %bb.0: # %entry
1739 ; P8LE-NEXT: lfsx f0, 0, r3
1740 ; P8LE-NEXT: xscvdpsxws f0, f0
1741 ; P8LE-NEXT: xxspltw v2, vs0, 1
1742 ; P8LE-NEXT: blr
1743 entry:
1744 %0 = load float, ptr %ptr, align 4
1745 %conv = fptosi float %0 to i32
1746 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
1747 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
1748 ret <4 x i32> %splat.splat
1749 }
1751 define <4 x i32> @spltCnstConvdtoi() {
1752 ; P9BE-LABEL: spltCnstConvdtoi:
1753 ; P9BE: # %bb.0: # %entry
1754 ; P9BE-NEXT: vspltisw v2, 4
1755 ; P9BE-NEXT: blr
1756 ;
1757 ; P9LE-LABEL: spltCnstConvdtoi:
1758 ; P9LE: # %bb.0: # %entry
1759 ; P9LE-NEXT: vspltisw v2, 4
1760 ; P9LE-NEXT: blr
1761 ;
1762 ; P8BE-LABEL: spltCnstConvdtoi:
1763 ; P8BE: # %bb.0: # %entry
1764 ; P8BE-NEXT: vspltisw v2, 4
1765 ; P8BE-NEXT: blr
1766 ;
1767 ; P8LE-LABEL: spltCnstConvdtoi:
1768 ; P8LE: # %bb.0: # %entry
1769 ; P8LE-NEXT: vspltisw v2, 4
1770 ; P8LE-NEXT: blr
1771 entry:
1772 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4>
1773 }
1775 define <4 x i32> @fromRegsConvdtoi(double %a, double %b, double %c, double %d) {
1776 ; P9BE-LABEL: fromRegsConvdtoi:
1777 ; P9BE: # %bb.0: # %entry
1778 ; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1779 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1780 ; P9BE-NEXT: xxmrghd vs0, vs2, vs4
1781 ; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1782 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1783 ; P9BE-NEXT: xvcvdpsxws v2, vs0
1784 ; P9BE-NEXT: xxmrghd vs0, vs1, vs3
1785 ; P9BE-NEXT: xvcvdpsxws v3, vs0
1786 ; P9BE-NEXT: vmrgew v2, v3, v2
1787 ; P9BE-NEXT: blr
1788 ;
1789 ; P9LE-LABEL: fromRegsConvdtoi:
1790 ; P9LE: # %bb.0: # %entry
1791 ; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1792 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1793 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
1794 ; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1795 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1796 ; P9LE-NEXT: xvcvdpsxws v2, vs0
1797 ; P9LE-NEXT: xxmrghd vs0, vs4, vs2
1798 ; P9LE-NEXT: xvcvdpsxws v3, vs0
1799 ; P9LE-NEXT: vmrgew v2, v3, v2
1800 ; P9LE-NEXT: blr
1801 ;
1802 ; P8BE-LABEL: fromRegsConvdtoi:
1803 ; P8BE: # %bb.0: # %entry
1804 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1805 ; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1806 ; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1807 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1808 ; P8BE-NEXT: xxmrghd vs0, vs2, vs4
1809 ; P8BE-NEXT: xxmrghd vs1, vs1, vs3
1810 ; P8BE-NEXT: xvcvdpsxws v2, vs0
1811 ; P8BE-NEXT: xvcvdpsxws v3, vs1
1812 ; P8BE-NEXT: vmrgew v2, v3, v2
1813 ; P8BE-NEXT: blr
1814 ;
1815 ; P8LE-LABEL: fromRegsConvdtoi:
1816 ; P8LE: # %bb.0: # %entry
1817 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1818 ; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1819 ; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1820 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1821 ; P8LE-NEXT: xxmrghd vs0, vs3, vs1
1822 ; P8LE-NEXT: xxmrghd vs1, vs4, vs2
1823 ; P8LE-NEXT: xvcvdpsxws v2, vs0
1824 ; P8LE-NEXT: xvcvdpsxws v3, vs1
1825 ; P8LE-NEXT: vmrgew v2, v3, v2
1826 ; P8LE-NEXT: blr
1827 entry:
1828 %conv = fptosi double %a to i32
1829 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1830 %conv1 = fptosi double %b to i32
1831 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1
1832 %conv3 = fptosi double %c to i32
1833 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2
1834 %conv5 = fptosi double %d to i32
1835 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
1836 ret <4 x i32> %vecinit6
1837 }
1839 define <4 x i32> @fromDiffConstsConvdtoi() {
1840 ; P9BE-LABEL: fromDiffConstsConvdtoi:
1841 ; P9BE: # %bb.0: # %entry
1842 ; P9BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha
1843 ; P9BE-NEXT: addi r3, r3, .LCPI25_0@toc@l
1844 ; P9BE-NEXT: lxv v2, 0(r3)
1845 ; P9BE-NEXT: blr
1846 ;
1847 ; P9LE-LABEL: fromDiffConstsConvdtoi:
1848 ; P9LE: # %bb.0: # %entry
1849 ; P9LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha
1850 ; P9LE-NEXT: addi r3, r3, .LCPI25_0@toc@l
1851 ; P9LE-NEXT: lxv v2, 0(r3)
1852 ; P9LE-NEXT: blr
1853 ;
1854 ; P8BE-LABEL: fromDiffConstsConvdtoi:
1855 ; P8BE: # %bb.0: # %entry
1856 ; P8BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha
1857 ; P8BE-NEXT: addi r3, r3, .LCPI25_0@toc@l
1858 ; P8BE-NEXT: lxvw4x v2, 0, r3
1859 ; P8BE-NEXT: blr
1860 ;
1861 ; P8LE-LABEL: fromDiffConstsConvdtoi:
1862 ; P8LE: # %bb.0: # %entry
1863 ; P8LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha
1864 ; P8LE-NEXT: addi r3, r3, .LCPI25_0@toc@l
1865 ; P8LE-NEXT: lxvd2x vs0, 0, r3
1866 ; P8LE-NEXT: xxswapd v2, vs0
1867 ; P8LE-NEXT: blr
1868 entry:
1869 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
1870 }
1872 define <4 x i32> @fromDiffMemConsAConvdtoi(ptr nocapture readonly %ptr) {
1873 ; P9BE-LABEL: fromDiffMemConsAConvdtoi:
1874 ; P9BE: # %bb.0: # %entry
1875 ; P9BE-NEXT: lxv vs0, 0(r3)
1876 ; P9BE-NEXT: lxv vs1, 16(r3)
1877 ; P9BE-NEXT: xxmrgld vs2, vs0, vs1
1878 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
1879 ; P9BE-NEXT: xvcvdpsxws v2, vs2
1880 ; P9BE-NEXT: xvcvdpsxws v3, vs0
1881 ; P9BE-NEXT: vmrgew v2, v3, v2
1882 ; P9BE-NEXT: blr
1883 ;
1884 ; P9LE-LABEL: fromDiffMemConsAConvdtoi:
1885 ; P9LE: # %bb.0: # %entry
1886 ; P9LE-NEXT: lxv vs0, 0(r3)
1887 ; P9LE-NEXT: lxv vs1, 16(r3)
1888 ; P9LE-NEXT: xxmrgld vs2, vs1, vs0
1889 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
1890 ; P9LE-NEXT: xvcvdpsxws v2, vs2
1891 ; P9LE-NEXT: xvcvdpsxws v3, vs0
1892 ; P9LE-NEXT: vmrgew v2, v3, v2
1893 ; P9LE-NEXT: blr
1894 ;
1895 ; P8BE-LABEL: fromDiffMemConsAConvdtoi:
1896 ; P8BE: # %bb.0: # %entry
1897 ; P8BE-NEXT: li r4, 16
1898 ; P8BE-NEXT: lxvd2x vs0, 0, r3
1899 ; P8BE-NEXT: lxvd2x vs1, r3, r4
1900 ; P8BE-NEXT: xxmrgld vs2, vs0, vs1
1901 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
1902 ; P8BE-NEXT: xvcvdpsxws v2, vs2
1903 ; P8BE-NEXT: xvcvdpsxws v3, vs0
1904 ; P8BE-NEXT: vmrgew v2, v3, v2
1905 ; P8BE-NEXT: blr
1906 ;
1907 ; P8LE-LABEL: fromDiffMemConsAConvdtoi:
1908 ; P8LE: # %bb.0: # %entry
1909 ; P8LE-NEXT: li r4, 16
1910 ; P8LE-NEXT: lxvd2x vs0, 0, r3
1911 ; P8LE-NEXT: lxvd2x vs1, r3, r4
1912 ; P8LE-NEXT: xxswapd vs0, vs0
1913 ; P8LE-NEXT: xxswapd vs1, vs1
1914 ; P8LE-NEXT: xxmrgld vs2, vs1, vs0
1915 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
1916 ; P8LE-NEXT: xvcvdpsxws v2, vs2
1917 ; P8LE-NEXT: xvcvdpsxws v3, vs0
1918 ; P8LE-NEXT: vmrgew v2, v3, v2
1919 ; P8LE-NEXT: blr
1920 entry:
1921 %0 = load <2 x double>, ptr %ptr, align 8
1922 %1 = fptosi <2 x double> %0 to <2 x i32>
1923 %arrayidx4 = getelementptr inbounds double, ptr %ptr, i64 2
1924 %2 = load <2 x double>, ptr %arrayidx4, align 8
1925 %3 = fptosi <2 x double> %2 to <2 x i32>
1926 %vecinit9 = shufflevector <2 x i32> %1, <2 x i32> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1927 ret <4 x i32> %vecinit9
1928 }
1930 define <4 x i32> @fromDiffMemConsDConvdtoi(ptr nocapture readonly %ptr) {
1931 ; P9BE-LABEL: fromDiffMemConsDConvdtoi:
1932 ; P9BE: # %bb.0: # %entry
1933 ; P9BE-NEXT: lfd f0, 24(r3)
1934 ; P9BE-NEXT: lfd f1, 16(r3)
1935 ; P9BE-NEXT: lfd f2, 8(r3)
1936 ; P9BE-NEXT: xxmrghd vs0, vs0, vs2
1937 ; P9BE-NEXT: lfd f3, 0(r3)
1938 ; P9BE-NEXT: xxmrghd vs1, vs1, vs3
1939 ; P9BE-NEXT: xvcvdpsxws v2, vs1
1940 ; P9BE-NEXT: xvcvdpsxws v3, vs0
1941 ; P9BE-NEXT: vmrgew v2, v3, v2
1942 ; P9BE-NEXT: blr
1943 ;
1944 ; P9LE-LABEL: fromDiffMemConsDConvdtoi:
1945 ; P9LE: # %bb.0: # %entry
1946 ; P9LE-NEXT: lfd f0, 24(r3)
1947 ; P9LE-NEXT: lfd f2, 8(r3)
1948 ; P9LE-NEXT: xxmrghd vs0, vs2, vs0
1949 ; P9LE-NEXT: lfd f1, 16(r3)
1950 ; P9LE-NEXT: lfd f3, 0(r3)
1951 ; P9LE-NEXT: xvcvdpsxws v2, vs0
1952 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
1953 ; P9LE-NEXT: xvcvdpsxws v3, vs0
1954 ; P9LE-NEXT: vmrgew v2, v3, v2
1955 ; P9LE-NEXT: blr
1956 ;
1957 ; P8BE-LABEL: fromDiffMemConsDConvdtoi:
1958 ; P8BE: # %bb.0: # %entry
1959 ; P8BE-NEXT: lfd f0, 16(r3)
1960 ; P8BE-NEXT: lfd f1, 0(r3)
1961 ; P8BE-NEXT: lfd f2, 24(r3)
1962 ; P8BE-NEXT: lfd f3, 8(r3)
1963 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
1964 ; P8BE-NEXT: xxmrghd vs1, vs2, vs3
1965 ; P8BE-NEXT: xvcvdpsxws v2, vs0
1966 ; P8BE-NEXT: xvcvdpsxws v3, vs1
1967 ; P8BE-NEXT: vmrgew v2, v3, v2
1968 ; P8BE-NEXT: blr
1969 ;
1970 ; P8LE-LABEL: fromDiffMemConsDConvdtoi:
1971 ; P8LE: # %bb.0: # %entry
1972 ; P8LE-NEXT: lfd f0, 24(r3)
1973 ; P8LE-NEXT: lfd f1, 8(r3)
1974 ; P8LE-NEXT: lfd f2, 16(r3)
1975 ; P8LE-NEXT: lfd f3, 0(r3)
1976 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
1977 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2
1978 ; P8LE-NEXT: xvcvdpsxws v2, vs0
1979 ; P8LE-NEXT: xvcvdpsxws v3, vs1
1980 ; P8LE-NEXT: vmrgew v2, v3, v2
1981 ; P8LE-NEXT: blr
1982 entry:
1983 %arrayidx = getelementptr inbounds double, ptr %ptr, i64 3
1984 %0 = load double, ptr %arrayidx, align 8
1985 %conv = fptosi double %0 to i32
1986 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1987 %arrayidx1 = getelementptr inbounds double, ptr %ptr, i64 2
1988 %1 = load double, ptr %arrayidx1, align 8
1989 %conv2 = fptosi double %1 to i32
1990 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
1991 %arrayidx4 = getelementptr inbounds double, ptr %ptr, i64 1
1992 %2 = load double, ptr %arrayidx4, align 8
1993 %conv5 = fptosi double %2 to i32
1994 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
1995 %3 = load double, ptr %ptr, align 8
1996 %conv8 = fptosi double %3 to i32
1997 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
1998 ret <4 x i32> %vecinit9
1999 }
2001 define <4 x i32> @fromDiffMemVarAConvdtoi(ptr nocapture readonly %arr, i32 signext %elem) {
2002 ; P9BE-LABEL: fromDiffMemVarAConvdtoi:
2003 ; P9BE: # %bb.0: # %entry
2004 ; P9BE-NEXT: sldi r4, r4, 3
2005 ; P9BE-NEXT: lfdux f0, r3, r4
2006 ; P9BE-NEXT: lfd f1, 8(r3)
2007 ; P9BE-NEXT: lfd f2, 16(r3)
2008 ; P9BE-NEXT: lfd f3, 24(r3)
2009 ; P9BE-NEXT: xxmrghd vs1, vs1, vs3
2010 ; P9BE-NEXT: xxmrghd vs0, vs0, vs2
2011 ; P9BE-NEXT: xvcvdpsxws v2, vs1
2012 ; P9BE-NEXT: xvcvdpsxws v3, vs0
2013 ; P9BE-NEXT: vmrgew v2, v3, v2
2014 ; P9BE-NEXT: blr
2015 ;
2016 ; P9LE-LABEL: fromDiffMemVarAConvdtoi:
2017 ; P9LE: # %bb.0: # %entry
2018 ; P9LE-NEXT: sldi r4, r4, 3
2019 ; P9LE-NEXT: lfdux f0, r3, r4
2020 ; P9LE-NEXT: lfd f2, 16(r3)
2021 ; P9LE-NEXT: lfd f1, 8(r3)
2022 ; P9LE-NEXT: lfd f3, 24(r3)
2023 ; P9LE-NEXT: xxmrghd vs0, vs2, vs0
2024 ; P9LE-NEXT: xvcvdpsxws v2, vs0
2025 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
2026 ; P9LE-NEXT: xvcvdpsxws v3, vs0
2027 ; P9LE-NEXT: vmrgew v2, v3, v2
2028 ; P9LE-NEXT: blr
2029 ;
2030 ; P8BE-LABEL: fromDiffMemVarAConvdtoi:
2031 ; P8BE: # %bb.0: # %entry
2032 ; P8BE-NEXT: sldi r4, r4, 3
2033 ; P8BE-NEXT: lfdux f0, r3, r4
2034 ; P8BE-NEXT: lfd f1, 8(r3)
2035 ; P8BE-NEXT: lfd f2, 24(r3)
2036 ; P8BE-NEXT: lfd f3, 16(r3)
2037 ; P8BE-NEXT: xxmrghd vs1, vs1, vs2
2038 ; P8BE-NEXT: xxmrghd vs0, vs0, vs3
2039 ; P8BE-NEXT: xvcvdpsxws v2, vs1
2040 ; P8BE-NEXT: xvcvdpsxws v3, vs0
2041 ; P8BE-NEXT: vmrgew v2, v3, v2
2042 ; P8BE-NEXT: blr
2043 ;
2044 ; P8LE-LABEL: fromDiffMemVarAConvdtoi:
2045 ; P8LE: # %bb.0: # %entry
2046 ; P8LE-NEXT: sldi r4, r4, 3
2047 ; P8LE-NEXT: lfdux f0, r3, r4
2048 ; P8LE-NEXT: lfd f1, 16(r3)
2049 ; P8LE-NEXT: lfd f2, 8(r3)
2050 ; P8LE-NEXT: lfd f3, 24(r3)
2051 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
2052 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2
2053 ; P8LE-NEXT: xvcvdpsxws v2, vs0
2054 ; P8LE-NEXT: xvcvdpsxws v3, vs1
2055 ; P8LE-NEXT: vmrgew v2, v3, v2
2056 ; P8LE-NEXT: blr
2057 entry:
2058 %idxprom = sext i32 %elem to i64
2059 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom
2060 %0 = load double, ptr %arrayidx, align 8
2061 %conv = fptosi double %0 to i32
2062 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
2063 %add = add nsw i32 %elem, 1
2064 %idxprom1 = sext i32 %add to i64
2065 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1
2066 %1 = load double, ptr %arrayidx2, align 8
2067 %conv3 = fptosi double %1 to i32
2068 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
2069 %add5 = add nsw i32 %elem, 2
2070 %idxprom6 = sext i32 %add5 to i64
2071 %arrayidx7 = getelementptr inbounds double, ptr %arr, i64 %idxprom6
2072 %2 = load double, ptr %arrayidx7, align 8
2073 %conv8 = fptosi double %2 to i32
2074 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
2075 %add10 = add nsw i32 %elem, 3
2076 %idxprom11 = sext i32 %add10 to i64
2077 %arrayidx12 = getelementptr inbounds double, ptr %arr, i64 %idxprom11
2078 %3 = load double, ptr %arrayidx12, align 8
2079 %conv13 = fptosi double %3 to i32
2080 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
2081 ret <4 x i32> %vecinit14
2082 }
2084 define <4 x i32> @fromDiffMemVarDConvdtoi(ptr nocapture readonly %arr, i32 signext %elem) {
2085 ; P9BE-LABEL: fromDiffMemVarDConvdtoi:
2086 ; P9BE: # %bb.0: # %entry
2087 ; P9BE-NEXT: sldi r4, r4, 3
2088 ; P9BE-NEXT: lfdux f0, r3, r4
2089 ; P9BE-NEXT: lfd f1, -8(r3)
2090 ; P9BE-NEXT: lfd f2, -16(r3)
2091 ; P9BE-NEXT: lfd f3, -24(r3)
2092 ; P9BE-NEXT: xxmrghd vs1, vs1, vs3
2093 ; P9BE-NEXT: xxmrghd vs0, vs0, vs2
2094 ; P9BE-NEXT: xvcvdpsxws v2, vs1
2095 ; P9BE-NEXT: xvcvdpsxws v3, vs0
2096 ; P9BE-NEXT: vmrgew v2, v3, v2
2097 ; P9BE-NEXT: blr
2098 ;
2099 ; P9LE-LABEL: fromDiffMemVarDConvdtoi:
2100 ; P9LE: # %bb.0: # %entry
2101 ; P9LE-NEXT: sldi r4, r4, 3
2102 ; P9LE-NEXT: lfdux f0, r3, r4
2103 ; P9LE-NEXT: lfd f2, -16(r3)
2104 ; P9LE-NEXT: lfd f1, -8(r3)
2105 ; P9LE-NEXT: lfd f3, -24(r3)
2106 ; P9LE-NEXT: xxmrghd vs0, vs2, vs0
2107 ; P9LE-NEXT: xvcvdpsxws v2, vs0
2108 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
2109 ; P9LE-NEXT: xvcvdpsxws v3, vs0
2110 ; P9LE-NEXT: vmrgew v2, v3, v2
2111 ; P9LE-NEXT: blr
2112 ;
2113 ; P8BE-LABEL: fromDiffMemVarDConvdtoi:
2114 ; P8BE: # %bb.0: # %entry
2115 ; P8BE-NEXT: sldi r4, r4, 3
2116 ; P8BE-NEXT: lfdux f0, r3, r4
2117 ; P8BE-NEXT: lfd f1, -8(r3)
2118 ; P8BE-NEXT: lfd f2, -24(r3)
2119 ; P8BE-NEXT: lfd f3, -16(r3)
2120 ; P8BE-NEXT: xxmrghd vs1, vs1, vs2
2121 ; P8BE-NEXT: xxmrghd vs0, vs0, vs3
2122 ; P8BE-NEXT: xvcvdpsxws v2, vs1
2123 ; P8BE-NEXT: xvcvdpsxws v3, vs0
2124 ; P8BE-NEXT: vmrgew v2, v3, v2
2125 ; P8BE-NEXT: blr
2126 ;
2127 ; P8LE-LABEL: fromDiffMemVarDConvdtoi:
2128 ; P8LE: # %bb.0: # %entry
2129 ; P8LE-NEXT: sldi r4, r4, 3
2130 ; P8LE-NEXT: lfdux f0, r3, r4
2131 ; P8LE-NEXT: lfd f1, -16(r3)
2132 ; P8LE-NEXT: lfd f2, -8(r3)
2133 ; P8LE-NEXT: lfd f3, -24(r3)
2134 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
2135 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2
2136 ; P8LE-NEXT: xvcvdpsxws v2, vs0
2137 ; P8LE-NEXT: xvcvdpsxws v3, vs1
2138 ; P8LE-NEXT: vmrgew v2, v3, v2
2139 ; P8LE-NEXT: blr
2140 entry:
2141 %idxprom = sext i32 %elem to i64
2142 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom
2143 %0 = load double, ptr %arrayidx, align 8
2144 %conv = fptosi double %0 to i32
2145 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
2146 %sub = add nsw i32 %elem, -1
2147 %idxprom1 = sext i32 %sub to i64
2148 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1
2149 %1 = load double, ptr %arrayidx2, align 8
2150 %conv3 = fptosi double %1 to i32
2151 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
2152 %sub5 = add nsw i32 %elem, -2
2153 %idxprom6 = sext i32 %sub5 to i64
2154 %arrayidx7 = getelementptr inbounds double, ptr %arr, i64 %idxprom6
2155 %2 = load double, ptr %arrayidx7, align 8
2156 %conv8 = fptosi double %2 to i32
2157 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
2158 %sub10 = add nsw i32 %elem, -3
2159 %idxprom11 = sext i32 %sub10 to i64
2160 %arrayidx12 = getelementptr inbounds double, ptr %arr, i64 %idxprom11
2161 %3 = load double, ptr %arrayidx12, align 8
2162 %conv13 = fptosi double %3 to i32
2163 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
2164 ret <4 x i32> %vecinit14
2165 }
2167 define <4 x i32> @spltRegValConvdtoi(double %val) {
2168 ; P9BE-LABEL: spltRegValConvdtoi:
2169 ; P9BE: # %bb.0: # %entry
2170 ; P9BE-NEXT: xscvdpsxws f0, f1
2171 ; P9BE-NEXT: xxspltw v2, vs0, 1
2172 ; P9BE-NEXT: blr
2173 ;
2174 ; P9LE-LABEL: spltRegValConvdtoi:
2175 ; P9LE: # %bb.0: # %entry
2176 ; P9LE-NEXT: xscvdpsxws f0, f1
2177 ; P9LE-NEXT: xxspltw v2, vs0, 1
2178 ; P9LE-NEXT: blr
2179 ;
2180 ; P8BE-LABEL: spltRegValConvdtoi:
2181 ; P8BE: # %bb.0: # %entry
2182 ; P8BE-NEXT: xscvdpsxws f0, f1
2183 ; P8BE-NEXT: xxspltw v2, vs0, 1
2184 ; P8BE-NEXT: blr
2185 ;
2186 ; P8LE-LABEL: spltRegValConvdtoi:
2187 ; P8LE: # %bb.0: # %entry
2188 ; P8LE-NEXT: xscvdpsxws f0, f1
2189 ; P8LE-NEXT: xxspltw v2, vs0, 1
2190 ; P8LE-NEXT: blr
2191 entry:
2192 %conv = fptosi double %val to i32
2193 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
2194 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
2195 ret <4 x i32> %splat.splat
2196 }
2198 define <4 x i32> @spltMemValConvdtoi(ptr nocapture readonly %ptr) {
2199 ; P9BE-LABEL: spltMemValConvdtoi:
2200 ; P9BE: # %bb.0: # %entry
2201 ; P9BE-NEXT: lfd f0, 0(r3)
2202 ; P9BE-NEXT: xscvdpsxws f0, f0
2203 ; P9BE-NEXT: xxspltw v2, vs0, 1
2204 ; P9BE-NEXT: blr
2205 ;
2206 ; P9LE-LABEL: spltMemValConvdtoi:
2207 ; P9LE: # %bb.0: # %entry
2208 ; P9LE-NEXT: lfd f0, 0(r3)
2209 ; P9LE-NEXT: xscvdpsxws f0, f0
2210 ; P9LE-NEXT: xxspltw v2, vs0, 1
2211 ; P9LE-NEXT: blr
2212 ;
2213 ; P8BE-LABEL: spltMemValConvdtoi:
2214 ; P8BE: # %bb.0: # %entry
2215 ; P8BE-NEXT: lfdx f0, 0, r3
2216 ; P8BE-NEXT: xscvdpsxws f0, f0
2217 ; P8BE-NEXT: xxspltw v2, vs0, 1
2218 ; P8BE-NEXT: blr
2219 ;
2220 ; P8LE-LABEL: spltMemValConvdtoi:
2221 ; P8LE: # %bb.0: # %entry
2222 ; P8LE-NEXT: lfdx f0, 0, r3
2223 ; P8LE-NEXT: xscvdpsxws f0, f0
2224 ; P8LE-NEXT: xxspltw v2, vs0, 1
2225 ; P8LE-NEXT: blr
2226 entry:
2227 %0 = load double, ptr %ptr, align 8
2228 %conv = fptosi double %0 to i32
2229 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
2230 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
2231 ret <4 x i32> %splat.splat
2232 }
2234 define <4 x i32> @allZeroui() {
2235 ; P9BE-LABEL: allZeroui:
2236 ; P9BE: # %bb.0: # %entry
2237 ; P9BE-NEXT: xxlxor v2, v2, v2
2238 ; P9BE-NEXT: blr
2239 ;
2240 ; P9LE-LABEL: allZeroui:
2241 ; P9LE: # %bb.0: # %entry
2242 ; P9LE-NEXT: xxlxor v2, v2, v2
2243 ; P9LE-NEXT: blr
2244 ;
2245 ; P8BE-LABEL: allZeroui:
2246 ; P8BE: # %bb.0: # %entry
2247 ; P8BE-NEXT: xxlxor v2, v2, v2
2248 ; P8BE-NEXT: blr
2249 ;
2250 ; P8LE-LABEL: allZeroui:
2251 ; P8LE: # %bb.0: # %entry
2252 ; P8LE-NEXT: xxlxor v2, v2, v2
2253 ; P8LE-NEXT: blr
2254 entry:
2255 ret <4 x i32> zeroinitializer
2256 }
2258 define <4 x i32> @spltConst1ui() {
2259 ; P9BE-LABEL: spltConst1ui:
2260 ; P9BE: # %bb.0: # %entry
2261 ; P9BE-NEXT: vspltisw v2, 1
2262 ; P9BE-NEXT: blr
2263 ;
2264 ; P9LE-LABEL: spltConst1ui:
2265 ; P9LE: # %bb.0: # %entry
2266 ; P9LE-NEXT: vspltisw v2, 1
2267 ; P9LE-NEXT: blr
2268 ;
2269 ; P8BE-LABEL: spltConst1ui:
2270 ; P8BE: # %bb.0: # %entry
2271 ; P8BE-NEXT: vspltisw v2, 1
2272 ; P8BE-NEXT: blr
2273 ;
2274 ; P8LE-LABEL: spltConst1ui:
2275 ; P8LE: # %bb.0: # %entry
2276 ; P8LE-NEXT: vspltisw v2, 1
2277 ; P8LE-NEXT: blr
2278 entry:
2279 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1>
2280 }
2282 define <4 x i32> @spltConst16kui() {
2283 ; P9BE-LABEL: spltConst16kui:
2284 ; P9BE: # %bb.0: # %entry
2285 ; P9BE-NEXT: vspltisw v2, -15
2286 ; P9BE-NEXT: vsrw v2, v2, v2
2287 ; P9BE-NEXT: blr
2288 ;
2289 ; P9LE-LABEL: spltConst16kui:
2290 ; P9LE: # %bb.0: # %entry
2291 ; P9LE-NEXT: vspltisw v2, -15
2292 ; P9LE-NEXT: vsrw v2, v2, v2
2293 ; P9LE-NEXT: blr
2294 ;
2295 ; P8BE-LABEL: spltConst16kui:
2296 ; P8BE: # %bb.0: # %entry
2297 ; P8BE-NEXT: vspltisw v2, -15
2298 ; P8BE-NEXT: vsrw v2, v2, v2
2299 ; P8BE-NEXT: blr
2300 ;
2301 ; P8LE-LABEL: spltConst16kui:
2302 ; P8LE: # %bb.0: # %entry
2303 ; P8LE-NEXT: vspltisw v2, -15
2304 ; P8LE-NEXT: vsrw v2, v2, v2
2305 ; P8LE-NEXT: blr
2306 entry:
2307 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
2308 }
2310 define <4 x i32> @spltConst32kui() {
2311 ; P9BE-LABEL: spltConst32kui:
2312 ; P9BE: # %bb.0: # %entry
2313 ; P9BE-NEXT: vspltisw v2, -16
2314 ; P9BE-NEXT: vsrw v2, v2, v2
2315 ; P9BE-NEXT: blr
2316 ;
2317 ; P9LE-LABEL: spltConst32kui:
2318 ; P9LE: # %bb.0: # %entry
2319 ; P9LE-NEXT: vspltisw v2, -16
2320 ; P9LE-NEXT: vsrw v2, v2, v2
2321 ; P9LE-NEXT: blr
2322 ;
2323 ; P8BE-LABEL: spltConst32kui:
2324 ; P8BE: # %bb.0: # %entry
2325 ; P8BE-NEXT: vspltisw v2, -16
2326 ; P8BE-NEXT: vsrw v2, v2, v2
2327 ; P8BE-NEXT: blr
2328 ;
2329 ; P8LE-LABEL: spltConst32kui:
2330 ; P8LE: # %bb.0: # %entry
2331 ; P8LE-NEXT: vspltisw v2, -16
2332 ; P8LE-NEXT: vsrw v2, v2, v2
2333 ; P8LE-NEXT: blr
2334 entry:
2335 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
2336 }
2338 define <4 x i32> @fromRegsui(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c, i32 zeroext %d) {
2339 ; P9BE-LABEL: fromRegsui:
2340 ; P9BE: # %bb.0: # %entry
2341 ; P9BE-NEXT: rldimi r6, r5, 32, 0
2342 ; P9BE-NEXT: rldimi r4, r3, 32, 0
2343 ; P9BE-NEXT: mtvsrdd v2, r4, r6
2344 ; P9BE-NEXT: blr
2345 ;
2346 ; P9LE-LABEL: fromRegsui:
2347 ; P9LE: # %bb.0: # %entry
2348 ; P9LE-NEXT: rldimi r3, r4, 32, 0
2349 ; P9LE-NEXT: rldimi r5, r6, 32, 0
2350 ; P9LE-NEXT: mtvsrdd v2, r5, r3
2351 ; P9LE-NEXT: blr
2352 ;
2353 ; P8BE-LABEL: fromRegsui:
2354 ; P8BE: # %bb.0: # %entry
2355 ; P8BE-NEXT: rldimi r6, r5, 32, 0
2356 ; P8BE-NEXT: rldimi r4, r3, 32, 0
2357 ; P8BE-NEXT: mtfprd f0, r6
2358 ; P8BE-NEXT: mtfprd f1, r4
2359 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
2360 ; P8BE-NEXT: blr
2361 ;
2362 ; P8LE-LABEL: fromRegsui:
2363 ; P8LE: # %bb.0: # %entry
2364 ; P8LE-NEXT: rldimi r3, r4, 32, 0
2365 ; P8LE-NEXT: rldimi r5, r6, 32, 0
2366 ; P8LE-NEXT: mtfprd f0, r3
2367 ; P8LE-NEXT: mtfprd f1, r5
2368 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
2369 ; P8LE-NEXT: blr
2370 entry:
2371 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0
2372 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
2373 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2
2374 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3
2375 ret <4 x i32> %vecinit3
2376 }
2378 define <4 x i32> @fromDiffConstsui() {
2379 ; P9BE-LABEL: fromDiffConstsui:
2380 ; P9BE: # %bb.0: # %entry
2381 ; P9BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha
2382 ; P9BE-NEXT: addi r3, r3, .LCPI37_0@toc@l
2383 ; P9BE-NEXT: lxv v2, 0(r3)
2384 ; P9BE-NEXT: blr
2385 ;
2386 ; P9LE-LABEL: fromDiffConstsui:
2387 ; P9LE: # %bb.0: # %entry
2388 ; P9LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha
2389 ; P9LE-NEXT: addi r3, r3, .LCPI37_0@toc@l
2390 ; P9LE-NEXT: lxv v2, 0(r3)
2391 ; P9LE-NEXT: blr
2392 ;
2393 ; P8BE-LABEL: fromDiffConstsui:
2394 ; P8BE: # %bb.0: # %entry
2395 ; P8BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha
2396 ; P8BE-NEXT: addi r3, r3, .LCPI37_0@toc@l
2397 ; P8BE-NEXT: lxvw4x v2, 0, r3
2398 ; P8BE-NEXT: blr
2399 ;
2400 ; P8LE-LABEL: fromDiffConstsui:
2401 ; P8LE: # %bb.0: # %entry
2402 ; P8LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha
2403 ; P8LE-NEXT: addi r3, r3, .LCPI37_0@toc@l
2404 ; P8LE-NEXT: lxvd2x vs0, 0, r3
2405 ; P8LE-NEXT: xxswapd v2, vs0
2406 ; P8LE-NEXT: blr
2407 entry:
2408 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19>
2409 }
2411 define <4 x i32> @fromDiffMemConsAui(ptr nocapture readonly %arr) {
2412 ; P9BE-LABEL: fromDiffMemConsAui:
2413 ; P9BE: # %bb.0: # %entry
2414 ; P9BE-NEXT: lxv v2, 0(r3)
2415 ; P9BE-NEXT: blr
2416 ;
2417 ; P9LE-LABEL: fromDiffMemConsAui:
2418 ; P9LE: # %bb.0: # %entry
2419 ; P9LE-NEXT: lxv v2, 0(r3)
2420 ; P9LE-NEXT: blr
2421 ;
2422 ; P8BE-LABEL: fromDiffMemConsAui:
2423 ; P8BE: # %bb.0: # %entry
2424 ; P8BE-NEXT: lxvw4x v2, 0, r3
2425 ; P8BE-NEXT: blr
2426 ;
2427 ; P8LE-LABEL: fromDiffMemConsAui:
2428 ; P8LE: # %bb.0: # %entry
2429 ; P8LE-NEXT: lxvd2x vs0, 0, r3
2430 ; P8LE-NEXT: xxswapd v2, vs0
2431 ; P8LE-NEXT: blr
2432 entry:
2433 %0 = load i32, ptr %arr, align 4
2434 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2435 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 1
2436 %1 = load i32, ptr %arrayidx1, align 4
2437 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2438 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 2
2439 %2 = load i32, ptr %arrayidx3, align 4
2440 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
2441 %arrayidx5 = getelementptr inbounds i32, ptr %arr, i64 3
2442 %3 = load i32, ptr %arrayidx5, align 4
2443 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
2444 ret <4 x i32> %vecinit6
2445 }
2447 define <4 x i32> @fromDiffMemConsDui(ptr nocapture readonly %arr) {
2448 ; P9BE-LABEL: fromDiffMemConsDui:
2449 ; P9BE: # %bb.0: # %entry
2450 ; P9BE-NEXT: lxv v2, 0(r3)
2451 ; P9BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha
2452 ; P9BE-NEXT: addi r3, r3, .LCPI39_0@toc@l
2453 ; P9BE-NEXT: lxv vs0, 0(r3)
2454 ; P9BE-NEXT: xxperm v2, v2, vs0
2455 ; P9BE-NEXT: blr
2456 ;
2457 ; P9LE-LABEL: fromDiffMemConsDui:
2458 ; P9LE: # %bb.0: # %entry
2459 ; P9LE-NEXT: lxvw4x v2, 0, r3
2460 ; P9LE-NEXT: blr
2461 ;
2462 ; P8BE-LABEL: fromDiffMemConsDui:
2463 ; P8BE: # %bb.0: # %entry
2464 ; P8BE-NEXT: addis r4, r2, .LCPI39_0@toc@ha
2465 ; P8BE-NEXT: lxvw4x v2, 0, r3
2466 ; P8BE-NEXT: addi r4, r4, .LCPI39_0@toc@l
2467 ; P8BE-NEXT: lxvw4x v3, 0, r4
2468 ; P8BE-NEXT: vperm v2, v2, v2, v3
2469 ; P8BE-NEXT: blr
2470 ;
2471 ; P8LE-LABEL: fromDiffMemConsDui:
2472 ; P8LE: # %bb.0: # %entry
2473 ; P8LE-NEXT: addis r4, r2, .LCPI39_0@toc@ha
2474 ; P8LE-NEXT: lxvd2x vs0, 0, r3
2475 ; P8LE-NEXT: addi r4, r4, .LCPI39_0@toc@l
2476 ; P8LE-NEXT: lxvd2x vs1, 0, r4
2477 ; P8LE-NEXT: xxswapd v2, vs0
2478 ; P8LE-NEXT: xxswapd v3, vs1
2479 ; P8LE-NEXT: vperm v2, v2, v2, v3
2480 ; P8LE-NEXT: blr
2481 entry:
2482 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 3
2483 %0 = load i32, ptr %arrayidx, align 4
2484 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2485 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 2
2486 %1 = load i32, ptr %arrayidx1, align 4
2487 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2488 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 1
2489 %2 = load i32, ptr %arrayidx3, align 4
2490 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
2491 %3 = load i32, ptr %arr, align 4
2492 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
2493 ret <4 x i32> %vecinit6
2494 }
2496 define <4 x i32> @fromDiffMemVarAui(ptr nocapture readonly %arr, i32 signext %elem) {
2497 ; P9BE-LABEL: fromDiffMemVarAui:
2498 ; P9BE: # %bb.0: # %entry
2499 ; P9BE-NEXT: sldi r4, r4, 2
2500 ; P9BE-NEXT: lxvx v2, r3, r4
2501 ; P9BE-NEXT: blr
2502 ;
2503 ; P9LE-LABEL: fromDiffMemVarAui:
2504 ; P9LE: # %bb.0: # %entry
2505 ; P9LE-NEXT: sldi r4, r4, 2
2506 ; P9LE-NEXT: lxvx v2, r3, r4
2507 ; P9LE-NEXT: blr
2508 ;
2509 ; P8BE-LABEL: fromDiffMemVarAui:
2510 ; P8BE: # %bb.0: # %entry
2511 ; P8BE-NEXT: sldi r4, r4, 2
2512 ; P8BE-NEXT: lxvw4x v2, r3, r4
2513 ; P8BE-NEXT: blr
2514 ;
2515 ; P8LE-LABEL: fromDiffMemVarAui:
2516 ; P8LE: # %bb.0: # %entry
2517 ; P8LE-NEXT: sldi r4, r4, 2
2518 ; P8LE-NEXT: lxvd2x vs0, r3, r4
2519 ; P8LE-NEXT: xxswapd v2, vs0
2520 ; P8LE-NEXT: blr
2521 entry:
2522 %idxprom = sext i32 %elem to i64
2523 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom
2524 %0 = load i32, ptr %arrayidx, align 4
2525 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2526 %add = add nsw i32 %elem, 1
2527 %idxprom1 = sext i32 %add to i64
2528 %arrayidx2 = getelementptr inbounds i32, ptr %arr, i64 %idxprom1
2529 %1 = load i32, ptr %arrayidx2, align 4
2530 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2531 %add4 = add nsw i32 %elem, 2
2532 %idxprom5 = sext i32 %add4 to i64
2533 %arrayidx6 = getelementptr inbounds i32, ptr %arr, i64 %idxprom5
2534 %2 = load i32, ptr %arrayidx6, align 4
2535 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2
2536 %add8 = add nsw i32 %elem, 3
2537 %idxprom9 = sext i32 %add8 to i64
2538 %arrayidx10 = getelementptr inbounds i32, ptr %arr, i64 %idxprom9
2539 %3 = load i32, ptr %arrayidx10, align 4
2540 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3
2541 ret <4 x i32> %vecinit11
2542 }
2544 define <4 x i32> @fromDiffMemVarDui(ptr nocapture readonly %arr, i32 signext %elem) {
2545 ; P9BE-LABEL: fromDiffMemVarDui:
2546 ; P9BE: # %bb.0: # %entry
2547 ; P9BE-NEXT: sldi r4, r4, 2
2548 ; P9BE-NEXT: add r3, r3, r4
2549 ; P9BE-NEXT: li r4, -12
2550 ; P9BE-NEXT: lxvx v2, r3, r4
2551 ; P9BE-NEXT: addis r3, r2, .LCPI41_0@toc@ha
2552 ; P9BE-NEXT: addi r3, r3, .LCPI41_0@toc@l
2553 ; P9BE-NEXT: lxv vs0, 0(r3)
2554 ; P9BE-NEXT: xxperm v2, v2, vs0
2555 ; P9BE-NEXT: blr
2556 ;
2557 ; P9LE-LABEL: fromDiffMemVarDui:
2558 ; P9LE: # %bb.0: # %entry
2559 ; P9LE-NEXT: sldi r4, r4, 2
2560 ; P9LE-NEXT: add r3, r3, r4
2561 ; P9LE-NEXT: li r4, -12
2562 ; P9LE-NEXT: lxvx v2, r3, r4
2563 ; P9LE-NEXT: addis r3, r2, .LCPI41_0@toc@ha
2564 ; P9LE-NEXT: addi r3, r3, .LCPI41_0@toc@l
2565 ; P9LE-NEXT: lxv vs0, 0(r3)
2566 ; P9LE-NEXT: xxperm v2, v2, vs0
2567 ; P9LE-NEXT: blr
2568 ;
2569 ; P8BE-LABEL: fromDiffMemVarDui:
2570 ; P8BE: # %bb.0: # %entry
2571 ; P8BE-NEXT: sldi r4, r4, 2
2572 ; P8BE-NEXT: addis r5, r2, .LCPI41_0@toc@ha
2573 ; P8BE-NEXT: add r3, r3, r4
2574 ; P8BE-NEXT: addi r4, r5, .LCPI41_0@toc@l
2575 ; P8BE-NEXT: addi r3, r3, -12
2576 ; P8BE-NEXT: lxvw4x v3, 0, r4
2577 ; P8BE-NEXT: lxvw4x v2, 0, r3
2578 ; P8BE-NEXT: vperm v2, v2, v2, v3
2579 ; P8BE-NEXT: blr
2580 ;
2581 ; P8LE-LABEL: fromDiffMemVarDui:
2582 ; P8LE: # %bb.0: # %entry
2583 ; P8LE-NEXT: sldi r4, r4, 2
2584 ; P8LE-NEXT: addis r5, r2, .LCPI41_0@toc@ha
2585 ; P8LE-NEXT: add r3, r3, r4
2586 ; P8LE-NEXT: addi r4, r5, .LCPI41_0@toc@l
2587 ; P8LE-NEXT: addi r3, r3, -12
2588 ; P8LE-NEXT: lxvd2x vs1, 0, r4
2589 ; P8LE-NEXT: lxvd2x vs0, 0, r3
2590 ; P8LE-NEXT: xxswapd v3, vs1
2591 ; P8LE-NEXT: xxswapd v2, vs0
2592 ; P8LE-NEXT: vperm v2, v2, v2, v3
2593 ; P8LE-NEXT: blr
2594 entry:
2595 %idxprom = sext i32 %elem to i64
2596 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom
2597 %0 = load i32, ptr %arrayidx, align 4
2598 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2599 %sub = add nsw i32 %elem, -1
2600 %idxprom1 = sext i32 %sub to i64
2601 %arrayidx2 = getelementptr inbounds i32, ptr %arr, i64 %idxprom1
2602 %1 = load i32, ptr %arrayidx2, align 4
2603 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2604 %sub4 = add nsw i32 %elem, -2
2605 %idxprom5 = sext i32 %sub4 to i64
2606 %arrayidx6 = getelementptr inbounds i32, ptr %arr, i64 %idxprom5
2607 %2 = load i32, ptr %arrayidx6, align 4
2608 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2
2609 %sub8 = add nsw i32 %elem, -3
2610 %idxprom9 = sext i32 %sub8 to i64
2611 %arrayidx10 = getelementptr inbounds i32, ptr %arr, i64 %idxprom9
2612 %3 = load i32, ptr %arrayidx10, align 4
2613 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3
2614 ret <4 x i32> %vecinit11
2615 }
2617 define <4 x i32> @fromRandMemConsui(ptr nocapture readonly %arr) {
2618 ; P9BE-LABEL: fromRandMemConsui:
2619 ; P9BE: # %bb.0: # %entry
2620 ; P9BE-NEXT: lwz r4, 16(r3)
2621 ; P9BE-NEXT: lwz r5, 72(r3)
2622 ; P9BE-NEXT: lwz r6, 8(r3)
2623 ; P9BE-NEXT: lwz r3, 352(r3)
2624 ; P9BE-NEXT: rldimi r3, r6, 32, 0
2625 ; P9BE-NEXT: rldimi r5, r4, 32, 0
2626 ; P9BE-NEXT: mtvsrdd v2, r5, r3
2627 ; P9BE-NEXT: blr
2628 ;
2629 ; P9LE-LABEL: fromRandMemConsui:
2630 ; P9LE: # %bb.0: # %entry
2631 ; P9LE-NEXT: lwz r4, 16(r3)
2632 ; P9LE-NEXT: lwz r5, 72(r3)
2633 ; P9LE-NEXT: lwz r6, 8(r3)
2634 ; P9LE-NEXT: lwz r3, 352(r3)
2635 ; P9LE-NEXT: rldimi r4, r5, 32, 0
2636 ; P9LE-NEXT: rldimi r6, r3, 32, 0
2637 ; P9LE-NEXT: mtvsrdd v2, r6, r4
2638 ; P9LE-NEXT: blr
2639 ;
2640 ; P8BE-LABEL: fromRandMemConsui:
2641 ; P8BE: # %bb.0: # %entry
2642 ; P8BE-NEXT: lwz r4, 8(r3)
2643 ; P8BE-NEXT: lwz r5, 352(r3)
2644 ; P8BE-NEXT: lwz r6, 16(r3)
2645 ; P8BE-NEXT: lwz r3, 72(r3)
2646 ; P8BE-NEXT: rldimi r5, r4, 32, 0
2647 ; P8BE-NEXT: rldimi r3, r6, 32, 0
2648 ; P8BE-NEXT: mtfprd f0, r5
2649 ; P8BE-NEXT: mtfprd f1, r3
2650 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
2651 ; P8BE-NEXT: blr
2652 ;
2653 ; P8LE-LABEL: fromRandMemConsui:
2654 ; P8LE: # %bb.0: # %entry
2655 ; P8LE-NEXT: lwz r4, 16(r3)
2656 ; P8LE-NEXT: lwz r5, 72(r3)
2657 ; P8LE-NEXT: lwz r6, 8(r3)
2658 ; P8LE-NEXT: lwz r3, 352(r3)
2659 ; P8LE-NEXT: rldimi r4, r5, 32, 0
2660 ; P8LE-NEXT: rldimi r6, r3, 32, 0
2661 ; P8LE-NEXT: mtfprd f0, r4
2662 ; P8LE-NEXT: mtfprd f1, r6
2663 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
2664 ; P8LE-NEXT: blr
2665 entry:
2666 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 4
2667 %0 = load i32, ptr %arrayidx, align 4
2668 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2669 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 18
2670 %1 = load i32, ptr %arrayidx1, align 4
2671 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2672 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 2
2673 %2 = load i32, ptr %arrayidx3, align 4
2674 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
2675 %arrayidx5 = getelementptr inbounds i32, ptr %arr, i64 88
2676 %3 = load i32, ptr %arrayidx5, align 4
2677 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
2678 ret <4 x i32> %vecinit6
2679 }
2681 define <4 x i32> @fromRandMemVarui(ptr nocapture readonly %arr, i32 signext %elem) {
2682 ; P9BE-LABEL: fromRandMemVarui:
2683 ; P9BE: # %bb.0: # %entry
2684 ; P9BE-NEXT: sldi r4, r4, 2
2685 ; P9BE-NEXT: add r3, r3, r4
2686 ; P9BE-NEXT: lwz r4, 16(r3)
2687 ; P9BE-NEXT: lwz r5, 4(r3)
2688 ; P9BE-NEXT: lwz r6, 8(r3)
2689 ; P9BE-NEXT: lwz r3, 32(r3)
2690 ; P9BE-NEXT: rldimi r3, r6, 32, 0
2691 ; P9BE-NEXT: rldimi r5, r4, 32, 0
2692 ; P9BE-NEXT: mtvsrdd v2, r5, r3
2693 ; P9BE-NEXT: blr
2694 ;
2695 ; P9LE-LABEL: fromRandMemVarui:
2696 ; P9LE: # %bb.0: # %entry
2697 ; P9LE-NEXT: sldi r4, r4, 2
2698 ; P9LE-NEXT: add r3, r3, r4
2699 ; P9LE-NEXT: lwz r4, 16(r3)
2700 ; P9LE-NEXT: lwz r5, 4(r3)
2701 ; P9LE-NEXT: lwz r6, 8(r3)
2702 ; P9LE-NEXT: lwz r3, 32(r3)
2703 ; P9LE-NEXT: rldimi r4, r5, 32, 0
2704 ; P9LE-NEXT: rldimi r6, r3, 32, 0
2705 ; P9LE-NEXT: mtvsrdd v2, r6, r4
2706 ; P9LE-NEXT: blr
2707 ;
2708 ; P8BE-LABEL: fromRandMemVarui:
2709 ; P8BE: # %bb.0: # %entry
2710 ; P8BE-NEXT: sldi r4, r4, 2
2711 ; P8BE-NEXT: add r3, r3, r4
2712 ; P8BE-NEXT: lwz r4, 8(r3)
2713 ; P8BE-NEXT: lwz r5, 32(r3)
2714 ; P8BE-NEXT: lwz r6, 16(r3)
2715 ; P8BE-NEXT: lwz r3, 4(r3)
2716 ; P8BE-NEXT: rldimi r5, r4, 32, 0
2717 ; P8BE-NEXT: rldimi r3, r6, 32, 0
2718 ; P8BE-NEXT: mtfprd f0, r5
2719 ; P8BE-NEXT: mtfprd f1, r3
2720 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
2721 ; P8BE-NEXT: blr
2722 ;
2723 ; P8LE-LABEL: fromRandMemVarui:
2724 ; P8LE: # %bb.0: # %entry
2725 ; P8LE-NEXT: sldi r4, r4, 2
2726 ; P8LE-NEXT: add r3, r3, r4
2727 ; P8LE-NEXT: lwz r4, 16(r3)
2728 ; P8LE-NEXT: lwz r5, 4(r3)
2729 ; P8LE-NEXT: lwz r6, 8(r3)
2730 ; P8LE-NEXT: lwz r3, 32(r3)
2731 ; P8LE-NEXT: rldimi r4, r5, 32, 0
2732 ; P8LE-NEXT: rldimi r6, r3, 32, 0
2733 ; P8LE-NEXT: mtfprd f0, r4
2734 ; P8LE-NEXT: mtfprd f1, r6
2735 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
2736 ; P8LE-NEXT: blr
2737 entry:
2738 %add = add nsw i32 %elem, 4
2739 %idxprom = sext i32 %add to i64
2740 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom
2741 %0 = load i32, ptr %arrayidx, align 4
2742 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2743 %add1 = add nsw i32 %elem, 1
2744 %idxprom2 = sext i32 %add1 to i64
2745 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 %idxprom2
2746 %1 = load i32, ptr %arrayidx3, align 4
2747 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2748 %add5 = add nsw i32 %elem, 2
2749 %idxprom6 = sext i32 %add5 to i64
2750 %arrayidx7 = getelementptr inbounds i32, ptr %arr, i64 %idxprom6
2751 %2 = load i32, ptr %arrayidx7, align 4
2752 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2
2753 %add9 = add nsw i32 %elem, 8
2754 %idxprom10 = sext i32 %add9 to i64
2755 %arrayidx11 = getelementptr inbounds i32, ptr %arr, i64 %idxprom10
2756 %3 = load i32, ptr %arrayidx11, align 4
2757 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3
2758 ret <4 x i32> %vecinit12
2759 }
2761 define <4 x i32> @spltRegValui(i32 zeroext %val) {
2762 ; P9BE-LABEL: spltRegValui:
2763 ; P9BE: # %bb.0: # %entry
2764 ; P9BE-NEXT: mtvsrws v2, r3
2765 ; P9BE-NEXT: blr
2766 ;
2767 ; P9LE-LABEL: spltRegValui:
2768 ; P9LE: # %bb.0: # %entry
2769 ; P9LE-NEXT: mtvsrws v2, r3
2770 ; P9LE-NEXT: blr
2771 ;
2772 ; P8BE-LABEL: spltRegValui:
2773 ; P8BE: # %bb.0: # %entry
2774 ; P8BE-NEXT: mtfprwz f0, r3
2775 ; P8BE-NEXT: xxspltw v2, vs0, 1
2776 ; P8BE-NEXT: blr
2777 ;
2778 ; P8LE-LABEL: spltRegValui:
2779 ; P8LE: # %bb.0: # %entry
2780 ; P8LE-NEXT: mtfprwz f0, r3
2781 ; P8LE-NEXT: xxspltw v2, vs0, 1
2782 ; P8LE-NEXT: blr
2783 entry:
2784 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0
2785 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
2786 ret <4 x i32> %splat.splat
2787 }
2789 define <4 x i32> @spltMemValui(ptr nocapture readonly %ptr) {
2790 ; P9BE-LABEL: spltMemValui:
2791 ; P9BE: # %bb.0: # %entry
2792 ; P9BE-NEXT: lxvwsx v2, 0, r3
2793 ; P9BE-NEXT: blr
2794 ;
2795 ; P9LE-LABEL: spltMemValui:
2796 ; P9LE: # %bb.0: # %entry
2797 ; P9LE-NEXT: lxvwsx v2, 0, r3
2798 ; P9LE-NEXT: blr
2799 ;
2800 ; P8BE-LABEL: spltMemValui:
2801 ; P8BE: # %bb.0: # %entry
2802 ; P8BE-NEXT: lfiwzx f0, 0, r3
2803 ; P8BE-NEXT: xxspltw v2, vs0, 1
2804 ; P8BE-NEXT: blr
2805 ;
2806 ; P8LE-LABEL: spltMemValui:
2807 ; P8LE: # %bb.0: # %entry
2808 ; P8LE-NEXT: lfiwzx f0, 0, r3
2809 ; P8LE-NEXT: xxspltw v2, vs0, 1
2810 ; P8LE-NEXT: blr
2811 entry:
2812 %0 = load i32, ptr %ptr, align 4
2813 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
2814 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
2815 ret <4 x i32> %splat.splat
2816 }
2818 define <4 x i32> @spltCnstConvftoui() {
2819 ; P9BE-LABEL: spltCnstConvftoui:
2820 ; P9BE: # %bb.0: # %entry
2821 ; P9BE-NEXT: vspltisw v2, 4
2822 ; P9BE-NEXT: blr
2823 ;
2824 ; P9LE-LABEL: spltCnstConvftoui:
2825 ; P9LE: # %bb.0: # %entry
2826 ; P9LE-NEXT: vspltisw v2, 4
2827 ; P9LE-NEXT: blr
2828 ;
2829 ; P8BE-LABEL: spltCnstConvftoui:
2830 ; P8BE: # %bb.0: # %entry
2831 ; P8BE-NEXT: vspltisw v2, 4
2832 ; P8BE-NEXT: blr
2833 ;
2834 ; P8LE-LABEL: spltCnstConvftoui:
2835 ; P8LE: # %bb.0: # %entry
2836 ; P8LE-NEXT: vspltisw v2, 4
2837 ; P8LE-NEXT: blr
2838 entry:
2839 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4>
2840 }
2842 define <4 x i32> @fromRegsConvftoui(float %a, float %b, float %c, float %d) {
2843 ; P9BE-LABEL: fromRegsConvftoui:
2844 ; P9BE: # %bb.0: # %entry
2845 ; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
2846 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
2847 ; P9BE-NEXT: xxmrghd vs0, vs2, vs4
2848 ; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
2849 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
2850 ; P9BE-NEXT: xvcvdpuxws v2, vs0
2851 ; P9BE-NEXT: xxmrghd vs0, vs1, vs3
2852 ; P9BE-NEXT: xvcvdpuxws v3, vs0
2853 ; P9BE-NEXT: vmrgew v2, v3, v2
2854 ; P9BE-NEXT: blr
2855 ;
2856 ; P9LE-LABEL: fromRegsConvftoui:
2857 ; P9LE: # %bb.0: # %entry
2858 ; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
2859 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
2860 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
2861 ; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
2862 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
2863 ; P9LE-NEXT: xvcvdpuxws v2, vs0
2864 ; P9LE-NEXT: xxmrghd vs0, vs4, vs2
2865 ; P9LE-NEXT: xvcvdpuxws v3, vs0
2866 ; P9LE-NEXT: vmrgew v2, v3, v2
2867 ; P9LE-NEXT: blr
2868 ;
2869 ; P8BE-LABEL: fromRegsConvftoui:
2870 ; P8BE: # %bb.0: # %entry
2871 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
2872 ; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
2873 ; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
2874 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
2875 ; P8BE-NEXT: xxmrghd vs0, vs2, vs4
2876 ; P8BE-NEXT: xxmrghd vs1, vs1, vs3
2877 ; P8BE-NEXT: xvcvdpuxws v2, vs0
2878 ; P8BE-NEXT: xvcvdpuxws v3, vs1
2879 ; P8BE-NEXT: vmrgew v2, v3, v2
2880 ; P8BE-NEXT: blr
2881 ;
2882 ; P8LE-LABEL: fromRegsConvftoui:
2883 ; P8LE: # %bb.0: # %entry
2884 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
2885 ; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
2886 ; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
2887 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
2888 ; P8LE-NEXT: xxmrghd vs0, vs3, vs1
2889 ; P8LE-NEXT: xxmrghd vs1, vs4, vs2
2890 ; P8LE-NEXT: xvcvdpuxws v2, vs0
2891 ; P8LE-NEXT: xvcvdpuxws v3, vs1
2892 ; P8LE-NEXT: vmrgew v2, v3, v2
2893 ; P8LE-NEXT: blr
2894 entry:
2895 %conv = fptoui float %a to i32
2896 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
2897 %conv1 = fptoui float %b to i32
2898 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1
2899 %conv3 = fptoui float %c to i32
2900 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2
2901 %conv5 = fptoui float %d to i32
2902 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
2903 ret <4 x i32> %vecinit6
2904 }
2906 define <4 x i32> @fromDiffConstsConvftoui() {
2907 ; P9BE-LABEL: fromDiffConstsConvftoui:
2908 ; P9BE: # %bb.0: # %entry
2909 ; P9BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha
2910 ; P9BE-NEXT: addi r3, r3, .LCPI48_0@toc@l
2911 ; P9BE-NEXT: lxv v2, 0(r3)
2912 ; P9BE-NEXT: blr
2913 ;
2914 ; P9LE-LABEL: fromDiffConstsConvftoui:
2915 ; P9LE: # %bb.0: # %entry
2916 ; P9LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha
2917 ; P9LE-NEXT: addi r3, r3, .LCPI48_0@toc@l
2918 ; P9LE-NEXT: lxv v2, 0(r3)
2919 ; P9LE-NEXT: blr
2920 ;
2921 ; P8BE-LABEL: fromDiffConstsConvftoui:
2922 ; P8BE: # %bb.0: # %entry
2923 ; P8BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha
2924 ; P8BE-NEXT: addi r3, r3, .LCPI48_0@toc@l
2925 ; P8BE-NEXT: lxvw4x v2, 0, r3
2926 ; P8BE-NEXT: blr
2927 ;
2928 ; P8LE-LABEL: fromDiffConstsConvftoui:
2929 ; P8LE: # %bb.0: # %entry
2930 ; P8LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha
2931 ; P8LE-NEXT: addi r3, r3, .LCPI48_0@toc@l
2932 ; P8LE-NEXT: lxvd2x vs0, 0, r3
2933 ; P8LE-NEXT: xxswapd v2, vs0
2934 ; P8LE-NEXT: blr
2935 entry:
2936 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
2937 }
2939 define <4 x i32> @fromDiffMemConsAConvftoui(ptr nocapture readonly %ptr) {
2940 ; P9BE-LABEL: fromDiffMemConsAConvftoui:
2941 ; P9BE: # %bb.0: # %entry
2942 ; P9BE-NEXT: lxv vs0, 0(r3)
2943 ; P9BE-NEXT: xvcvspuxws v2, vs0
2944 ; P9BE-NEXT: blr
2945 ;
2946 ; P9LE-LABEL: fromDiffMemConsAConvftoui:
2947 ; P9LE: # %bb.0: # %entry
2948 ; P9LE-NEXT: lxv vs0, 0(r3)
2949 ; P9LE-NEXT: xvcvspuxws v2, vs0
2950 ; P9LE-NEXT: blr
2951 ;
2952 ; P8BE-LABEL: fromDiffMemConsAConvftoui:
2953 ; P8BE: # %bb.0: # %entry
2954 ; P8BE-NEXT: lxvw4x vs0, 0, r3
2955 ; P8BE-NEXT: xvcvspuxws v2, vs0
2956 ; P8BE-NEXT: blr
2957 ;
2958 ; P8LE-LABEL: fromDiffMemConsAConvftoui:
2959 ; P8LE: # %bb.0: # %entry
2960 ; P8LE-NEXT: lxvd2x vs0, 0, r3
2961 ; P8LE-NEXT: xxswapd v2, vs0
2962 ; P8LE-NEXT: xvcvspuxws v2, v2
2963 ; P8LE-NEXT: blr
2964 entry:
2965 %0 = load <4 x float>, ptr %ptr, align 4
2966 %1 = fptoui <4 x float> %0 to <4 x i32>
2967 ret <4 x i32> %1
2968 }
2970 define <4 x i32> @fromDiffMemConsDConvftoui(ptr nocapture readonly %ptr) {
2971 ; P9BE-LABEL: fromDiffMemConsDConvftoui:
2972 ; P9BE: # %bb.0: # %entry
2973 ; P9BE-NEXT: lxv vs0, 0(r3)
2974 ; P9BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha
2975 ; P9BE-NEXT: addi r3, r3, .LCPI50_0@toc@l
2976 ; P9BE-NEXT: lxv vs1, 0(r3)
2977 ; P9BE-NEXT: xxperm vs0, vs0, vs1
2978 ; P9BE-NEXT: xvcvspuxws v2, vs0
2979 ; P9BE-NEXT: blr
2980 ;
2981 ; P9LE-LABEL: fromDiffMemConsDConvftoui:
2982 ; P9LE: # %bb.0: # %entry
2983 ; P9LE-NEXT: lxv vs0, 0(r3)
2984 ; P9LE-NEXT: addis r3, r2, .LCPI50_0@toc@ha
2985 ; P9LE-NEXT: addi r3, r3, .LCPI50_0@toc@l
2986 ; P9LE-NEXT: lxv vs1, 0(r3)
2987 ; P9LE-NEXT: xxperm vs0, vs0, vs1
2988 ; P9LE-NEXT: xvcvspuxws v2, vs0
2989 ; P9LE-NEXT: blr
2990 ;
2991 ; P8BE-LABEL: fromDiffMemConsDConvftoui:
2992 ; P8BE: # %bb.0: # %entry
2993 ; P8BE-NEXT: addis r4, r2, .LCPI50_0@toc@ha
2994 ; P8BE-NEXT: lxvw4x v2, 0, r3
2995 ; P8BE-NEXT: addi r4, r4, .LCPI50_0@toc@l
2996 ; P8BE-NEXT: lxvw4x v3, 0, r4
2997 ; P8BE-NEXT: vperm v2, v2, v2, v3
2998 ; P8BE-NEXT: xvcvspuxws v2, v2
2999 ; P8BE-NEXT: blr
3000 ;
3001 ; P8LE-LABEL: fromDiffMemConsDConvftoui:
3002 ; P8LE: # %bb.0: # %entry
3003 ; P8LE-NEXT: addis r4, r2, .LCPI50_0@toc@ha
3004 ; P8LE-NEXT: lxvd2x vs0, 0, r3
3005 ; P8LE-NEXT: addi r4, r4, .LCPI50_0@toc@l
3006 ; P8LE-NEXT: lxvd2x vs1, 0, r4
3007 ; P8LE-NEXT: xxswapd v2, vs0
3008 ; P8LE-NEXT: xxswapd v3, vs1
3009 ; P8LE-NEXT: vperm v2, v2, v2, v3
3010 ; P8LE-NEXT: xvcvspuxws v2, v2
3011 ; P8LE-NEXT: blr
3012 entry:
3013 %arrayidx = getelementptr inbounds float, ptr %ptr, i64 3
3014 %0 = load float, ptr %arrayidx, align 4
3015 %conv = fptoui float %0 to i32
3016 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
3017 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 2
3018 %1 = load float, ptr %arrayidx1, align 4
3019 %conv2 = fptoui float %1 to i32
3020 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
3021 %arrayidx4 = getelementptr inbounds float, ptr %ptr, i64 1
3022 %2 = load float, ptr %arrayidx4, align 4
3023 %conv5 = fptoui float %2 to i32
3024 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
3025 %3 = load float, ptr %ptr, align 4
3026 %conv8 = fptoui float %3 to i32
3027 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
3028 ret <4 x i32> %vecinit9
3029 }
3031 define <4 x i32> @fromDiffMemVarAConvftoui(ptr nocapture readonly %arr, i32 signext %elem) {
3032 ; P9BE-LABEL: fromDiffMemVarAConvftoui:
3033 ; P9BE: # %bb.0: # %entry
3034 ; P9BE-NEXT: sldi r4, r4, 2
3035 ; P9BE-NEXT: lfsux f0, r3, r4
3036 ; P9BE-NEXT: lfs f1, 12(r3)
3037 ; P9BE-NEXT: lfs f2, 4(r3)
3038 ; P9BE-NEXT: xxmrghd vs1, vs2, vs1
3039 ; P9BE-NEXT: xvcvdpsp v2, vs1
3040 ; P9BE-NEXT: lfs f1, 8(r3)
3041 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
3042 ; P9BE-NEXT: xvcvdpsp v3, vs0
3043 ; P9BE-NEXT: vmrgew v2, v3, v2
3044 ; P9BE-NEXT: xvcvspuxws v2, v2
3045 ; P9BE-NEXT: blr
3046 ;
3047 ; P9LE-LABEL: fromDiffMemVarAConvftoui:
3048 ; P9LE: # %bb.0: # %entry
3049 ; P9LE-NEXT: sldi r4, r4, 2
3050 ; P9LE-NEXT: lfsux f0, r3, r4
3051 ; P9LE-NEXT: lfs f1, 8(r3)
3052 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
3053 ; P9LE-NEXT: lfs f1, 12(r3)
3054 ; P9LE-NEXT: xvcvdpsp v2, vs0
3055 ; P9LE-NEXT: lfs f0, 4(r3)
3056 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
3057 ; P9LE-NEXT: xvcvdpsp v3, vs0
3058 ; P9LE-NEXT: vmrgew v2, v3, v2
3059 ; P9LE-NEXT: xvcvspuxws v2, v2
3060 ; P9LE-NEXT: blr
3061 ;
3062 ; P8BE-LABEL: fromDiffMemVarAConvftoui:
3063 ; P8BE: # %bb.0: # %entry
3064 ; P8BE-NEXT: sldi r4, r4, 2
3065 ; P8BE-NEXT: lfsux f0, r3, r4
3066 ; P8BE-NEXT: lfs f1, 12(r3)
3067 ; P8BE-NEXT: lfs f2, 4(r3)
3068 ; P8BE-NEXT: lfs f3, 8(r3)
3069 ; P8BE-NEXT: xxmrghd vs1, vs2, vs1
3070 ; P8BE-NEXT: xxmrghd vs0, vs0, vs3
3071 ; P8BE-NEXT: xvcvdpsp v2, vs1
3072 ; P8BE-NEXT: xvcvdpsp v3, vs0
3073 ; P8BE-NEXT: vmrgew v2, v3, v2
3074 ; P8BE-NEXT: xvcvspuxws v2, v2
3075 ; P8BE-NEXT: blr
3076 ;
3077 ; P8LE-LABEL: fromDiffMemVarAConvftoui:
3078 ; P8LE: # %bb.0: # %entry
3079 ; P8LE-NEXT: sldi r4, r4, 2
3080 ; P8LE-NEXT: lfsux f0, r3, r4
3081 ; P8LE-NEXT: lfs f1, 8(r3)
3082 ; P8LE-NEXT: lfs f2, 4(r3)
3083 ; P8LE-NEXT: lfs f3, 12(r3)
3084 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
3085 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2
3086 ; P8LE-NEXT: xvcvdpsp v2, vs0
3087 ; P8LE-NEXT: xvcvdpsp v3, vs1
3088 ; P8LE-NEXT: vmrgew v2, v3, v2
3089 ; P8LE-NEXT: xvcvspuxws v2, v2
3090 ; P8LE-NEXT: blr
3091 entry:
3092 %idxprom = sext i32 %elem to i64
3093 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom
3094 %0 = load float, ptr %arrayidx, align 4
3095 %conv = fptoui float %0 to i32
3096 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
3097 %add = add nsw i32 %elem, 1
3098 %idxprom1 = sext i32 %add to i64
3099 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1
3100 %1 = load float, ptr %arrayidx2, align 4
3101 %conv3 = fptoui float %1 to i32
3102 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
3103 %add5 = add nsw i32 %elem, 2
3104 %idxprom6 = sext i32 %add5 to i64
3105 %arrayidx7 = getelementptr inbounds float, ptr %arr, i64 %idxprom6
3106 %2 = load float, ptr %arrayidx7, align 4
3107 %conv8 = fptoui float %2 to i32
3108 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
3109 %add10 = add nsw i32 %elem, 3
3110 %idxprom11 = sext i32 %add10 to i64
3111 %arrayidx12 = getelementptr inbounds float, ptr %arr, i64 %idxprom11
3112 %3 = load float, ptr %arrayidx12, align 4
3113 %conv13 = fptoui float %3 to i32
3114 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
3115 ret <4 x i32> %vecinit14
3116 ; FIXME: implement finding consecutive loads with pre-inc
3117 }
3119 define <4 x i32> @fromDiffMemVarDConvftoui(ptr nocapture readonly %arr, i32 signext %elem) {
3120 ; P9BE-LABEL: fromDiffMemVarDConvftoui:
3121 ; P9BE: # %bb.0: # %entry
3122 ; P9BE-NEXT: sldi r4, r4, 2
3123 ; P9BE-NEXT: lfsux f0, r3, r4
3124 ; P9BE-NEXT: lfs f1, -12(r3)
3125 ; P9BE-NEXT: lfs f2, -4(r3)
3126 ; P9BE-NEXT: xxmrghd vs1, vs2, vs1
3127 ; P9BE-NEXT: xvcvdpsp v2, vs1
3128 ; P9BE-NEXT: lfs f1, -8(r3)
3129 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
3130 ; P9BE-NEXT: xvcvdpsp v3, vs0
3131 ; P9BE-NEXT: vmrgew v2, v3, v2
3132 ; P9BE-NEXT: xvcvspuxws v2, v2
3133 ; P9BE-NEXT: blr
3134 ;
3135 ; P9LE-LABEL: fromDiffMemVarDConvftoui:
3136 ; P9LE: # %bb.0: # %entry
3137 ; P9LE-NEXT: sldi r4, r4, 2
3138 ; P9LE-NEXT: lfsux f0, r3, r4
3139 ; P9LE-NEXT: lfs f1, -8(r3)
3140 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
3141 ; P9LE-NEXT: lfs f1, -12(r3)
3142 ; P9LE-NEXT: xvcvdpsp v2, vs0
3143 ; P9LE-NEXT: lfs f0, -4(r3)
3144 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
3145 ; P9LE-NEXT: xvcvdpsp v3, vs0
3146 ; P9LE-NEXT: vmrgew v2, v3, v2
3147 ; P9LE-NEXT: xvcvspuxws v2, v2
3148 ; P9LE-NEXT: blr
3149 ;
3150 ; P8BE-LABEL: fromDiffMemVarDConvftoui:
3151 ; P8BE: # %bb.0: # %entry
3152 ; P8BE-NEXT: sldi r4, r4, 2
3153 ; P8BE-NEXT: lfsux f0, r3, r4
3154 ; P8BE-NEXT: lfs f1, -12(r3)
3155 ; P8BE-NEXT: lfs f2, -4(r3)
3156 ; P8BE-NEXT: lfs f3, -8(r3)
3157 ; P8BE-NEXT: xxmrghd vs1, vs2, vs1
3158 ; P8BE-NEXT: xxmrghd vs0, vs0, vs3
3159 ; P8BE-NEXT: xvcvdpsp v2, vs1
3160 ; P8BE-NEXT: xvcvdpsp v3, vs0
3161 ; P8BE-NEXT: vmrgew v2, v3, v2
3162 ; P8BE-NEXT: xvcvspuxws v2, v2
3163 ; P8BE-NEXT: blr
3164 ;
3165 ; P8LE-LABEL: fromDiffMemVarDConvftoui:
3166 ; P8LE: # %bb.0: # %entry
3167 ; P8LE-NEXT: sldi r4, r4, 2
3168 ; P8LE-NEXT: lfsux f0, r3, r4
3169 ; P8LE-NEXT: lfs f1, -8(r3)
3170 ; P8LE-NEXT: lfs f2, -4(r3)
3171 ; P8LE-NEXT: lfs f3, -12(r3)
3172 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
3173 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2
3174 ; P8LE-NEXT: xvcvdpsp v2, vs0
3175 ; P8LE-NEXT: xvcvdpsp v3, vs1
3176 ; P8LE-NEXT: vmrgew v2, v3, v2
3177 ; P8LE-NEXT: xvcvspuxws v2, v2
3178 ; P8LE-NEXT: blr
3179 entry:
3180 %idxprom = sext i32 %elem to i64
3181 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom
3182 %0 = load float, ptr %arrayidx, align 4
3183 %conv = fptoui float %0 to i32
3184 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
3185 %sub = add nsw i32 %elem, -1
3186 %idxprom1 = sext i32 %sub to i64
3187 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1
3188 %1 = load float, ptr %arrayidx2, align 4
3189 %conv3 = fptoui float %1 to i32
3190 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
3191 %sub5 = add nsw i32 %elem, -2
3192 %idxprom6 = sext i32 %sub5 to i64
3193 %arrayidx7 = getelementptr inbounds float, ptr %arr, i64 %idxprom6
3194 %2 = load float, ptr %arrayidx7, align 4
3195 %conv8 = fptoui float %2 to i32
3196 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
3197 %sub10 = add nsw i32 %elem, -3
3198 %idxprom11 = sext i32 %sub10 to i64
3199 %arrayidx12 = getelementptr inbounds float, ptr %arr, i64 %idxprom11
3200 %3 = load float, ptr %arrayidx12, align 4
3201 %conv13 = fptoui float %3 to i32
3202 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
3203 ret <4 x i32> %vecinit14
3204 ; FIXME: implement finding consecutive loads with pre-inc
3205 }
3207 define <4 x i32> @spltRegValConvftoui(float %val) {
3208 ; P9BE-LABEL: spltRegValConvftoui:
3209 ; P9BE: # %bb.0: # %entry
3210 ; P9BE-NEXT: xscvdpuxws f0, f1
3211 ; P9BE-NEXT: xxspltw v2, vs0, 1
3212 ; P9BE-NEXT: blr
3213 ;
3214 ; P9LE-LABEL: spltRegValConvftoui:
3215 ; P9LE: # %bb.0: # %entry
3216 ; P9LE-NEXT: xscvdpuxws f0, f1
3217 ; P9LE-NEXT: xxspltw v2, vs0, 1
3218 ; P9LE-NEXT: blr
3219 ;
3220 ; P8BE-LABEL: spltRegValConvftoui:
3221 ; P8BE: # %bb.0: # %entry
3222 ; P8BE-NEXT: xscvdpuxws f0, f1
3223 ; P8BE-NEXT: xxspltw v2, vs0, 1
3224 ; P8BE-NEXT: blr
3225 ;
3226 ; P8LE-LABEL: spltRegValConvftoui:
3227 ; P8LE: # %bb.0: # %entry
3228 ; P8LE-NEXT: xscvdpuxws f0, f1
3229 ; P8LE-NEXT: xxspltw v2, vs0, 1
3230 ; P8LE-NEXT: blr
3231 entry:
3232 %conv = fptoui float %val to i32
3233 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
3234 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
3235 ret <4 x i32> %splat.splat
3236 }
3238 define <4 x i32> @spltMemValConvftoui(ptr nocapture readonly %ptr) {
3239 ; P9BE-LABEL: spltMemValConvftoui:
3240 ; P9BE: # %bb.0: # %entry
3241 ; P9BE-NEXT: lfiwzx f0, 0, r3
3242 ; P9BE-NEXT: xvcvspuxws vs0, vs0
3243 ; P9BE-NEXT: xxspltw v2, vs0, 1
3244 ; P9BE-NEXT: blr
3245 ;
3246 ; P9LE-LABEL: spltMemValConvftoui:
3247 ; P9LE: # %bb.0: # %entry
3248 ; P9LE-NEXT: lfiwzx f0, 0, r3
3249 ; P9LE-NEXT: xvcvspuxws vs0, vs0
3250 ; P9LE-NEXT: xxspltw v2, vs0, 1
3251 ; P9LE-NEXT: blr
3252 ;
3253 ; P8BE-LABEL: spltMemValConvftoui:
3254 ; P8BE: # %bb.0: # %entry
3255 ; P8BE-NEXT: lfsx f0, 0, r3
3256 ; P8BE-NEXT: xscvdpuxws f0, f0
3257 ; P8BE-NEXT: xxspltw v2, vs0, 1
3258 ; P8BE-NEXT: blr
3259 ;
3260 ; P8LE-LABEL: spltMemValConvftoui:
3261 ; P8LE: # %bb.0: # %entry
3262 ; P8LE-NEXT: lfsx f0, 0, r3
3263 ; P8LE-NEXT: xscvdpuxws f0, f0
3264 ; P8LE-NEXT: xxspltw v2, vs0, 1
3265 ; P8LE-NEXT: blr
3266 entry:
3267 %0 = load float, ptr %ptr, align 4
3268 %conv = fptoui float %0 to i32
3269 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
3270 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
3271 ret <4 x i32> %splat.splat
3272 }
3274 define <4 x i32> @spltCnstConvdtoui() {
3275 ; P9BE-LABEL: spltCnstConvdtoui:
3276 ; P9BE: # %bb.0: # %entry
3277 ; P9BE-NEXT: vspltisw v2, 4
3278 ; P9BE-NEXT: blr
3279 ;
3280 ; P9LE-LABEL: spltCnstConvdtoui:
3281 ; P9LE: # %bb.0: # %entry
3282 ; P9LE-NEXT: vspltisw v2, 4
3283 ; P9LE-NEXT: blr
3284 ;
3285 ; P8BE-LABEL: spltCnstConvdtoui:
3286 ; P8BE: # %bb.0: # %entry
3287 ; P8BE-NEXT: vspltisw v2, 4
3288 ; P8BE-NEXT: blr
3289 ;
3290 ; P8LE-LABEL: spltCnstConvdtoui:
3291 ; P8LE: # %bb.0: # %entry
3292 ; P8LE-NEXT: vspltisw v2, 4
3293 ; P8LE-NEXT: blr
3294 entry:
3295 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4>
3296 }
3298 define <4 x i32> @fromRegsConvdtoui(double %a, double %b, double %c, double %d) {
3299 ; P9BE-LABEL: fromRegsConvdtoui:
3300 ; P9BE: # %bb.0: # %entry
3301 ; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
3302 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
3303 ; P9BE-NEXT: xxmrghd vs0, vs2, vs4
3304 ; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
3305 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
3306 ; P9BE-NEXT: xvcvdpuxws v2, vs0
3307 ; P9BE-NEXT: xxmrghd vs0, vs1, vs3
3308 ; P9BE-NEXT: xvcvdpuxws v3, vs0
3309 ; P9BE-NEXT: vmrgew v2, v3, v2
3310 ; P9BE-NEXT: blr
3311 ;
3312 ; P9LE-LABEL: fromRegsConvdtoui:
3313 ; P9LE: # %bb.0: # %entry
3314 ; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
3315 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
3316 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
3317 ; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
3318 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
3319 ; P9LE-NEXT: xvcvdpuxws v2, vs0
3320 ; P9LE-NEXT: xxmrghd vs0, vs4, vs2
3321 ; P9LE-NEXT: xvcvdpuxws v3, vs0
3322 ; P9LE-NEXT: vmrgew v2, v3, v2
3323 ; P9LE-NEXT: blr
3324 ;
3325 ; P8BE-LABEL: fromRegsConvdtoui:
3326 ; P8BE: # %bb.0: # %entry
3327 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
3328 ; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
3329 ; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
3330 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
3331 ; P8BE-NEXT: xxmrghd vs0, vs2, vs4
3332 ; P8BE-NEXT: xxmrghd vs1, vs1, vs3
3333 ; P8BE-NEXT: xvcvdpuxws v2, vs0
3334 ; P8BE-NEXT: xvcvdpuxws v3, vs1
3335 ; P8BE-NEXT: vmrgew v2, v3, v2
3336 ; P8BE-NEXT: blr
3337 ;
3338 ; P8LE-LABEL: fromRegsConvdtoui:
3339 ; P8LE: # %bb.0: # %entry
3340 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
3341 ; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
3342 ; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
3343 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
3344 ; P8LE-NEXT: xxmrghd vs0, vs3, vs1
3345 ; P8LE-NEXT: xxmrghd vs1, vs4, vs2
3346 ; P8LE-NEXT: xvcvdpuxws v2, vs0
3347 ; P8LE-NEXT: xvcvdpuxws v3, vs1
3348 ; P8LE-NEXT: vmrgew v2, v3, v2
3349 ; P8LE-NEXT: blr
3350 entry:
3351 %conv = fptoui double %a to i32
3352 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
3353 %conv1 = fptoui double %b to i32
3354 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1
3355 %conv3 = fptoui double %c to i32
3356 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2
3357 %conv5 = fptoui double %d to i32
3358 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
3359 ret <4 x i32> %vecinit6
3360 }
3362 define <4 x i32> @fromDiffConstsConvdtoui() {
3363 ; P9BE-LABEL: fromDiffConstsConvdtoui:
3364 ; P9BE: # %bb.0: # %entry
3365 ; P9BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha
3366 ; P9BE-NEXT: addi r3, r3, .LCPI57_0@toc@l
3367 ; P9BE-NEXT: lxv v2, 0(r3)
3368 ; P9BE-NEXT: blr
3369 ;
3370 ; P9LE-LABEL: fromDiffConstsConvdtoui:
3371 ; P9LE: # %bb.0: # %entry
3372 ; P9LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha
3373 ; P9LE-NEXT: addi r3, r3, .LCPI57_0@toc@l
3374 ; P9LE-NEXT: lxv v2, 0(r3)
3375 ; P9LE-NEXT: blr
3376 ;
3377 ; P8BE-LABEL: fromDiffConstsConvdtoui:
3378 ; P8BE: # %bb.0: # %entry
3379 ; P8BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha
3380 ; P8BE-NEXT: addi r3, r3, .LCPI57_0@toc@l
3381 ; P8BE-NEXT: lxvw4x v2, 0, r3
3382 ; P8BE-NEXT: blr
3383 ;
3384 ; P8LE-LABEL: fromDiffConstsConvdtoui:
3385 ; P8LE: # %bb.0: # %entry
3386 ; P8LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha
3387 ; P8LE-NEXT: addi r3, r3, .LCPI57_0@toc@l
3388 ; P8LE-NEXT: lxvd2x vs0, 0, r3
3389 ; P8LE-NEXT: xxswapd v2, vs0
3390 ; P8LE-NEXT: blr
3391 entry:
3392 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
3393 }
3395 define <4 x i32> @fromDiffMemConsAConvdtoui(ptr nocapture readonly %ptr) {
3396 ; P9BE-LABEL: fromDiffMemConsAConvdtoui:
3397 ; P9BE: # %bb.0: # %entry
3398 ; P9BE-NEXT: lxv vs0, 0(r3)
3399 ; P9BE-NEXT: lxv vs1, 16(r3)
3400 ; P9BE-NEXT: xxmrgld vs2, vs0, vs1
3401 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
3402 ; P9BE-NEXT: xvcvdpuxws v2, vs2
3403 ; P9BE-NEXT: xvcvdpuxws v3, vs0
3404 ; P9BE-NEXT: vmrgew v2, v3, v2
3405 ; P9BE-NEXT: blr
3406 ;
3407 ; P9LE-LABEL: fromDiffMemConsAConvdtoui:
3408 ; P9LE: # %bb.0: # %entry
3409 ; P9LE-NEXT: lxv vs0, 0(r3)
3410 ; P9LE-NEXT: lxv vs1, 16(r3)
3411 ; P9LE-NEXT: xxmrgld vs2, vs1, vs0
3412 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
3413 ; P9LE-NEXT: xvcvdpuxws v2, vs2
3414 ; P9LE-NEXT: xvcvdpuxws v3, vs0
3415 ; P9LE-NEXT: vmrgew v2, v3, v2
3416 ; P9LE-NEXT: blr
3417 ;
3418 ; P8BE-LABEL: fromDiffMemConsAConvdtoui:
3419 ; P8BE: # %bb.0: # %entry
3420 ; P8BE-NEXT: li r4, 16
3421 ; P8BE-NEXT: lxvd2x vs0, 0, r3
3422 ; P8BE-NEXT: lxvd2x vs1, r3, r4
3423 ; P8BE-NEXT: xxmrgld vs2, vs0, vs1
3424 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
3425 ; P8BE-NEXT: xvcvdpuxws v2, vs2
3426 ; P8BE-NEXT: xvcvdpuxws v3, vs0
3427 ; P8BE-NEXT: vmrgew v2, v3, v2
3428 ; P8BE-NEXT: blr
3429 ;
3430 ; P8LE-LABEL: fromDiffMemConsAConvdtoui:
3431 ; P8LE: # %bb.0: # %entry
3432 ; P8LE-NEXT: li r4, 16
3433 ; P8LE-NEXT: lxvd2x vs0, 0, r3
3434 ; P8LE-NEXT: lxvd2x vs1, r3, r4
3435 ; P8LE-NEXT: xxswapd vs0, vs0
3436 ; P8LE-NEXT: xxswapd vs1, vs1
3437 ; P8LE-NEXT: xxmrgld vs2, vs1, vs0
3438 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
3439 ; P8LE-NEXT: xvcvdpuxws v2, vs2
3440 ; P8LE-NEXT: xvcvdpuxws v3, vs0
3441 ; P8LE-NEXT: vmrgew v2, v3, v2
3442 ; P8LE-NEXT: blr
3443 entry:
3444 %0 = load <2 x double>, ptr %ptr, align 8
3445 %1 = fptoui <2 x double> %0 to <2 x i32>
3446 %arrayidx4 = getelementptr inbounds double, ptr %ptr, i64 2
3447 %2 = load <2 x double>, ptr %arrayidx4, align 8
3448 %3 = fptoui <2 x double> %2 to <2 x i32>
3449 %vecinit9 = shufflevector <2 x i32> %1, <2 x i32> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
3450 ret <4 x i32> %vecinit9
3451 }
3453 define <4 x i32> @fromDiffMemConsDConvdtoui(ptr nocapture readonly %ptr) {
3454 ; P9BE-LABEL: fromDiffMemConsDConvdtoui:
3455 ; P9BE: # %bb.0: # %entry
3456 ; P9BE-NEXT: lfd f0, 24(r3)
3457 ; P9BE-NEXT: lfd f1, 16(r3)
3458 ; P9BE-NEXT: lfd f2, 8(r3)
3459 ; P9BE-NEXT: xxmrghd vs0, vs0, vs2
3460 ; P9BE-NEXT: lfd f3, 0(r3)
3461 ; P9BE-NEXT: xxmrghd vs1, vs1, vs3
3462 ; P9BE-NEXT: xvcvdpuxws v2, vs1
3463 ; P9BE-NEXT: xvcvdpuxws v3, vs0
3464 ; P9BE-NEXT: vmrgew v2, v3, v2
3465 ; P9BE-NEXT: blr
3466 ;
3467 ; P9LE-LABEL: fromDiffMemConsDConvdtoui:
3468 ; P9LE: # %bb.0: # %entry
3469 ; P9LE-NEXT: lfd f0, 24(r3)
3470 ; P9LE-NEXT: lfd f2, 8(r3)
3471 ; P9LE-NEXT: xxmrghd vs0, vs2, vs0
3472 ; P9LE-NEXT: lfd f1, 16(r3)
3473 ; P9LE-NEXT: lfd f3, 0(r3)
3474 ; P9LE-NEXT: xvcvdpuxws v2, vs0
3475 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
3476 ; P9LE-NEXT: xvcvdpuxws v3, vs0
3477 ; P9LE-NEXT: vmrgew v2, v3, v2
3478 ; P9LE-NEXT: blr
3479 ;
3480 ; P8BE-LABEL: fromDiffMemConsDConvdtoui:
3481 ; P8BE: # %bb.0: # %entry
3482 ; P8BE-NEXT: lfd f0, 16(r3)
3483 ; P8BE-NEXT: lfd f1, 0(r3)
3484 ; P8BE-NEXT: lfd f2, 24(r3)
3485 ; P8BE-NEXT: lfd f3, 8(r3)
3486 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
3487 ; P8BE-NEXT: xxmrghd vs1, vs2, vs3
3488 ; P8BE-NEXT: xvcvdpuxws v2, vs0
3489 ; P8BE-NEXT: xvcvdpuxws v3, vs1
3490 ; P8BE-NEXT: vmrgew v2, v3, v2
3491 ; P8BE-NEXT: blr
3492 ;
3493 ; P8LE-LABEL: fromDiffMemConsDConvdtoui:
3494 ; P8LE: # %bb.0: # %entry
3495 ; P8LE-NEXT: lfd f0, 24(r3)
3496 ; P8LE-NEXT: lfd f1, 8(r3)
3497 ; P8LE-NEXT: lfd f2, 16(r3)
3498 ; P8LE-NEXT: lfd f3, 0(r3)
3499 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
3500 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2
3501 ; P8LE-NEXT: xvcvdpuxws v2, vs0
3502 ; P8LE-NEXT: xvcvdpuxws v3, vs1
3503 ; P8LE-NEXT: vmrgew v2, v3, v2
3504 ; P8LE-NEXT: blr
3505 entry:
3506 %arrayidx = getelementptr inbounds double, ptr %ptr, i64 3
3507 %0 = load double, ptr %arrayidx, align 8
3508 %conv = fptoui double %0 to i32
3509 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
3510 %arrayidx1 = getelementptr inbounds double, ptr %ptr, i64 2
3511 %1 = load double, ptr %arrayidx1, align 8
3512 %conv2 = fptoui double %1 to i32
3513 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
3514 %arrayidx4 = getelementptr inbounds double, ptr %ptr, i64 1
3515 %2 = load double, ptr %arrayidx4, align 8
3516 %conv5 = fptoui double %2 to i32
3517 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
3518 %3 = load double, ptr %ptr, align 8
3519 %conv8 = fptoui double %3 to i32
3520 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
3521 ret <4 x i32> %vecinit9
3522 }
3524 define <4 x i32> @fromDiffMemVarAConvdtoui(ptr nocapture readonly %arr, i32 signext %elem) {
3525 ; P9BE-LABEL: fromDiffMemVarAConvdtoui:
3526 ; P9BE: # %bb.0: # %entry
3527 ; P9BE-NEXT: sldi r4, r4, 3
3528 ; P9BE-NEXT: lfdux f0, r3, r4
3529 ; P9BE-NEXT: lfd f1, 8(r3)
3530 ; P9BE-NEXT: lfd f2, 16(r3)
3531 ; P9BE-NEXT: lfd f3, 24(r3)
3532 ; P9BE-NEXT: xxmrghd vs1, vs1, vs3
3533 ; P9BE-NEXT: xxmrghd vs0, vs0, vs2
3534 ; P9BE-NEXT: xvcvdpuxws v2, vs1
3535 ; P9BE-NEXT: xvcvdpuxws v3, vs0
3536 ; P9BE-NEXT: vmrgew v2, v3, v2
3537 ; P9BE-NEXT: blr
3538 ;
3539 ; P9LE-LABEL: fromDiffMemVarAConvdtoui:
3540 ; P9LE: # %bb.0: # %entry
3541 ; P9LE-NEXT: sldi r4, r4, 3
3542 ; P9LE-NEXT: lfdux f0, r3, r4
3543 ; P9LE-NEXT: lfd f2, 16(r3)
3544 ; P9LE-NEXT: lfd f1, 8(r3)
3545 ; P9LE-NEXT: lfd f3, 24(r3)
3546 ; P9LE-NEXT: xxmrghd vs0, vs2, vs0
3547 ; P9LE-NEXT: xvcvdpuxws v2, vs0
3548 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
3549 ; P9LE-NEXT: xvcvdpuxws v3, vs0
3550 ; P9LE-NEXT: vmrgew v2, v3, v2
3551 ; P9LE-NEXT: blr
3552 ;
3553 ; P8BE-LABEL: fromDiffMemVarAConvdtoui:
3554 ; P8BE: # %bb.0: # %entry
3555 ; P8BE-NEXT: sldi r4, r4, 3
3556 ; P8BE-NEXT: lfdux f0, r3, r4
3557 ; P8BE-NEXT: lfd f1, 8(r3)
3558 ; P8BE-NEXT: lfd f2, 24(r3)
3559 ; P8BE-NEXT: lfd f3, 16(r3)
3560 ; P8BE-NEXT: xxmrghd vs1, vs1, vs2
3561 ; P8BE-NEXT: xxmrghd vs0, vs0, vs3
3562 ; P8BE-NEXT: xvcvdpuxws v2, vs1
3563 ; P8BE-NEXT: xvcvdpuxws v3, vs0
3564 ; P8BE-NEXT: vmrgew v2, v3, v2
3565 ; P8BE-NEXT: blr
3566 ;
3567 ; P8LE-LABEL: fromDiffMemVarAConvdtoui:
3568 ; P8LE: # %bb.0: # %entry
3569 ; P8LE-NEXT: sldi r4, r4, 3
3570 ; P8LE-NEXT: lfdux f0, r3, r4
3571 ; P8LE-NEXT: lfd f1, 16(r3)
3572 ; P8LE-NEXT: lfd f2, 8(r3)
3573 ; P8LE-NEXT: lfd f3, 24(r3)
3574 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
3575 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2
3576 ; P8LE-NEXT: xvcvdpuxws v2, vs0
3577 ; P8LE-NEXT: xvcvdpuxws v3, vs1
3578 ; P8LE-NEXT: vmrgew v2, v3, v2
3579 ; P8LE-NEXT: blr
3580 entry:
3581 %idxprom = sext i32 %elem to i64
3582 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom
3583 %0 = load double, ptr %arrayidx, align 8
3584 %conv = fptoui double %0 to i32
3585 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
3586 %add = add nsw i32 %elem, 1
3587 %idxprom1 = sext i32 %add to i64
3588 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1
3589 %1 = load double, ptr %arrayidx2, align 8
3590 %conv3 = fptoui double %1 to i32
3591 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
3592 %add5 = add nsw i32 %elem, 2
3593 %idxprom6 = sext i32 %add5 to i64
3594 %arrayidx7 = getelementptr inbounds double, ptr %arr, i64 %idxprom6
3595 %2 = load double, ptr %arrayidx7, align 8
3596 %conv8 = fptoui double %2 to i32
3597 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
3598 %add10 = add nsw i32 %elem, 3
3599 %idxprom11 = sext i32 %add10 to i64
3600 %arrayidx12 = getelementptr inbounds double, ptr %arr, i64 %idxprom11
3601 %3 = load double, ptr %arrayidx12, align 8
3602 %conv13 = fptoui double %3 to i32
3603 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
3604 ret <4 x i32> %vecinit14
3605 }
3607 define <4 x i32> @fromDiffMemVarDConvdtoui(ptr nocapture readonly %arr, i32 signext %elem) {
3608 ; P9BE-LABEL: fromDiffMemVarDConvdtoui:
3609 ; P9BE: # %bb.0: # %entry
3610 ; P9BE-NEXT: sldi r4, r4, 3
3611 ; P9BE-NEXT: lfdux f0, r3, r4
3612 ; P9BE-NEXT: lfd f1, -8(r3)
3613 ; P9BE-NEXT: lfd f2, -16(r3)
3614 ; P9BE-NEXT: lfd f3, -24(r3)
3615 ; P9BE-NEXT: xxmrghd vs1, vs1, vs3
3616 ; P9BE-NEXT: xxmrghd vs0, vs0, vs2
3617 ; P9BE-NEXT: xvcvdpuxws v2, vs1
3618 ; P9BE-NEXT: xvcvdpuxws v3, vs0
3619 ; P9BE-NEXT: vmrgew v2, v3, v2
3620 ; P9BE-NEXT: blr
3621 ;
3622 ; P9LE-LABEL: fromDiffMemVarDConvdtoui:
3623 ; P9LE: # %bb.0: # %entry
3624 ; P9LE-NEXT: sldi r4, r4, 3
3625 ; P9LE-NEXT: lfdux f0, r3, r4
3626 ; P9LE-NEXT: lfd f2, -16(r3)
3627 ; P9LE-NEXT: lfd f1, -8(r3)
3628 ; P9LE-NEXT: lfd f3, -24(r3)
3629 ; P9LE-NEXT: xxmrghd vs0, vs2, vs0
3630 ; P9LE-NEXT: xvcvdpuxws v2, vs0
3631 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
3632 ; P9LE-NEXT: xvcvdpuxws v3, vs0
3633 ; P9LE-NEXT: vmrgew v2, v3, v2
3634 ; P9LE-NEXT: blr
3635 ;
3636 ; P8BE-LABEL: fromDiffMemVarDConvdtoui:
3637 ; P8BE: # %bb.0: # %entry
3638 ; P8BE-NEXT: sldi r4, r4, 3
3639 ; P8BE-NEXT: lfdux f0, r3, r4
3640 ; P8BE-NEXT: lfd f1, -8(r3)
3641 ; P8BE-NEXT: lfd f2, -24(r3)
3642 ; P8BE-NEXT: lfd f3, -16(r3)
3643 ; P8BE-NEXT: xxmrghd vs1, vs1, vs2
3644 ; P8BE-NEXT: xxmrghd vs0, vs0, vs3
3645 ; P8BE-NEXT: xvcvdpuxws v2, vs1
3646 ; P8BE-NEXT: xvcvdpuxws v3, vs0
3647 ; P8BE-NEXT: vmrgew v2, v3, v2
3648 ; P8BE-NEXT: blr
3649 ;
3650 ; P8LE-LABEL: fromDiffMemVarDConvdtoui:
3651 ; P8LE: # %bb.0: # %entry
3652 ; P8LE-NEXT: sldi r4, r4, 3
3653 ; P8LE-NEXT: lfdux f0, r3, r4
3654 ; P8LE-NEXT: lfd f1, -16(r3)
3655 ; P8LE-NEXT: lfd f2, -8(r3)
3656 ; P8LE-NEXT: lfd f3, -24(r3)
3657 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
3658 ; P8LE-NEXT: xxmrghd vs1, vs3, vs2
3659 ; P8LE-NEXT: xvcvdpuxws v2, vs0
3660 ; P8LE-NEXT: xvcvdpuxws v3, vs1
3661 ; P8LE-NEXT: vmrgew v2, v3, v2
3662 ; P8LE-NEXT: blr
3663 entry:
3664 %idxprom = sext i32 %elem to i64
3665 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom
3666 %0 = load double, ptr %arrayidx, align 8
3667 %conv = fptoui double %0 to i32
3668 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
3669 %sub = add nsw i32 %elem, -1
3670 %idxprom1 = sext i32 %sub to i64
3671 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1
3672 %1 = load double, ptr %arrayidx2, align 8
3673 %conv3 = fptoui double %1 to i32
3674 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
3675 %sub5 = add nsw i32 %elem, -2
3676 %idxprom6 = sext i32 %sub5 to i64
3677 %arrayidx7 = getelementptr inbounds double, ptr %arr, i64 %idxprom6
3678 %2 = load double, ptr %arrayidx7, align 8
3679 %conv8 = fptoui double %2 to i32
3680 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
3681 %sub10 = add nsw i32 %elem, -3
3682 %idxprom11 = sext i32 %sub10 to i64
3683 %arrayidx12 = getelementptr inbounds double, ptr %arr, i64 %idxprom11
3684 %3 = load double, ptr %arrayidx12, align 8
3685 %conv13 = fptoui double %3 to i32
3686 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
3687 ret <4 x i32> %vecinit14
3688 }
3690 define <4 x i32> @spltRegValConvdtoui(double %val) {
3691 ; P9BE-LABEL: spltRegValConvdtoui:
3692 ; P9BE: # %bb.0: # %entry
3693 ; P9BE-NEXT: xscvdpuxws f0, f1
3694 ; P9BE-NEXT: xxspltw v2, vs0, 1
3695 ; P9BE-NEXT: blr
3696 ;
3697 ; P9LE-LABEL: spltRegValConvdtoui:
3698 ; P9LE: # %bb.0: # %entry
3699 ; P9LE-NEXT: xscvdpuxws f0, f1
3700 ; P9LE-NEXT: xxspltw v2, vs0, 1
3701 ; P9LE-NEXT: blr
3702 ;
3703 ; P8BE-LABEL: spltRegValConvdtoui:
3704 ; P8BE: # %bb.0: # %entry
3705 ; P8BE-NEXT: xscvdpuxws f0, f1
3706 ; P8BE-NEXT: xxspltw v2, vs0, 1
3707 ; P8BE-NEXT: blr
3708 ;
3709 ; P8LE-LABEL: spltRegValConvdtoui:
3710 ; P8LE: # %bb.0: # %entry
3711 ; P8LE-NEXT: xscvdpuxws f0, f1
3712 ; P8LE-NEXT: xxspltw v2, vs0, 1
3713 ; P8LE-NEXT: blr
3714 entry:
3715 %conv = fptoui double %val to i32
3716 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
3717 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
3718 ret <4 x i32> %splat.splat
3719 }
3721 define <4 x i32> @spltMemValConvdtoui(ptr nocapture readonly %ptr) {
3722 ; P9BE-LABEL: spltMemValConvdtoui:
3723 ; P9BE: # %bb.0: # %entry
3724 ; P9BE-NEXT: lfd f0, 0(r3)
3725 ; P9BE-NEXT: xscvdpuxws f0, f0
3726 ; P9BE-NEXT: xxspltw v2, vs0, 1
3727 ; P9BE-NEXT: blr
3728 ;
3729 ; P9LE-LABEL: spltMemValConvdtoui:
3730 ; P9LE: # %bb.0: # %entry
3731 ; P9LE-NEXT: lfd f0, 0(r3)
3732 ; P9LE-NEXT: xscvdpuxws f0, f0
3733 ; P9LE-NEXT: xxspltw v2, vs0, 1
3734 ; P9LE-NEXT: blr
3735 ;
3736 ; P8BE-LABEL: spltMemValConvdtoui:
3737 ; P8BE: # %bb.0: # %entry
3738 ; P8BE-NEXT: lfdx f0, 0, r3
3739 ; P8BE-NEXT: xscvdpuxws f0, f0
3740 ; P8BE-NEXT: xxspltw v2, vs0, 1
3741 ; P8BE-NEXT: blr
3742 ;
3743 ; P8LE-LABEL: spltMemValConvdtoui:
3744 ; P8LE: # %bb.0: # %entry
3745 ; P8LE-NEXT: lfdx f0, 0, r3
3746 ; P8LE-NEXT: xscvdpuxws f0, f0
3747 ; P8LE-NEXT: xxspltw v2, vs0, 1
3748 ; P8LE-NEXT: blr
3749 entry:
3750 %0 = load double, ptr %ptr, align 8
3751 %conv = fptoui double %0 to i32
3752 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
3753 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
3754 ret <4 x i32> %splat.splat
3755 }
3757 define <2 x i64> @allZeroll() {
3758 ; P9BE-LABEL: allZeroll:
3759 ; P9BE: # %bb.0: # %entry
3760 ; P9BE-NEXT: xxlxor v2, v2, v2
3761 ; P9BE-NEXT: blr
3762 ;
3763 ; P9LE-LABEL: allZeroll:
3764 ; P9LE: # %bb.0: # %entry
3765 ; P9LE-NEXT: xxlxor v2, v2, v2
3766 ; P9LE-NEXT: blr
3767 ;
3768 ; P8BE-LABEL: allZeroll:
3769 ; P8BE: # %bb.0: # %entry
3770 ; P8BE-NEXT: xxlxor v2, v2, v2
3771 ; P8BE-NEXT: blr
3772 ;
3773 ; P8LE-LABEL: allZeroll:
3774 ; P8LE: # %bb.0: # %entry
3775 ; P8LE-NEXT: xxlxor v2, v2, v2
3776 ; P8LE-NEXT: blr
3777 entry:
3778 ret <2 x i64> zeroinitializer
3779 }
3781 define <2 x i64> @spltConst1ll() {
3782 ; P9BE-LABEL: spltConst1ll:
3783 ; P9BE: # %bb.0: # %entry
3784 ; P9BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha
3785 ; P9BE-NEXT: addi r3, r3, .LCPI65_0@toc@l
3786 ; P9BE-NEXT: lxv v2, 0(r3)
3787 ; P9BE-NEXT: blr
3788 ;
3789 ; P9LE-LABEL: spltConst1ll:
3790 ; P9LE: # %bb.0: # %entry
3791 ; P9LE-NEXT: addis r3, r2, .LCPI65_0@toc@ha
3792 ; P9LE-NEXT: addi r3, r3, .LCPI65_0@toc@l
3793 ; P9LE-NEXT: lxv v2, 0(r3)
3794 ; P9LE-NEXT: blr
3795 ;
3796 ; P8BE-LABEL: spltConst1ll:
3797 ; P8BE: # %bb.0: # %entry
3798 ; P8BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha
3799 ; P8BE-NEXT: addi r3, r3, .LCPI65_0@toc@l
3800 ; P8BE-NEXT: lxvd2x v2, 0, r3
3801 ; P8BE-NEXT: blr
3802 ;
3803 ; P8LE-LABEL: spltConst1ll:
3804 ; P8LE: # %bb.0: # %entry
3805 ; P8LE-NEXT: addis r3, r2, .LCPI65_0@toc@ha
3806 ; P8LE-NEXT: addi r3, r3, .LCPI65_0@toc@l
3807 ; P8LE-NEXT: lxvd2x v2, 0, r3
3808 ; P8LE-NEXT: blr
3809 entry:
3810 ret <2 x i64> <i64 1, i64 1>
3811 }
3813 define <2 x i64> @spltConst16kll() {
3814 ; P9BE-LABEL: spltConst16kll:
3815 ; P9BE: # %bb.0: # %entry
3816 ; P9BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha
3817 ; P9BE-NEXT: addi r3, r3, .LCPI66_0@toc@l
3818 ; P9BE-NEXT: lxv v2, 0(r3)
3819 ; P9BE-NEXT: blr
3820 ;
3821 ; P9LE-LABEL: spltConst16kll:
3822 ; P9LE: # %bb.0: # %entry
3823 ; P9LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha
3824 ; P9LE-NEXT: addi r3, r3, .LCPI66_0@toc@l
3825 ; P9LE-NEXT: lxv v2, 0(r3)
3826 ; P9LE-NEXT: blr
3827 ;
3828 ; P8BE-LABEL: spltConst16kll:
3829 ; P8BE: # %bb.0: # %entry
3830 ; P8BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha
3831 ; P8BE-NEXT: addi r3, r3, .LCPI66_0@toc@l
3832 ; P8BE-NEXT: lxvd2x v2, 0, r3
3833 ; P8BE-NEXT: blr
3834 ;
3835 ; P8LE-LABEL: spltConst16kll:
3836 ; P8LE: # %bb.0: # %entry
3837 ; P8LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha
3838 ; P8LE-NEXT: addi r3, r3, .LCPI66_0@toc@l
3839 ; P8LE-NEXT: lxvd2x v2, 0, r3
3840 ; P8LE-NEXT: blr
3841 entry:
3842 ret <2 x i64> <i64 32767, i64 32767>
3843 }
3845 define <2 x i64> @spltConst32kll() {
3846 ; P9BE-LABEL: spltConst32kll:
3847 ; P9BE: # %bb.0: # %entry
3848 ; P9BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha
3849 ; P9BE-NEXT: addi r3, r3, .LCPI67_0@toc@l
3850 ; P9BE-NEXT: lxv v2, 0(r3)
3851 ; P9BE-NEXT: blr
3852 ;
3853 ; P9LE-LABEL: spltConst32kll:
3854 ; P9LE: # %bb.0: # %entry
3855 ; P9LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha
3856 ; P9LE-NEXT: addi r3, r3, .LCPI67_0@toc@l
3857 ; P9LE-NEXT: lxv v2, 0(r3)
3858 ; P9LE-NEXT: blr
3859 ;
3860 ; P8BE-LABEL: spltConst32kll:
3861 ; P8BE: # %bb.0: # %entry
3862 ; P8BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha
3863 ; P8BE-NEXT: addi r3, r3, .LCPI67_0@toc@l
3864 ; P8BE-NEXT: lxvd2x v2, 0, r3
3865 ; P8BE-NEXT: blr
3866 ;
3867 ; P8LE-LABEL: spltConst32kll:
3868 ; P8LE: # %bb.0: # %entry
3869 ; P8LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha
3870 ; P8LE-NEXT: addi r3, r3, .LCPI67_0@toc@l
3871 ; P8LE-NEXT: lxvd2x v2, 0, r3
3872 ; P8LE-NEXT: blr
3873 entry:
3874 ret <2 x i64> <i64 65535, i64 65535>
3875 }
3877 define <2 x i64> @fromRegsll(i64 %a, i64 %b) {
3878 ; P9BE-LABEL: fromRegsll:
3879 ; P9BE: # %bb.0: # %entry
3880 ; P9BE-NEXT: mtvsrdd v2, r3, r4
3881 ; P9BE-NEXT: blr
3882 ;
3883 ; P9LE-LABEL: fromRegsll:
3884 ; P9LE: # %bb.0: # %entry
3885 ; P9LE-NEXT: mtvsrdd v2, r4, r3
3886 ; P9LE-NEXT: blr
3887 ;
3888 ; P8BE-LABEL: fromRegsll:
3889 ; P8BE: # %bb.0: # %entry
3890 ; P8BE-NEXT: mtfprd f0, r4
3891 ; P8BE-NEXT: mtfprd f1, r3
3892 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
3893 ; P8BE-NEXT: blr
3894 ;
3895 ; P8LE-LABEL: fromRegsll:
3896 ; P8LE: # %bb.0: # %entry
3897 ; P8LE-NEXT: mtfprd f0, r3
3898 ; P8LE-NEXT: mtfprd f1, r4
3899 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
3900 ; P8LE-NEXT: blr
3901 entry:
3902 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
3903 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1
3904 ret <2 x i64> %vecinit1
3905 }
3907 define <2 x i64> @fromDiffConstsll() {
3908 ; P9BE-LABEL: fromDiffConstsll:
3909 ; P9BE: # %bb.0: # %entry
3910 ; P9BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha
3911 ; P9BE-NEXT: addi r3, r3, .LCPI69_0@toc@l
3912 ; P9BE-NEXT: lxv v2, 0(r3)
3913 ; P9BE-NEXT: blr
3914 ;
3915 ; P9LE-LABEL: fromDiffConstsll:
3916 ; P9LE: # %bb.0: # %entry
3917 ; P9LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha
3918 ; P9LE-NEXT: addi r3, r3, .LCPI69_0@toc@l
3919 ; P9LE-NEXT: lxv v2, 0(r3)
3920 ; P9LE-NEXT: blr
3921 ;
3922 ; P8BE-LABEL: fromDiffConstsll:
3923 ; P8BE: # %bb.0: # %entry
3924 ; P8BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha
3925 ; P8BE-NEXT: addi r3, r3, .LCPI69_0@toc@l
3926 ; P8BE-NEXT: lxvd2x v2, 0, r3
3927 ; P8BE-NEXT: blr
3928 ;
3929 ; P8LE-LABEL: fromDiffConstsll:
3930 ; P8LE: # %bb.0: # %entry
3931 ; P8LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha
3932 ; P8LE-NEXT: addi r3, r3, .LCPI69_0@toc@l
3933 ; P8LE-NEXT: lxvd2x vs0, 0, r3
3934 ; P8LE-NEXT: xxswapd v2, vs0
3935 ; P8LE-NEXT: blr
3936 entry:
3937 ret <2 x i64> <i64 242, i64 -113>
3938 }
3940 define <2 x i64> @fromDiffMemConsAll(ptr nocapture readonly %arr) {
3941 ; P9BE-LABEL: fromDiffMemConsAll:
3942 ; P9BE: # %bb.0: # %entry
3943 ; P9BE-NEXT: lxv v2, 0(r3)
3944 ; P9BE-NEXT: blr
3945 ;
3946 ; P9LE-LABEL: fromDiffMemConsAll:
3947 ; P9LE: # %bb.0: # %entry
3948 ; P9LE-NEXT: lxv v2, 0(r3)
3949 ; P9LE-NEXT: blr
3950 ;
3951 ; P8BE-LABEL: fromDiffMemConsAll:
3952 ; P8BE: # %bb.0: # %entry
3953 ; P8BE-NEXT: lxvd2x v2, 0, r3
3954 ; P8BE-NEXT: blr
3955 ;
3956 ; P8LE-LABEL: fromDiffMemConsAll:
3957 ; P8LE: # %bb.0: # %entry
3958 ; P8LE-NEXT: lxvd2x vs0, 0, r3
3959 ; P8LE-NEXT: xxswapd v2, vs0
3960 ; P8LE-NEXT: blr
3961 entry:
3962 %0 = load i64, ptr %arr, align 8
3963 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
3964 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 1
3965 %1 = load i64, ptr %arrayidx1, align 8
3966 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
3967 ret <2 x i64> %vecinit2
3968 }
3970 define <2 x i64> @fromDiffMemConsDll(ptr nocapture readonly %arr) {
3971 ; P9BE-LABEL: fromDiffMemConsDll:
3972 ; P9BE: # %bb.0: # %entry
3973 ; P9BE-NEXT: lxv v2, 16(r3)
3974 ; P9BE-NEXT: xxswapd v2, v2
3975 ; P9BE-NEXT: blr
3976 ;
3977 ; P9LE-LABEL: fromDiffMemConsDll:
3978 ; P9LE: # %bb.0: # %entry
3979 ; P9LE-NEXT: addi r3, r3, 16
3980 ; P9LE-NEXT: lxvd2x v2, 0, r3
3981 ; P9LE-NEXT: blr
3982 ;
3983 ; P8BE-LABEL: fromDiffMemConsDll:
3984 ; P8BE: # %bb.0: # %entry
3985 ; P8BE-NEXT: addi r3, r3, 16
3986 ; P8BE-NEXT: lxvd2x v2, 0, r3
3987 ; P8BE-NEXT: xxswapd v2, v2
3988 ; P8BE-NEXT: blr
3989 ;
3990 ; P8LE-LABEL: fromDiffMemConsDll:
3991 ; P8LE: # %bb.0: # %entry
3992 ; P8LE-NEXT: addi r3, r3, 16
3993 ; P8LE-NEXT: lxvd2x v2, 0, r3
3994 ; P8LE-NEXT: blr
3995 entry:
3996 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 3
3997 %0 = load i64, ptr %arrayidx, align 8
3998 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
3999 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 2
4000 %1 = load i64, ptr %arrayidx1, align 8
4001 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
4002 ret <2 x i64> %vecinit2
4003 }
4005 define <2 x i64> @fromDiffMemVarAll(ptr nocapture readonly %arr, i32 signext %elem) {
4006 ; P9BE-LABEL: fromDiffMemVarAll:
4007 ; P9BE: # %bb.0: # %entry
4008 ; P9BE-NEXT: sldi r4, r4, 3
4009 ; P9BE-NEXT: lxvx v2, r3, r4
4010 ; P9BE-NEXT: blr
4011 ;
4012 ; P9LE-LABEL: fromDiffMemVarAll:
4013 ; P9LE: # %bb.0: # %entry
4014 ; P9LE-NEXT: sldi r4, r4, 3
4015 ; P9LE-NEXT: lxvx v2, r3, r4
4016 ; P9LE-NEXT: blr
4017 ;
4018 ; P8BE-LABEL: fromDiffMemVarAll:
4019 ; P8BE: # %bb.0: # %entry
4020 ; P8BE-NEXT: sldi r4, r4, 3
4021 ; P8BE-NEXT: lxvd2x v2, r3, r4
4022 ; P8BE-NEXT: blr
4023 ;
4024 ; P8LE-LABEL: fromDiffMemVarAll:
4025 ; P8LE: # %bb.0: # %entry
4026 ; P8LE-NEXT: sldi r4, r4, 3
4027 ; P8LE-NEXT: lxvd2x vs0, r3, r4
4028 ; P8LE-NEXT: xxswapd v2, vs0
4029 ; P8LE-NEXT: blr
4030 entry:
4031 %idxprom = sext i32 %elem to i64
4032 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom
4033 %0 = load i64, ptr %arrayidx, align 8
4034 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
4035 %add = add nsw i32 %elem, 1
4036 %idxprom1 = sext i32 %add to i64
4037 %arrayidx2 = getelementptr inbounds i64, ptr %arr, i64 %idxprom1
4038 %1 = load i64, ptr %arrayidx2, align 8
4039 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
4040 ret <2 x i64> %vecinit3
4041 }
4043 define <2 x i64> @fromDiffMemVarDll(ptr nocapture readonly %arr, i32 signext %elem) {
4044 ; P9BE-LABEL: fromDiffMemVarDll:
4045 ; P9BE: # %bb.0: # %entry
4046 ; P9BE-NEXT: sldi r4, r4, 3
4047 ; P9BE-NEXT: add r3, r3, r4
4048 ; P9BE-NEXT: li r4, -8
4049 ; P9BE-NEXT: lxvx v2, r3, r4
4050 ; P9BE-NEXT: xxswapd v2, v2
4051 ; P9BE-NEXT: blr
4052 ;
4053 ; P9LE-LABEL: fromDiffMemVarDll:
4054 ; P9LE: # %bb.0: # %entry
4055 ; P9LE-NEXT: sldi r4, r4, 3
4056 ; P9LE-NEXT: add r3, r3, r4
4057 ; P9LE-NEXT: addi r3, r3, -8
4058 ; P9LE-NEXT: lxvd2x v2, 0, r3
4059 ; P9LE-NEXT: blr
4060 ;
4061 ; P8BE-LABEL: fromDiffMemVarDll:
4062 ; P8BE: # %bb.0: # %entry
4063 ; P8BE-NEXT: sldi r4, r4, 3
4064 ; P8BE-NEXT: add r3, r3, r4
4065 ; P8BE-NEXT: addi r3, r3, -8
4066 ; P8BE-NEXT: lxvd2x v2, 0, r3
4067 ; P8BE-NEXT: xxswapd v2, v2
4068 ; P8BE-NEXT: blr
4069 ;
4070 ; P8LE-LABEL: fromDiffMemVarDll:
4071 ; P8LE: # %bb.0: # %entry
4072 ; P8LE-NEXT: sldi r4, r4, 3
4073 ; P8LE-NEXT: add r3, r3, r4
4074 ; P8LE-NEXT: addi r3, r3, -8
4075 ; P8LE-NEXT: lxvd2x v2, 0, r3
4076 ; P8LE-NEXT: blr
4077 entry:
4078 %idxprom = sext i32 %elem to i64
4079 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom
4080 %0 = load i64, ptr %arrayidx, align 8
4081 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
4082 %sub = add nsw i32 %elem, -1
4083 %idxprom1 = sext i32 %sub to i64
4084 %arrayidx2 = getelementptr inbounds i64, ptr %arr, i64 %idxprom1
4085 %1 = load i64, ptr %arrayidx2, align 8
4086 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
4087 ret <2 x i64> %vecinit3
4088 }
4090 define <2 x i64> @fromRandMemConsll(ptr nocapture readonly %arr) {
4091 ; P9BE-LABEL: fromRandMemConsll:
4092 ; P9BE: # %bb.0: # %entry
4093 ; P9BE-NEXT: ld r4, 32(r3)
4094 ; P9BE-NEXT: ld r3, 144(r3)
4095 ; P9BE-NEXT: mtvsrdd v2, r4, r3
4096 ; P9BE-NEXT: blr
4097 ;
4098 ; P9LE-LABEL: fromRandMemConsll:
4099 ; P9LE: # %bb.0: # %entry
4100 ; P9LE-NEXT: ld r4, 32(r3)
4101 ; P9LE-NEXT: ld r3, 144(r3)
4102 ; P9LE-NEXT: mtvsrdd v2, r3, r4
4103 ; P9LE-NEXT: blr
4104 ;
4105 ; P8BE-LABEL: fromRandMemConsll:
4106 ; P8BE: # %bb.0: # %entry
4107 ; P8BE-NEXT: ld r4, 144(r3)
4108 ; P8BE-NEXT: ld r3, 32(r3)
4109 ; P8BE-NEXT: mtfprd f0, r4
4110 ; P8BE-NEXT: mtfprd f1, r3
4111 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
4112 ; P8BE-NEXT: blr
4113 ;
4114 ; P8LE-LABEL: fromRandMemConsll:
4115 ; P8LE: # %bb.0: # %entry
4116 ; P8LE-NEXT: ld r4, 32(r3)
4117 ; P8LE-NEXT: ld r3, 144(r3)
4118 ; P8LE-NEXT: mtfprd f0, r4
4119 ; P8LE-NEXT: mtfprd f1, r3
4120 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
4121 ; P8LE-NEXT: blr
4122 entry:
4123 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 4
4124 %0 = load i64, ptr %arrayidx, align 8
4125 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
4126 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 18
4127 %1 = load i64, ptr %arrayidx1, align 8
4128 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
4129 ret <2 x i64> %vecinit2
4130 }
4132 define <2 x i64> @fromRandMemVarll(ptr nocapture readonly %arr, i32 signext %elem) {
4133 ; P9BE-LABEL: fromRandMemVarll:
4134 ; P9BE: # %bb.0: # %entry
4135 ; P9BE-NEXT: sldi r4, r4, 3
4136 ; P9BE-NEXT: add r3, r3, r4
4137 ; P9BE-NEXT: ld r4, 32(r3)
4138 ; P9BE-NEXT: ld r3, 8(r3)
4139 ; P9BE-NEXT: mtvsrdd v2, r4, r3
4140 ; P9BE-NEXT: blr
4141 ;
4142 ; P9LE-LABEL: fromRandMemVarll:
4143 ; P9LE: # %bb.0: # %entry
4144 ; P9LE-NEXT: sldi r4, r4, 3
4145 ; P9LE-NEXT: add r3, r3, r4
4146 ; P9LE-NEXT: ld r4, 32(r3)
4147 ; P9LE-NEXT: ld r3, 8(r3)
4148 ; P9LE-NEXT: mtvsrdd v2, r3, r4
4149 ; P9LE-NEXT: blr
4150 ;
4151 ; P8BE-LABEL: fromRandMemVarll:
4152 ; P8BE: # %bb.0: # %entry
4153 ; P8BE-NEXT: sldi r4, r4, 3
4154 ; P8BE-NEXT: add r3, r3, r4
4155 ; P8BE-NEXT: ld r4, 8(r3)
4156 ; P8BE-NEXT: ld r3, 32(r3)
4157 ; P8BE-NEXT: mtfprd f0, r4
4158 ; P8BE-NEXT: mtfprd f1, r3
4159 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
4160 ; P8BE-NEXT: blr
4161 ;
4162 ; P8LE-LABEL: fromRandMemVarll:
4163 ; P8LE: # %bb.0: # %entry
4164 ; P8LE-NEXT: sldi r4, r4, 3
4165 ; P8LE-NEXT: add r3, r3, r4
4166 ; P8LE-NEXT: ld r4, 32(r3)
4167 ; P8LE-NEXT: ld r3, 8(r3)
4168 ; P8LE-NEXT: mtfprd f0, r4
4169 ; P8LE-NEXT: mtfprd f1, r3
4170 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
4171 ; P8LE-NEXT: blr
4172 entry:
4173 %add = add nsw i32 %elem, 4
4174 %idxprom = sext i32 %add to i64
4175 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom
4176 %0 = load i64, ptr %arrayidx, align 8
4177 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
4178 %add1 = add nsw i32 %elem, 1
4179 %idxprom2 = sext i32 %add1 to i64
4180 %arrayidx3 = getelementptr inbounds i64, ptr %arr, i64 %idxprom2
4181 %1 = load i64, ptr %arrayidx3, align 8
4182 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
4183 ret <2 x i64> %vecinit4
4184 }
4186 define <2 x i64> @spltRegValll(i64 %val) {
4187 ; P9BE-LABEL: spltRegValll:
4188 ; P9BE: # %bb.0: # %entry
4189 ; P9BE-NEXT: mtvsrdd v2, r3, r3
4190 ; P9BE-NEXT: blr
4191 ;
4192 ; P9LE-LABEL: spltRegValll:
4193 ; P9LE: # %bb.0: # %entry
4194 ; P9LE-NEXT: mtvsrdd v2, r3, r3
4195 ; P9LE-NEXT: blr
4196 ;
4197 ; P8BE-LABEL: spltRegValll:
4198 ; P8BE: # %bb.0: # %entry
4199 ; P8BE-NEXT: mtfprd f0, r3
4200 ; P8BE-NEXT: xxspltd v2, vs0, 0
4201 ; P8BE-NEXT: blr
4202 ;
4203 ; P8LE-LABEL: spltRegValll:
4204 ; P8LE: # %bb.0: # %entry
4205 ; P8LE-NEXT: mtfprd f0, r3
4206 ; P8LE-NEXT: xxspltd v2, vs0, 0
4207 ; P8LE-NEXT: blr
4208 entry:
4209 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0
4210 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
4211 ret <2 x i64> %splat.splat
4212 }
4214 define <2 x i64> @spltMemValll(ptr nocapture readonly %ptr) {
4215 ; P9BE-LABEL: spltMemValll:
4216 ; P9BE: # %bb.0: # %entry
4217 ; P9BE-NEXT: lxvdsx v2, 0, r3
4218 ; P9BE-NEXT: blr
4219 ;
4220 ; P9LE-LABEL: spltMemValll:
4221 ; P9LE: # %bb.0: # %entry
4222 ; P9LE-NEXT: lxvdsx v2, 0, r3
4223 ; P9LE-NEXT: blr
4224 ;
4225 ; P8BE-LABEL: spltMemValll:
4226 ; P8BE: # %bb.0: # %entry
4227 ; P8BE-NEXT: lxvdsx v2, 0, r3
4228 ; P8BE-NEXT: blr
4229 ;
4230 ; P8LE-LABEL: spltMemValll:
4231 ; P8LE: # %bb.0: # %entry
4232 ; P8LE-NEXT: lxvdsx v2, 0, r3
4233 ; P8LE-NEXT: blr
4234 entry:
4235 %0 = load i64, ptr %ptr, align 8
4236 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0
4237 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
4238 ret <2 x i64> %splat.splat
4239 }
4241 define <2 x i64> @spltCnstConvftoll() {
4242 ; P9BE-LABEL: spltCnstConvftoll:
4243 ; P9BE: # %bb.0: # %entry
4244 ; P9BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha
4245 ; P9BE-NEXT: addi r3, r3, .LCPI78_0@toc@l
4246 ; P9BE-NEXT: lxv v2, 0(r3)
4247 ; P9BE-NEXT: blr
4248 ;
4249 ; P9LE-LABEL: spltCnstConvftoll:
4250 ; P9LE: # %bb.0: # %entry
4251 ; P9LE-NEXT: addis r3, r2, .LCPI78_0@toc@ha
4252 ; P9LE-NEXT: addi r3, r3, .LCPI78_0@toc@l
4253 ; P9LE-NEXT: lxv v2, 0(r3)
4254 ; P9LE-NEXT: blr
4255 ;
4256 ; P8BE-LABEL: spltCnstConvftoll:
4257 ; P8BE: # %bb.0: # %entry
4258 ; P8BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha
4259 ; P8BE-NEXT: addi r3, r3, .LCPI78_0@toc@l
4260 ; P8BE-NEXT: lxvd2x v2, 0, r3
4261 ; P8BE-NEXT: blr
4262 ;
4263 ; P8LE-LABEL: spltCnstConvftoll:
4264 ; P8LE: # %bb.0: # %entry
4265 ; P8LE-NEXT: addis r3, r2, .LCPI78_0@toc@ha
4266 ; P8LE-NEXT: addi r3, r3, .LCPI78_0@toc@l
4267 ; P8LE-NEXT: lxvd2x v2, 0, r3
4268 ; P8LE-NEXT: blr
4269 entry:
4270 ret <2 x i64> <i64 4, i64 4>
4271 }
4273 define <2 x i64> @fromRegsConvftoll(float %a, float %b) {
4274 ; P9BE-LABEL: fromRegsConvftoll:
4275 ; P9BE: # %bb.0: # %entry
4276 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4277 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4278 ; P9BE-NEXT: xxmrghd vs0, vs1, vs2
4279 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4280 ; P9BE-NEXT: blr
4281 ;
4282 ; P9LE-LABEL: fromRegsConvftoll:
4283 ; P9LE: # %bb.0: # %entry
4284 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4285 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4286 ; P9LE-NEXT: xxmrghd vs0, vs2, vs1
4287 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4288 ; P9LE-NEXT: blr
4289 ;
4290 ; P8BE-LABEL: fromRegsConvftoll:
4291 ; P8BE: # %bb.0: # %entry
4292 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4293 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4294 ; P8BE-NEXT: xxmrghd vs0, vs1, vs2
4295 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4296 ; P8BE-NEXT: blr
4297 ;
4298 ; P8LE-LABEL: fromRegsConvftoll:
4299 ; P8LE: # %bb.0: # %entry
4300 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4301 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4302 ; P8LE-NEXT: xxmrghd vs0, vs2, vs1
4303 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4304 ; P8LE-NEXT: blr
4305 entry:
4306 %conv = fptosi float %a to i64
4307 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4308 %conv1 = fptosi float %b to i64
4309 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1
4310 ret <2 x i64> %vecinit2
4311 }
4313 define <2 x i64> @fromDiffConstsConvftoll() {
4314 ; P9BE-LABEL: fromDiffConstsConvftoll:
4315 ; P9BE: # %bb.0: # %entry
4316 ; P9BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha
4317 ; P9BE-NEXT: addi r3, r3, .LCPI80_0@toc@l
4318 ; P9BE-NEXT: lxv v2, 0(r3)
4319 ; P9BE-NEXT: blr
4320 ;
4321 ; P9LE-LABEL: fromDiffConstsConvftoll:
4322 ; P9LE: # %bb.0: # %entry
4323 ; P9LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha
4324 ; P9LE-NEXT: addi r3, r3, .LCPI80_0@toc@l
4325 ; P9LE-NEXT: lxv v2, 0(r3)
4326 ; P9LE-NEXT: blr
4327 ;
4328 ; P8BE-LABEL: fromDiffConstsConvftoll:
4329 ; P8BE: # %bb.0: # %entry
4330 ; P8BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha
4331 ; P8BE-NEXT: addi r3, r3, .LCPI80_0@toc@l
4332 ; P8BE-NEXT: lxvd2x v2, 0, r3
4333 ; P8BE-NEXT: blr
4334 ;
4335 ; P8LE-LABEL: fromDiffConstsConvftoll:
4336 ; P8LE: # %bb.0: # %entry
4337 ; P8LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha
4338 ; P8LE-NEXT: addi r3, r3, .LCPI80_0@toc@l
4339 ; P8LE-NEXT: lxvd2x vs0, 0, r3
4340 ; P8LE-NEXT: xxswapd v2, vs0
4341 ; P8LE-NEXT: blr
4342 entry:
4343 ret <2 x i64> <i64 24, i64 234>
4344 }
4346 define <2 x i64> @fromDiffMemConsAConvftoll(ptr nocapture readonly %ptr) {
4347 ; P9BE-LABEL: fromDiffMemConsAConvftoll:
4348 ; P9BE: # %bb.0: # %entry
4349 ; P9BE-NEXT: lfs f0, 0(r3)
4350 ; P9BE-NEXT: lfs f1, 4(r3)
4351 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
4352 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4353 ; P9BE-NEXT: blr
4354 ;
4355 ; P9LE-LABEL: fromDiffMemConsAConvftoll:
4356 ; P9LE: # %bb.0: # %entry
4357 ; P9LE-NEXT: lfs f0, 0(r3)
4358 ; P9LE-NEXT: lfs f1, 4(r3)
4359 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
4360 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4361 ; P9LE-NEXT: blr
4362 ;
4363 ; P8BE-LABEL: fromDiffMemConsAConvftoll:
4364 ; P8BE: # %bb.0: # %entry
4365 ; P8BE-NEXT: lfs f0, 0(r3)
4366 ; P8BE-NEXT: lfs f1, 4(r3)
4367 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
4368 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4369 ; P8BE-NEXT: blr
4370 ;
4371 ; P8LE-LABEL: fromDiffMemConsAConvftoll:
4372 ; P8LE: # %bb.0: # %entry
4373 ; P8LE-NEXT: lfs f0, 0(r3)
4374 ; P8LE-NEXT: lfs f1, 4(r3)
4375 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
4376 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4377 ; P8LE-NEXT: blr
4378 entry:
4379 %0 = load float, ptr %ptr, align 4
4380 %conv = fptosi float %0 to i64
4381 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4382 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 1
4383 %1 = load float, ptr %arrayidx1, align 4
4384 %conv2 = fptosi float %1 to i64
4385 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
4386 ret <2 x i64> %vecinit3
4387 }
4389 define <2 x i64> @fromDiffMemConsDConvftoll(ptr nocapture readonly %ptr) {
4390 ; P9BE-LABEL: fromDiffMemConsDConvftoll:
4391 ; P9BE: # %bb.0: # %entry
4392 ; P9BE-NEXT: lfs f0, 12(r3)
4393 ; P9BE-NEXT: lfs f1, 8(r3)
4394 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
4395 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4396 ; P9BE-NEXT: blr
4397 ;
4398 ; P9LE-LABEL: fromDiffMemConsDConvftoll:
4399 ; P9LE: # %bb.0: # %entry
4400 ; P9LE-NEXT: lfs f0, 12(r3)
4401 ; P9LE-NEXT: lfs f1, 8(r3)
4402 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
4403 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4404 ; P9LE-NEXT: blr
4405 ;
4406 ; P8BE-LABEL: fromDiffMemConsDConvftoll:
4407 ; P8BE: # %bb.0: # %entry
4408 ; P8BE-NEXT: lfs f0, 12(r3)
4409 ; P8BE-NEXT: lfs f1, 8(r3)
4410 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
4411 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4412 ; P8BE-NEXT: blr
4413 ;
4414 ; P8LE-LABEL: fromDiffMemConsDConvftoll:
4415 ; P8LE: # %bb.0: # %entry
4416 ; P8LE-NEXT: lfs f0, 12(r3)
4417 ; P8LE-NEXT: lfs f1, 8(r3)
4418 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
4419 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4420 ; P8LE-NEXT: blr
4421 entry:
4422 %arrayidx = getelementptr inbounds float, ptr %ptr, i64 3
4423 %0 = load float, ptr %arrayidx, align 4
4424 %conv = fptosi float %0 to i64
4425 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4426 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 2
4427 %1 = load float, ptr %arrayidx1, align 4
4428 %conv2 = fptosi float %1 to i64
4429 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
4430 ret <2 x i64> %vecinit3
4431 }
4433 define <2 x i64> @fromDiffMemVarAConvftoll(ptr nocapture readonly %arr, i32 signext %elem) {
4434 ; P9BE-LABEL: fromDiffMemVarAConvftoll:
4435 ; P9BE: # %bb.0: # %entry
4436 ; P9BE-NEXT: sldi r4, r4, 2
4437 ; P9BE-NEXT: lfsux f0, r3, r4
4438 ; P9BE-NEXT: lfs f1, 4(r3)
4439 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
4440 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4441 ; P9BE-NEXT: blr
4442 ;
4443 ; P9LE-LABEL: fromDiffMemVarAConvftoll:
4444 ; P9LE: # %bb.0: # %entry
4445 ; P9LE-NEXT: sldi r4, r4, 2
4446 ; P9LE-NEXT: lfsux f0, r3, r4
4447 ; P9LE-NEXT: lfs f1, 4(r3)
4448 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
4449 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4450 ; P9LE-NEXT: blr
4451 ;
4452 ; P8BE-LABEL: fromDiffMemVarAConvftoll:
4453 ; P8BE: # %bb.0: # %entry
4454 ; P8BE-NEXT: sldi r4, r4, 2
4455 ; P8BE-NEXT: lfsux f0, r3, r4
4456 ; P8BE-NEXT: lfs f1, 4(r3)
4457 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
4458 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4459 ; P8BE-NEXT: blr
4460 ;
4461 ; P8LE-LABEL: fromDiffMemVarAConvftoll:
4462 ; P8LE: # %bb.0: # %entry
4463 ; P8LE-NEXT: sldi r4, r4, 2
4464 ; P8LE-NEXT: lfsux f0, r3, r4
4465 ; P8LE-NEXT: lfs f1, 4(r3)
4466 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
4467 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4468 ; P8LE-NEXT: blr
4469 entry:
4470 %idxprom = sext i32 %elem to i64
4471 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom
4472 %0 = load float, ptr %arrayidx, align 4
4473 %conv = fptosi float %0 to i64
4474 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4475 %add = add nsw i32 %elem, 1
4476 %idxprom1 = sext i32 %add to i64
4477 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1
4478 %1 = load float, ptr %arrayidx2, align 4
4479 %conv3 = fptosi float %1 to i64
4480 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
4481 ret <2 x i64> %vecinit4
4482 }
4484 define <2 x i64> @fromDiffMemVarDConvftoll(ptr nocapture readonly %arr, i32 signext %elem) {
4485 ; P9BE-LABEL: fromDiffMemVarDConvftoll:
4486 ; P9BE: # %bb.0: # %entry
4487 ; P9BE-NEXT: sldi r4, r4, 2
4488 ; P9BE-NEXT: lfsux f0, r3, r4
4489 ; P9BE-NEXT: lfs f1, -4(r3)
4490 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
4491 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4492 ; P9BE-NEXT: blr
4493 ;
4494 ; P9LE-LABEL: fromDiffMemVarDConvftoll:
4495 ; P9LE: # %bb.0: # %entry
4496 ; P9LE-NEXT: sldi r4, r4, 2
4497 ; P9LE-NEXT: lfsux f0, r3, r4
4498 ; P9LE-NEXT: lfs f1, -4(r3)
4499 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
4500 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4501 ; P9LE-NEXT: blr
4502 ;
4503 ; P8BE-LABEL: fromDiffMemVarDConvftoll:
4504 ; P8BE: # %bb.0: # %entry
4505 ; P8BE-NEXT: sldi r4, r4, 2
4506 ; P8BE-NEXT: lfsux f0, r3, r4
4507 ; P8BE-NEXT: lfs f1, -4(r3)
4508 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
4509 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4510 ; P8BE-NEXT: blr
4511 ;
4512 ; P8LE-LABEL: fromDiffMemVarDConvftoll:
4513 ; P8LE: # %bb.0: # %entry
4514 ; P8LE-NEXT: sldi r4, r4, 2
4515 ; P8LE-NEXT: lfsux f0, r3, r4
4516 ; P8LE-NEXT: lfs f1, -4(r3)
4517 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
4518 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4519 ; P8LE-NEXT: blr
4520 entry:
4521 %idxprom = sext i32 %elem to i64
4522 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom
4523 %0 = load float, ptr %arrayidx, align 4
4524 %conv = fptosi float %0 to i64
4525 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4526 %sub = add nsw i32 %elem, -1
4527 %idxprom1 = sext i32 %sub to i64
4528 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1
4529 %1 = load float, ptr %arrayidx2, align 4
4530 %conv3 = fptosi float %1 to i64
4531 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
4532 ret <2 x i64> %vecinit4
4533 }
4535 define <2 x i64> @spltRegValConvftoll(float %val) {
4536 ; P9BE-LABEL: spltRegValConvftoll:
4537 ; P9BE: # %bb.0: # %entry
4538 ; P9BE-NEXT: xscvdpsxds f0, f1
4539 ; P9BE-NEXT: xxspltd v2, f0, 0
4540 ; P9BE-NEXT: blr
4541 ;
4542 ; P9LE-LABEL: spltRegValConvftoll:
4543 ; P9LE: # %bb.0: # %entry
4544 ; P9LE-NEXT: xscvdpsxds f0, f1
4545 ; P9LE-NEXT: xxspltd v2, f0, 0
4546 ; P9LE-NEXT: blr
4547 ;
4548 ; P8BE-LABEL: spltRegValConvftoll:
4549 ; P8BE: # %bb.0: # %entry
4550 ; P8BE-NEXT: xscvdpsxds f0, f1
4551 ; P8BE-NEXT: xxspltd v2, f0, 0
4552 ; P8BE-NEXT: blr
4553 ;
4554 ; P8LE-LABEL: spltRegValConvftoll:
4555 ; P8LE: # %bb.0: # %entry
4556 ; P8LE-NEXT: xscvdpsxds f0, f1
4557 ; P8LE-NEXT: xxspltd v2, f0, 0
4558 ; P8LE-NEXT: blr
4559 entry:
4560 %conv = fptosi float %val to i64
4561 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
4562 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
4563 ret <2 x i64> %splat.splat
4564 }
4566 define <2 x i64> @spltMemValConvftoll(ptr nocapture readonly %ptr) {
4567 ; P9BE-LABEL: spltMemValConvftoll:
4568 ; P9BE: # %bb.0: # %entry
4569 ; P9BE-NEXT: lfs f0, 0(r3)
4570 ; P9BE-NEXT: xscvdpsxds f0, f0
4571 ; P9BE-NEXT: xxspltd v2, f0, 0
4572 ; P9BE-NEXT: blr
4573 ;
4574 ; P9LE-LABEL: spltMemValConvftoll:
4575 ; P9LE: # %bb.0: # %entry
4576 ; P9LE-NEXT: lfs f0, 0(r3)
4577 ; P9LE-NEXT: xscvdpsxds f0, f0
4578 ; P9LE-NEXT: xxspltd v2, vs0, 0
4579 ; P9LE-NEXT: blr
4580 ;
4581 ; P8BE-LABEL: spltMemValConvftoll:
4582 ; P8BE: # %bb.0: # %entry
4583 ; P8BE-NEXT: lfsx f0, 0, r3
4584 ; P8BE-NEXT: xscvdpsxds f0, f0
4585 ; P8BE-NEXT: xxspltd v2, f0, 0
4586 ; P8BE-NEXT: blr
4587 ;
4588 ; P8LE-LABEL: spltMemValConvftoll:
4589 ; P8LE: # %bb.0: # %entry
4590 ; P8LE-NEXT: lfsx f0, 0, r3
4591 ; P8LE-NEXT: xscvdpsxds f0, f0
4592 ; P8LE-NEXT: xxspltd v2, vs0, 0
4593 ; P8LE-NEXT: blr
4594 entry:
4595 %0 = load float, ptr %ptr, align 4
4596 %conv = fptosi float %0 to i64
4597 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
4598 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
4599 ret <2 x i64> %splat.splat
4600 }
4602 define <2 x i64> @spltCnstConvdtoll() {
4603 ; P9BE-LABEL: spltCnstConvdtoll:
4604 ; P9BE: # %bb.0: # %entry
4605 ; P9BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha
4606 ; P9BE-NEXT: addi r3, r3, .LCPI87_0@toc@l
4607 ; P9BE-NEXT: lxv v2, 0(r3)
4608 ; P9BE-NEXT: blr
4609 ;
4610 ; P9LE-LABEL: spltCnstConvdtoll:
4611 ; P9LE: # %bb.0: # %entry
4612 ; P9LE-NEXT: addis r3, r2, .LCPI87_0@toc@ha
4613 ; P9LE-NEXT: addi r3, r3, .LCPI87_0@toc@l
4614 ; P9LE-NEXT: lxv v2, 0(r3)
4615 ; P9LE-NEXT: blr
4616 ;
4617 ; P8BE-LABEL: spltCnstConvdtoll:
4618 ; P8BE: # %bb.0: # %entry
4619 ; P8BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha
4620 ; P8BE-NEXT: addi r3, r3, .LCPI87_0@toc@l
4621 ; P8BE-NEXT: lxvd2x v2, 0, r3
4622 ; P8BE-NEXT: blr
4623 ;
4624 ; P8LE-LABEL: spltCnstConvdtoll:
4625 ; P8LE: # %bb.0: # %entry
4626 ; P8LE-NEXT: addis r3, r2, .LCPI87_0@toc@ha
4627 ; P8LE-NEXT: addi r3, r3, .LCPI87_0@toc@l
4628 ; P8LE-NEXT: lxvd2x v2, 0, r3
4629 ; P8LE-NEXT: blr
4630 entry:
4631 ret <2 x i64> <i64 4, i64 4>
4632 }
4634 define <2 x i64> @fromRegsConvdtoll(double %a, double %b) {
4635 ; P9BE-LABEL: fromRegsConvdtoll:
4636 ; P9BE: # %bb.0: # %entry
4637 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4638 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4639 ; P9BE-NEXT: xxmrghd vs0, vs1, vs2
4640 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4641 ; P9BE-NEXT: blr
4642 ;
4643 ; P9LE-LABEL: fromRegsConvdtoll:
4644 ; P9LE: # %bb.0: # %entry
4645 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4646 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4647 ; P9LE-NEXT: xxmrghd vs0, vs2, vs1
4648 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4649 ; P9LE-NEXT: blr
4650 ;
4651 ; P8BE-LABEL: fromRegsConvdtoll:
4652 ; P8BE: # %bb.0: # %entry
4653 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4654 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4655 ; P8BE-NEXT: xxmrghd vs0, vs1, vs2
4656 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4657 ; P8BE-NEXT: blr
4658 ;
4659 ; P8LE-LABEL: fromRegsConvdtoll:
4660 ; P8LE: # %bb.0: # %entry
4661 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4662 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4663 ; P8LE-NEXT: xxmrghd vs0, vs2, vs1
4664 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4665 ; P8LE-NEXT: blr
4666 entry:
4667 %conv = fptosi double %a to i64
4668 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4669 %conv1 = fptosi double %b to i64
4670 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1
4671 ret <2 x i64> %vecinit2
4672 }
4674 define <2 x i64> @fromDiffConstsConvdtoll() {
4675 ; P9BE-LABEL: fromDiffConstsConvdtoll:
4676 ; P9BE: # %bb.0: # %entry
4677 ; P9BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha
4678 ; P9BE-NEXT: addi r3, r3, .LCPI89_0@toc@l
4679 ; P9BE-NEXT: lxv v2, 0(r3)
4680 ; P9BE-NEXT: blr
4681 ;
4682 ; P9LE-LABEL: fromDiffConstsConvdtoll:
4683 ; P9LE: # %bb.0: # %entry
4684 ; P9LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha
4685 ; P9LE-NEXT: addi r3, r3, .LCPI89_0@toc@l
4686 ; P9LE-NEXT: lxv v2, 0(r3)
4687 ; P9LE-NEXT: blr
4688 ;
4689 ; P8BE-LABEL: fromDiffConstsConvdtoll:
4690 ; P8BE: # %bb.0: # %entry
4691 ; P8BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha
4692 ; P8BE-NEXT: addi r3, r3, .LCPI89_0@toc@l
4693 ; P8BE-NEXT: lxvd2x v2, 0, r3
4694 ; P8BE-NEXT: blr
4695 ;
4696 ; P8LE-LABEL: fromDiffConstsConvdtoll:
4697 ; P8LE: # %bb.0: # %entry
4698 ; P8LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha
4699 ; P8LE-NEXT: addi r3, r3, .LCPI89_0@toc@l
4700 ; P8LE-NEXT: lxvd2x vs0, 0, r3
4701 ; P8LE-NEXT: xxswapd v2, vs0
4702 ; P8LE-NEXT: blr
4703 entry:
4704 ret <2 x i64> <i64 24, i64 234>
4705 }
4707 define <2 x i64> @fromDiffMemConsAConvdtoll(ptr nocapture readonly %ptr) {
4708 ; P9BE-LABEL: fromDiffMemConsAConvdtoll:
4709 ; P9BE: # %bb.0: # %entry
4710 ; P9BE-NEXT: lxv vs0, 0(r3)
4711 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4712 ; P9BE-NEXT: blr
4713 ;
4714 ; P9LE-LABEL: fromDiffMemConsAConvdtoll:
4715 ; P9LE: # %bb.0: # %entry
4716 ; P9LE-NEXT: lxv vs0, 0(r3)
4717 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4718 ; P9LE-NEXT: blr
4719 ;
4720 ; P8BE-LABEL: fromDiffMemConsAConvdtoll:
4721 ; P8BE: # %bb.0: # %entry
4722 ; P8BE-NEXT: lxvd2x vs0, 0, r3
4723 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4724 ; P8BE-NEXT: blr
4725 ;
4726 ; P8LE-LABEL: fromDiffMemConsAConvdtoll:
4727 ; P8LE: # %bb.0: # %entry
4728 ; P8LE-NEXT: lxvd2x vs0, 0, r3
4729 ; P8LE-NEXT: xxswapd vs0, vs0
4730 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4731 ; P8LE-NEXT: blr
4732 entry:
4733 %0 = load <2 x double>, ptr %ptr, align 8
4734 %1 = fptosi <2 x double> %0 to <2 x i64>
4735 ret <2 x i64> %1
4736 }
4738 define <2 x i64> @fromDiffMemConsDConvdtoll(ptr nocapture readonly %ptr) {
4739 ; P9BE-LABEL: fromDiffMemConsDConvdtoll:
4740 ; P9BE: # %bb.0: # %entry
4741 ; P9BE-NEXT: lxv vs0, 16(r3)
4742 ; P9BE-NEXT: xxswapd vs0, vs0
4743 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4744 ; P9BE-NEXT: blr
4745 ;
4746 ; P9LE-LABEL: fromDiffMemConsDConvdtoll:
4747 ; P9LE: # %bb.0: # %entry
4748 ; P9LE-NEXT: addi r3, r3, 16
4749 ; P9LE-NEXT: lxvd2x vs0, 0, r3
4750 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4751 ; P9LE-NEXT: blr
4752 ;
4753 ; P8BE-LABEL: fromDiffMemConsDConvdtoll:
4754 ; P8BE: # %bb.0: # %entry
4755 ; P8BE-NEXT: addi r3, r3, 16
4756 ; P8BE-NEXT: lxvd2x vs0, 0, r3
4757 ; P8BE-NEXT: xxswapd vs0, vs0
4758 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4759 ; P8BE-NEXT: blr
4760 ;
4761 ; P8LE-LABEL: fromDiffMemConsDConvdtoll:
4762 ; P8LE: # %bb.0: # %entry
4763 ; P8LE-NEXT: addi r3, r3, 16
4764 ; P8LE-NEXT: lxvd2x vs0, 0, r3
4765 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4766 ; P8LE-NEXT: blr
4767 entry:
4768 %arrayidx = getelementptr inbounds double, ptr %ptr, i64 3
4769 %0 = load double, ptr %arrayidx, align 8
4770 %conv = fptosi double %0 to i64
4771 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4772 %arrayidx1 = getelementptr inbounds double, ptr %ptr, i64 2
4773 %1 = load double, ptr %arrayidx1, align 8
4774 %conv2 = fptosi double %1 to i64
4775 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
4776 ret <2 x i64> %vecinit3
4777 }
4779 define <2 x i64> @fromDiffMemVarAConvdtoll(ptr nocapture readonly %arr, i32 signext %elem) {
4780 ; P9BE-LABEL: fromDiffMemVarAConvdtoll:
4781 ; P9BE: # %bb.0: # %entry
4782 ; P9BE-NEXT: sldi r4, r4, 3
4783 ; P9BE-NEXT: lxvx vs0, r3, r4
4784 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4785 ; P9BE-NEXT: blr
4786 ;
4787 ; P9LE-LABEL: fromDiffMemVarAConvdtoll:
4788 ; P9LE: # %bb.0: # %entry
4789 ; P9LE-NEXT: sldi r4, r4, 3
4790 ; P9LE-NEXT: lxvx vs0, r3, r4
4791 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4792 ; P9LE-NEXT: blr
4793 ;
4794 ; P8BE-LABEL: fromDiffMemVarAConvdtoll:
4795 ; P8BE: # %bb.0: # %entry
4796 ; P8BE-NEXT: sldi r4, r4, 3
4797 ; P8BE-NEXT: lxvd2x vs0, r3, r4
4798 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4799 ; P8BE-NEXT: blr
4800 ;
4801 ; P8LE-LABEL: fromDiffMemVarAConvdtoll:
4802 ; P8LE: # %bb.0: # %entry
4803 ; P8LE-NEXT: sldi r4, r4, 3
4804 ; P8LE-NEXT: lxvd2x vs0, r3, r4
4805 ; P8LE-NEXT: xxswapd vs0, vs0
4806 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4807 ; P8LE-NEXT: blr
4808 entry:
4809 %idxprom = sext i32 %elem to i64
4810 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom
4811 %0 = load double, ptr %arrayidx, align 8
4812 %conv = fptosi double %0 to i64
4813 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4814 %add = add nsw i32 %elem, 1
4815 %idxprom1 = sext i32 %add to i64
4816 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1
4817 %1 = load double, ptr %arrayidx2, align 8
4818 %conv3 = fptosi double %1 to i64
4819 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
4820 ret <2 x i64> %vecinit4
4821 }
4823 define <2 x i64> @fromDiffMemVarDConvdtoll(ptr nocapture readonly %arr, i32 signext %elem) {
4824 ; P9BE-LABEL: fromDiffMemVarDConvdtoll:
4825 ; P9BE: # %bb.0: # %entry
4826 ; P9BE-NEXT: sldi r4, r4, 3
4827 ; P9BE-NEXT: add r3, r3, r4
4828 ; P9BE-NEXT: li r4, -8
4829 ; P9BE-NEXT: lxvx vs0, r3, r4
4830 ; P9BE-NEXT: xxswapd vs0, vs0
4831 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4832 ; P9BE-NEXT: blr
4833 ;
4834 ; P9LE-LABEL: fromDiffMemVarDConvdtoll:
4835 ; P9LE: # %bb.0: # %entry
4836 ; P9LE-NEXT: sldi r4, r4, 3
4837 ; P9LE-NEXT: add r3, r3, r4
4838 ; P9LE-NEXT: addi r3, r3, -8
4839 ; P9LE-NEXT: lxvd2x vs0, 0, r3
4840 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4841 ; P9LE-NEXT: blr
4842 ;
4843 ; P8BE-LABEL: fromDiffMemVarDConvdtoll:
4844 ; P8BE: # %bb.0: # %entry
4845 ; P8BE-NEXT: sldi r4, r4, 3
4846 ; P8BE-NEXT: add r3, r3, r4
4847 ; P8BE-NEXT: addi r3, r3, -8
4848 ; P8BE-NEXT: lxvd2x vs0, 0, r3
4849 ; P8BE-NEXT: xxswapd vs0, vs0
4850 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4851 ; P8BE-NEXT: blr
4852 ;
4853 ; P8LE-LABEL: fromDiffMemVarDConvdtoll:
4854 ; P8LE: # %bb.0: # %entry
4855 ; P8LE-NEXT: sldi r4, r4, 3
4856 ; P8LE-NEXT: add r3, r3, r4
4857 ; P8LE-NEXT: addi r3, r3, -8
4858 ; P8LE-NEXT: lxvd2x vs0, 0, r3
4859 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4860 ; P8LE-NEXT: blr
4861 entry:
4862 %idxprom = sext i32 %elem to i64
4863 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom
4864 %0 = load double, ptr %arrayidx, align 8
4865 %conv = fptosi double %0 to i64
4866 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4867 %sub = add nsw i32 %elem, -1
4868 %idxprom1 = sext i32 %sub to i64
4869 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1
4870 %1 = load double, ptr %arrayidx2, align 8
4871 %conv3 = fptosi double %1 to i64
4872 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
4873 ret <2 x i64> %vecinit4
4874 }
4876 define <2 x i64> @spltRegValConvdtoll(double %val) {
4877 ; P9BE-LABEL: spltRegValConvdtoll:
4878 ; P9BE: # %bb.0: # %entry
4879 ; P9BE-NEXT: xscvdpsxds f0, f1
4880 ; P9BE-NEXT: xxspltd v2, vs0, 0
4881 ; P9BE-NEXT: blr
4882 ;
4883 ; P9LE-LABEL: spltRegValConvdtoll:
4884 ; P9LE: # %bb.0: # %entry
4885 ; P9LE-NEXT: xscvdpsxds f0, f1
4886 ; P9LE-NEXT: xxspltd v2, vs0, 0
4887 ; P9LE-NEXT: blr
4888 ;
4889 ; P8BE-LABEL: spltRegValConvdtoll:
4890 ; P8BE: # %bb.0: # %entry
4891 ; P8BE-NEXT: xscvdpsxds f0, f1
4892 ; P8BE-NEXT: xxspltd v2, vs0, 0
4893 ; P8BE-NEXT: blr
4894 ;
4895 ; P8LE-LABEL: spltRegValConvdtoll:
4896 ; P8LE: # %bb.0: # %entry
4897 ; P8LE-NEXT: xscvdpsxds f0, f1
4898 ; P8LE-NEXT: xxspltd v2, vs0, 0
4899 ; P8LE-NEXT: blr
4900 entry:
4901 %conv = fptosi double %val to i64
4902 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
4903 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
4904 ret <2 x i64> %splat.splat
4905 }
4907 define <2 x i64> @spltMemValConvdtoll(ptr nocapture readonly %ptr) {
4908 ; P9BE-LABEL: spltMemValConvdtoll:
4909 ; P9BE: # %bb.0: # %entry
4910 ; P9BE-NEXT: lxvdsx vs0, 0, r3
4911 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4912 ; P9BE-NEXT: blr
4913 ;
4914 ; P9LE-LABEL: spltMemValConvdtoll:
4915 ; P9LE: # %bb.0: # %entry
4916 ; P9LE-NEXT: lxvdsx vs0, 0, r3
4917 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4918 ; P9LE-NEXT: blr
4919 ;
4920 ; P8BE-LABEL: spltMemValConvdtoll:
4921 ; P8BE: # %bb.0: # %entry
4922 ; P8BE-NEXT: lxvdsx vs0, 0, r3
4923 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4924 ; P8BE-NEXT: blr
4925 ;
4926 ; P8LE-LABEL: spltMemValConvdtoll:
4927 ; P8LE: # %bb.0: # %entry
4928 ; P8LE-NEXT: lxvdsx vs0, 0, r3
4929 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4930 ; P8LE-NEXT: blr
4931 entry:
4932 %0 = load double, ptr %ptr, align 8
4933 %conv = fptosi double %0 to i64
4934 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
4935 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
4936 ret <2 x i64> %splat.splat
4937 }
4939 define <2 x i64> @allZeroull() {
4940 ; P9BE-LABEL: allZeroull:
4941 ; P9BE: # %bb.0: # %entry
4942 ; P9BE-NEXT: xxlxor v2, v2, v2
4943 ; P9BE-NEXT: blr
4944 ;
4945 ; P9LE-LABEL: allZeroull:
4946 ; P9LE: # %bb.0: # %entry
4947 ; P9LE-NEXT: xxlxor v2, v2, v2
4948 ; P9LE-NEXT: blr
4949 ;
4950 ; P8BE-LABEL: allZeroull:
4951 ; P8BE: # %bb.0: # %entry
4952 ; P8BE-NEXT: xxlxor v2, v2, v2
4953 ; P8BE-NEXT: blr
4954 ;
4955 ; P8LE-LABEL: allZeroull:
4956 ; P8LE: # %bb.0: # %entry
4957 ; P8LE-NEXT: xxlxor v2, v2, v2
4958 ; P8LE-NEXT: blr
4959 entry:
4960 ret <2 x i64> zeroinitializer
4961 }
4963 define <2 x i64> @spltConst1ull() {
4964 ; P9BE-LABEL: spltConst1ull:
4965 ; P9BE: # %bb.0: # %entry
4966 ; P9BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha
4967 ; P9BE-NEXT: addi r3, r3, .LCPI97_0@toc@l
4968 ; P9BE-NEXT: lxv v2, 0(r3)
4969 ; P9BE-NEXT: blr
4970 ;
4971 ; P9LE-LABEL: spltConst1ull:
4972 ; P9LE: # %bb.0: # %entry
4973 ; P9LE-NEXT: addis r3, r2, .LCPI97_0@toc@ha
4974 ; P9LE-NEXT: addi r3, r3, .LCPI97_0@toc@l
4975 ; P9LE-NEXT: lxv v2, 0(r3)
4976 ; P9LE-NEXT: blr
4977 ;
4978 ; P8BE-LABEL: spltConst1ull:
4979 ; P8BE: # %bb.0: # %entry
4980 ; P8BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha
4981 ; P8BE-NEXT: addi r3, r3, .LCPI97_0@toc@l
4982 ; P8BE-NEXT: lxvd2x v2, 0, r3
4983 ; P8BE-NEXT: blr
4984 ;
4985 ; P8LE-LABEL: spltConst1ull:
4986 ; P8LE: # %bb.0: # %entry
4987 ; P8LE-NEXT: addis r3, r2, .LCPI97_0@toc@ha
4988 ; P8LE-NEXT: addi r3, r3, .LCPI97_0@toc@l
4989 ; P8LE-NEXT: lxvd2x v2, 0, r3
4990 ; P8LE-NEXT: blr
4991 entry:
4992 ret <2 x i64> <i64 1, i64 1>
4993 }
4995 define <2 x i64> @spltConst16kull() {
4996 ; P9BE-LABEL: spltConst16kull:
4997 ; P9BE: # %bb.0: # %entry
4998 ; P9BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha
4999 ; P9BE-NEXT: addi r3, r3, .LCPI98_0@toc@l
5000 ; P9BE-NEXT: lxv v2, 0(r3)
5001 ; P9BE-NEXT: blr
5002 ;
5003 ; P9LE-LABEL: spltConst16kull:
5004 ; P9LE: # %bb.0: # %entry
5005 ; P9LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha
5006 ; P9LE-NEXT: addi r3, r3, .LCPI98_0@toc@l
5007 ; P9LE-NEXT: lxv v2, 0(r3)
5008 ; P9LE-NEXT: blr
5009 ;
5010 ; P8BE-LABEL: spltConst16kull:
5011 ; P8BE: # %bb.0: # %entry
5012 ; P8BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha
5013 ; P8BE-NEXT: addi r3, r3, .LCPI98_0@toc@l
5014 ; P8BE-NEXT: lxvd2x v2, 0, r3
5015 ; P8BE-NEXT: blr
5016 ;
5017 ; P8LE-LABEL: spltConst16kull:
5018 ; P8LE: # %bb.0: # %entry
5019 ; P8LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha
5020 ; P8LE-NEXT: addi r3, r3, .LCPI98_0@toc@l
5021 ; P8LE-NEXT: lxvd2x v2, 0, r3
5022 ; P8LE-NEXT: blr
5023 entry:
5024 ret <2 x i64> <i64 32767, i64 32767>
5025 }
5027 define <2 x i64> @spltConst32kull() {
5028 ; P9BE-LABEL: spltConst32kull:
5029 ; P9BE: # %bb.0: # %entry
5030 ; P9BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha
5031 ; P9BE-NEXT: addi r3, r3, .LCPI99_0@toc@l
5032 ; P9BE-NEXT: lxv v2, 0(r3)
5033 ; P9BE-NEXT: blr
5034 ;
5035 ; P9LE-LABEL: spltConst32kull:
5036 ; P9LE: # %bb.0: # %entry
5037 ; P9LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha
5038 ; P9LE-NEXT: addi r3, r3, .LCPI99_0@toc@l
5039 ; P9LE-NEXT: lxv v2, 0(r3)
5040 ; P9LE-NEXT: blr
5041 ;
5042 ; P8BE-LABEL: spltConst32kull:
5043 ; P8BE: # %bb.0: # %entry
5044 ; P8BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha
5045 ; P8BE-NEXT: addi r3, r3, .LCPI99_0@toc@l
5046 ; P8BE-NEXT: lxvd2x v2, 0, r3
5047 ; P8BE-NEXT: blr
5048 ;
5049 ; P8LE-LABEL: spltConst32kull:
5050 ; P8LE: # %bb.0: # %entry
5051 ; P8LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha
5052 ; P8LE-NEXT: addi r3, r3, .LCPI99_0@toc@l
5053 ; P8LE-NEXT: lxvd2x v2, 0, r3
5054 ; P8LE-NEXT: blr
5055 entry:
5056 ret <2 x i64> <i64 65535, i64 65535>
5057 }
5059 define <2 x i64> @fromRegsull(i64 %a, i64 %b) {
5060 ; P9BE-LABEL: fromRegsull:
5061 ; P9BE: # %bb.0: # %entry
5062 ; P9BE-NEXT: mtvsrdd v2, r3, r4
5063 ; P9BE-NEXT: blr
5064 ;
5065 ; P9LE-LABEL: fromRegsull:
5066 ; P9LE: # %bb.0: # %entry
5067 ; P9LE-NEXT: mtvsrdd v2, r4, r3
5068 ; P9LE-NEXT: blr
5069 ;
5070 ; P8BE-LABEL: fromRegsull:
5071 ; P8BE: # %bb.0: # %entry
5072 ; P8BE-NEXT: mtfprd f0, r4
5073 ; P8BE-NEXT: mtfprd f1, r3
5074 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
5075 ; P8BE-NEXT: blr
5076 ;
5077 ; P8LE-LABEL: fromRegsull:
5078 ; P8LE: # %bb.0: # %entry
5079 ; P8LE-NEXT: mtfprd f0, r3
5080 ; P8LE-NEXT: mtfprd f1, r4
5081 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
5082 ; P8LE-NEXT: blr
5083 entry:
5084 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
5085 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1
5086 ret <2 x i64> %vecinit1
5087 }
5089 define <2 x i64> @fromDiffConstsull() {
5090 ; P9BE-LABEL: fromDiffConstsull:
5091 ; P9BE: # %bb.0: # %entry
5092 ; P9BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha
5093 ; P9BE-NEXT: addi r3, r3, .LCPI101_0@toc@l
5094 ; P9BE-NEXT: lxv v2, 0(r3)
5095 ; P9BE-NEXT: blr
5096 ;
5097 ; P9LE-LABEL: fromDiffConstsull:
5098 ; P9LE: # %bb.0: # %entry
5099 ; P9LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha
5100 ; P9LE-NEXT: addi r3, r3, .LCPI101_0@toc@l
5101 ; P9LE-NEXT: lxv v2, 0(r3)
5102 ; P9LE-NEXT: blr
5103 ;
5104 ; P8BE-LABEL: fromDiffConstsull:
5105 ; P8BE: # %bb.0: # %entry
5106 ; P8BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha
5107 ; P8BE-NEXT: addi r3, r3, .LCPI101_0@toc@l
5108 ; P8BE-NEXT: lxvd2x v2, 0, r3
5109 ; P8BE-NEXT: blr
5110 ;
5111 ; P8LE-LABEL: fromDiffConstsull:
5112 ; P8LE: # %bb.0: # %entry
5113 ; P8LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha
5114 ; P8LE-NEXT: addi r3, r3, .LCPI101_0@toc@l
5115 ; P8LE-NEXT: lxvd2x vs0, 0, r3
5116 ; P8LE-NEXT: xxswapd v2, vs0
5117 ; P8LE-NEXT: blr
5118 entry:
5119 ret <2 x i64> <i64 242, i64 -113>
5120 }
5122 define <2 x i64> @fromDiffMemConsAull(ptr nocapture readonly %arr) {
5123 ; P9BE-LABEL: fromDiffMemConsAull:
5124 ; P9BE: # %bb.0: # %entry
5125 ; P9BE-NEXT: lxv v2, 0(r3)
5126 ; P9BE-NEXT: blr
5127 ;
5128 ; P9LE-LABEL: fromDiffMemConsAull:
5129 ; P9LE: # %bb.0: # %entry
5130 ; P9LE-NEXT: lxv v2, 0(r3)
5131 ; P9LE-NEXT: blr
5132 ;
5133 ; P8BE-LABEL: fromDiffMemConsAull:
5134 ; P8BE: # %bb.0: # %entry
5135 ; P8BE-NEXT: lxvd2x v2, 0, r3
5136 ; P8BE-NEXT: blr
5137 ;
5138 ; P8LE-LABEL: fromDiffMemConsAull:
5139 ; P8LE: # %bb.0: # %entry
5140 ; P8LE-NEXT: lxvd2x vs0, 0, r3
5141 ; P8LE-NEXT: xxswapd v2, vs0
5142 ; P8LE-NEXT: blr
5143 entry:
5144 %0 = load i64, ptr %arr, align 8
5145 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
5146 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 1
5147 %1 = load i64, ptr %arrayidx1, align 8
5148 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
5149 ret <2 x i64> %vecinit2
5150 }
5152 define <2 x i64> @fromDiffMemConsDull(ptr nocapture readonly %arr) {
5153 ; P9BE-LABEL: fromDiffMemConsDull:
5154 ; P9BE: # %bb.0: # %entry
5155 ; P9BE-NEXT: lxv v2, 16(r3)
5156 ; P9BE-NEXT: xxswapd v2, v2
5157 ; P9BE-NEXT: blr
5158 ;
5159 ; P9LE-LABEL: fromDiffMemConsDull:
5160 ; P9LE: # %bb.0: # %entry
5161 ; P9LE-NEXT: addi r3, r3, 16
5162 ; P9LE-NEXT: lxvd2x v2, 0, r3
5163 ; P9LE-NEXT: blr
5164 ;
5165 ; P8BE-LABEL: fromDiffMemConsDull:
5166 ; P8BE: # %bb.0: # %entry
5167 ; P8BE-NEXT: addi r3, r3, 16
5168 ; P8BE-NEXT: lxvd2x v2, 0, r3
5169 ; P8BE-NEXT: xxswapd v2, v2
5170 ; P8BE-NEXT: blr
5171 ;
5172 ; P8LE-LABEL: fromDiffMemConsDull:
5173 ; P8LE: # %bb.0: # %entry
5174 ; P8LE-NEXT: addi r3, r3, 16
5175 ; P8LE-NEXT: lxvd2x v2, 0, r3
5176 ; P8LE-NEXT: blr
5177 entry:
5178 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 3
5179 %0 = load i64, ptr %arrayidx, align 8
5180 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
5181 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 2
5182 %1 = load i64, ptr %arrayidx1, align 8
5183 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
5184 ret <2 x i64> %vecinit2
5185 }
5187 define <2 x i64> @fromDiffMemVarAull(ptr nocapture readonly %arr, i32 signext %elem) {
5188 ; P9BE-LABEL: fromDiffMemVarAull:
5189 ; P9BE: # %bb.0: # %entry
5190 ; P9BE-NEXT: sldi r4, r4, 3
5191 ; P9BE-NEXT: lxvx v2, r3, r4
5192 ; P9BE-NEXT: blr
5193 ;
5194 ; P9LE-LABEL: fromDiffMemVarAull:
5195 ; P9LE: # %bb.0: # %entry
5196 ; P9LE-NEXT: sldi r4, r4, 3
5197 ; P9LE-NEXT: lxvx v2, r3, r4
5198 ; P9LE-NEXT: blr
5199 ;
5200 ; P8BE-LABEL: fromDiffMemVarAull:
5201 ; P8BE: # %bb.0: # %entry
5202 ; P8BE-NEXT: sldi r4, r4, 3
5203 ; P8BE-NEXT: lxvd2x v2, r3, r4
5204 ; P8BE-NEXT: blr
5205 ;
5206 ; P8LE-LABEL: fromDiffMemVarAull:
5207 ; P8LE: # %bb.0: # %entry
5208 ; P8LE-NEXT: sldi r4, r4, 3
5209 ; P8LE-NEXT: lxvd2x vs0, r3, r4
5210 ; P8LE-NEXT: xxswapd v2, vs0
5211 ; P8LE-NEXT: blr
5212 entry:
5213 %idxprom = sext i32 %elem to i64
5214 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom
5215 %0 = load i64, ptr %arrayidx, align 8
5216 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
5217 %add = add nsw i32 %elem, 1
5218 %idxprom1 = sext i32 %add to i64
5219 %arrayidx2 = getelementptr inbounds i64, ptr %arr, i64 %idxprom1
5220 %1 = load i64, ptr %arrayidx2, align 8
5221 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
5222 ret <2 x i64> %vecinit3
5223 }
5225 define <2 x i64> @fromDiffMemVarDull(ptr nocapture readonly %arr, i32 signext %elem) {
5226 ; P9BE-LABEL: fromDiffMemVarDull:
5227 ; P9BE: # %bb.0: # %entry
5228 ; P9BE-NEXT: sldi r4, r4, 3
5229 ; P9BE-NEXT: add r3, r3, r4
5230 ; P9BE-NEXT: li r4, -8
5231 ; P9BE-NEXT: lxvx v2, r3, r4
5232 ; P9BE-NEXT: xxswapd v2, v2
5233 ; P9BE-NEXT: blr
5234 ;
5235 ; P9LE-LABEL: fromDiffMemVarDull:
5236 ; P9LE: # %bb.0: # %entry
5237 ; P9LE-NEXT: sldi r4, r4, 3
5238 ; P9LE-NEXT: add r3, r3, r4
5239 ; P9LE-NEXT: addi r3, r3, -8
5240 ; P9LE-NEXT: lxvd2x v2, 0, r3
5241 ; P9LE-NEXT: blr
5242 ;
5243 ; P8BE-LABEL: fromDiffMemVarDull:
5244 ; P8BE: # %bb.0: # %entry
5245 ; P8BE-NEXT: sldi r4, r4, 3
5246 ; P8BE-NEXT: add r3, r3, r4
5247 ; P8BE-NEXT: addi r3, r3, -8
5248 ; P8BE-NEXT: lxvd2x v2, 0, r3
5249 ; P8BE-NEXT: xxswapd v2, v2
5250 ; P8BE-NEXT: blr
5251 ;
5252 ; P8LE-LABEL: fromDiffMemVarDull:
5253 ; P8LE: # %bb.0: # %entry
5254 ; P8LE-NEXT: sldi r4, r4, 3
5255 ; P8LE-NEXT: add r3, r3, r4
5256 ; P8LE-NEXT: addi r3, r3, -8
5257 ; P8LE-NEXT: lxvd2x v2, 0, r3
5258 ; P8LE-NEXT: blr
5259 entry:
5260 %idxprom = sext i32 %elem to i64
5261 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom
5262 %0 = load i64, ptr %arrayidx, align 8
5263 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
5264 %sub = add nsw i32 %elem, -1
5265 %idxprom1 = sext i32 %sub to i64
5266 %arrayidx2 = getelementptr inbounds i64, ptr %arr, i64 %idxprom1
5267 %1 = load i64, ptr %arrayidx2, align 8
5268 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
5269 ret <2 x i64> %vecinit3
5270 }
5272 define <2 x i64> @fromRandMemConsull(ptr nocapture readonly %arr) {
5273 ; P9BE-LABEL: fromRandMemConsull:
5274 ; P9BE: # %bb.0: # %entry
5275 ; P9BE-NEXT: ld r4, 32(r3)
5276 ; P9BE-NEXT: ld r3, 144(r3)
5277 ; P9BE-NEXT: mtvsrdd v2, r4, r3
5278 ; P9BE-NEXT: blr
5279 ;
5280 ; P9LE-LABEL: fromRandMemConsull:
5281 ; P9LE: # %bb.0: # %entry
5282 ; P9LE-NEXT: ld r4, 32(r3)
5283 ; P9LE-NEXT: ld r3, 144(r3)
5284 ; P9LE-NEXT: mtvsrdd v2, r3, r4
5285 ; P9LE-NEXT: blr
5286 ;
5287 ; P8BE-LABEL: fromRandMemConsull:
5288 ; P8BE: # %bb.0: # %entry
5289 ; P8BE-NEXT: ld r4, 144(r3)
5290 ; P8BE-NEXT: ld r3, 32(r3)
5291 ; P8BE-NEXT: mtfprd f0, r4
5292 ; P8BE-NEXT: mtfprd f1, r3
5293 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
5294 ; P8BE-NEXT: blr
5295 ;
5296 ; P8LE-LABEL: fromRandMemConsull:
5297 ; P8LE: # %bb.0: # %entry
5298 ; P8LE-NEXT: ld r4, 32(r3)
5299 ; P8LE-NEXT: ld r3, 144(r3)
5300 ; P8LE-NEXT: mtfprd f0, r4
5301 ; P8LE-NEXT: mtfprd f1, r3
5302 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
5303 ; P8LE-NEXT: blr
5304 entry:
5305 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 4
5306 %0 = load i64, ptr %arrayidx, align 8
5307 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
5308 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 18
5309 %1 = load i64, ptr %arrayidx1, align 8
5310 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
5311 ret <2 x i64> %vecinit2
5312 }
5314 define <2 x i64> @fromRandMemVarull(ptr nocapture readonly %arr, i32 signext %elem) {
5315 ; P9BE-LABEL: fromRandMemVarull:
5316 ; P9BE: # %bb.0: # %entry
5317 ; P9BE-NEXT: sldi r4, r4, 3
5318 ; P9BE-NEXT: add r3, r3, r4
5319 ; P9BE-NEXT: ld r4, 32(r3)
5320 ; P9BE-NEXT: ld r3, 8(r3)
5321 ; P9BE-NEXT: mtvsrdd v2, r4, r3
5322 ; P9BE-NEXT: blr
5323 ;
5324 ; P9LE-LABEL: fromRandMemVarull:
5325 ; P9LE: # %bb.0: # %entry
5326 ; P9LE-NEXT: sldi r4, r4, 3
5327 ; P9LE-NEXT: add r3, r3, r4
5328 ; P9LE-NEXT: ld r4, 32(r3)
5329 ; P9LE-NEXT: ld r3, 8(r3)
5330 ; P9LE-NEXT: mtvsrdd v2, r3, r4
5331 ; P9LE-NEXT: blr
5332 ;
5333 ; P8BE-LABEL: fromRandMemVarull:
5334 ; P8BE: # %bb.0: # %entry
5335 ; P8BE-NEXT: sldi r4, r4, 3
5336 ; P8BE-NEXT: add r3, r3, r4
5337 ; P8BE-NEXT: ld r4, 8(r3)
5338 ; P8BE-NEXT: ld r3, 32(r3)
5339 ; P8BE-NEXT: mtfprd f0, r4
5340 ; P8BE-NEXT: mtfprd f1, r3
5341 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
5342 ; P8BE-NEXT: blr
5343 ;
5344 ; P8LE-LABEL: fromRandMemVarull:
5345 ; P8LE: # %bb.0: # %entry
5346 ; P8LE-NEXT: sldi r4, r4, 3
5347 ; P8LE-NEXT: add r3, r3, r4
5348 ; P8LE-NEXT: ld r4, 32(r3)
5349 ; P8LE-NEXT: ld r3, 8(r3)
5350 ; P8LE-NEXT: mtfprd f0, r4
5351 ; P8LE-NEXT: mtfprd f1, r3
5352 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
5353 ; P8LE-NEXT: blr
5354 entry:
5355 %add = add nsw i32 %elem, 4
5356 %idxprom = sext i32 %add to i64
5357 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom
5358 %0 = load i64, ptr %arrayidx, align 8
5359 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
5360 %add1 = add nsw i32 %elem, 1
5361 %idxprom2 = sext i32 %add1 to i64
5362 %arrayidx3 = getelementptr inbounds i64, ptr %arr, i64 %idxprom2
5363 %1 = load i64, ptr %arrayidx3, align 8
5364 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
5365 ret <2 x i64> %vecinit4
5366 }
5368 define <2 x i64> @spltRegValull(i64 %val) {
5369 ; P9BE-LABEL: spltRegValull:
5370 ; P9BE: # %bb.0: # %entry
5371 ; P9BE-NEXT: mtvsrdd v2, r3, r3
5372 ; P9BE-NEXT: blr
5373 ;
5374 ; P9LE-LABEL: spltRegValull:
5375 ; P9LE: # %bb.0: # %entry
5376 ; P9LE-NEXT: mtvsrdd v2, r3, r3
5377 ; P9LE-NEXT: blr
5378 ;
5379 ; P8BE-LABEL: spltRegValull:
5380 ; P8BE: # %bb.0: # %entry
5381 ; P8BE-NEXT: mtfprd f0, r3
5382 ; P8BE-NEXT: xxspltd v2, vs0, 0
5383 ; P8BE-NEXT: blr
5384 ;
5385 ; P8LE-LABEL: spltRegValull:
5386 ; P8LE: # %bb.0: # %entry
5387 ; P8LE-NEXT: mtfprd f0, r3
5388 ; P8LE-NEXT: xxspltd v2, vs0, 0
5389 ; P8LE-NEXT: blr
5390 entry:
5391 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0
5392 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
5393 ret <2 x i64> %splat.splat
5394 }
5396 define <2 x i64> @spltMemValull(ptr nocapture readonly %ptr) {
5397 ; P9BE-LABEL: spltMemValull:
5398 ; P9BE: # %bb.0: # %entry
5399 ; P9BE-NEXT: lxvdsx v2, 0, r3
5400 ; P9BE-NEXT: blr
5401 ;
5402 ; P9LE-LABEL: spltMemValull:
5403 ; P9LE: # %bb.0: # %entry
5404 ; P9LE-NEXT: lxvdsx v2, 0, r3
5405 ; P9LE-NEXT: blr
5406 ;
5407 ; P8BE-LABEL: spltMemValull:
5408 ; P8BE: # %bb.0: # %entry
5409 ; P8BE-NEXT: lxvdsx v2, 0, r3
5410 ; P8BE-NEXT: blr
5411 ;
5412 ; P8LE-LABEL: spltMemValull:
5413 ; P8LE: # %bb.0: # %entry
5414 ; P8LE-NEXT: lxvdsx v2, 0, r3
5415 ; P8LE-NEXT: blr
5416 entry:
5417 %0 = load i64, ptr %ptr, align 8
5418 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0
5419 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
5420 ret <2 x i64> %splat.splat
5421 }
5423 define <2 x i64> @spltCnstConvftoull() {
5424 ; P9BE-LABEL: spltCnstConvftoull:
5425 ; P9BE: # %bb.0: # %entry
5426 ; P9BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha
5427 ; P9BE-NEXT: addi r3, r3, .LCPI110_0@toc@l
5428 ; P9BE-NEXT: lxv v2, 0(r3)
5429 ; P9BE-NEXT: blr
5430 ;
5431 ; P9LE-LABEL: spltCnstConvftoull:
5432 ; P9LE: # %bb.0: # %entry
5433 ; P9LE-NEXT: addis r3, r2, .LCPI110_0@toc@ha
5434 ; P9LE-NEXT: addi r3, r3, .LCPI110_0@toc@l
5435 ; P9LE-NEXT: lxv v2, 0(r3)
5436 ; P9LE-NEXT: blr
5437 ;
5438 ; P8BE-LABEL: spltCnstConvftoull:
5439 ; P8BE: # %bb.0: # %entry
5440 ; P8BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha
5441 ; P8BE-NEXT: addi r3, r3, .LCPI110_0@toc@l
5442 ; P8BE-NEXT: lxvd2x v2, 0, r3
5443 ; P8BE-NEXT: blr
5444 ;
5445 ; P8LE-LABEL: spltCnstConvftoull:
5446 ; P8LE: # %bb.0: # %entry
5447 ; P8LE-NEXT: addis r3, r2, .LCPI110_0@toc@ha
5448 ; P8LE-NEXT: addi r3, r3, .LCPI110_0@toc@l
5449 ; P8LE-NEXT: lxvd2x v2, 0, r3
5450 ; P8LE-NEXT: blr
5451 entry:
5452 ret <2 x i64> <i64 4, i64 4>
5453 }
5455 define <2 x i64> @fromRegsConvftoull(float %a, float %b) {
5456 ; P9BE-LABEL: fromRegsConvftoull:
5457 ; P9BE: # %bb.0: # %entry
5458 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
5459 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
5460 ; P9BE-NEXT: xxmrghd vs0, vs1, vs2
5461 ; P9BE-NEXT: xvcvdpuxds v2, vs0
5462 ; P9BE-NEXT: blr
5463 ;
5464 ; P9LE-LABEL: fromRegsConvftoull:
5465 ; P9LE: # %bb.0: # %entry
5466 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
5467 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
5468 ; P9LE-NEXT: xxmrghd vs0, vs2, vs1
5469 ; P9LE-NEXT: xvcvdpuxds v2, vs0
5470 ; P9LE-NEXT: blr
5471 ;
5472 ; P8BE-LABEL: fromRegsConvftoull:
5473 ; P8BE: # %bb.0: # %entry
5474 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
5475 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
5476 ; P8BE-NEXT: xxmrghd vs0, vs1, vs2
5477 ; P8BE-NEXT: xvcvdpuxds v2, vs0
5478 ; P8BE-NEXT: blr
5479 ;
5480 ; P8LE-LABEL: fromRegsConvftoull:
5481 ; P8LE: # %bb.0: # %entry
5482 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
5483 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
5484 ; P8LE-NEXT: xxmrghd vs0, vs2, vs1
5485 ; P8LE-NEXT: xvcvdpuxds v2, vs0
5486 ; P8LE-NEXT: blr
5487 entry:
5488 %conv = fptoui float %a to i64
5489 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
5490 %conv1 = fptoui float %b to i64
5491 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1
5492 ret <2 x i64> %vecinit2
5493 }
5495 define <2 x i64> @fromDiffConstsConvftoull() {
5496 ; P9BE-LABEL: fromDiffConstsConvftoull:
5497 ; P9BE: # %bb.0: # %entry
5498 ; P9BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha
5499 ; P9BE-NEXT: addi r3, r3, .LCPI112_0@toc@l
5500 ; P9BE-NEXT: lxv v2, 0(r3)
5501 ; P9BE-NEXT: blr
5502 ;
5503 ; P9LE-LABEL: fromDiffConstsConvftoull:
5504 ; P9LE: # %bb.0: # %entry
5505 ; P9LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha
5506 ; P9LE-NEXT: addi r3, r3, .LCPI112_0@toc@l
5507 ; P9LE-NEXT: lxv v2, 0(r3)
5508 ; P9LE-NEXT: blr
5509 ;
5510 ; P8BE-LABEL: fromDiffConstsConvftoull:
5511 ; P8BE: # %bb.0: # %entry
5512 ; P8BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha
5513 ; P8BE-NEXT: addi r3, r3, .LCPI112_0@toc@l
5514 ; P8BE-NEXT: lxvd2x v2, 0, r3
5515 ; P8BE-NEXT: blr
5516 ;
5517 ; P8LE-LABEL: fromDiffConstsConvftoull:
5518 ; P8LE: # %bb.0: # %entry
5519 ; P8LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha
5520 ; P8LE-NEXT: addi r3, r3, .LCPI112_0@toc@l
5521 ; P8LE-NEXT: lxvd2x vs0, 0, r3
5522 ; P8LE-NEXT: xxswapd v2, vs0
5523 ; P8LE-NEXT: blr
5524 entry:
5525 ret <2 x i64> <i64 24, i64 234>
5526 }
5528 define <2 x i64> @fromDiffMemConsAConvftoull(ptr nocapture readonly %ptr) {
5529 ; P9BE-LABEL: fromDiffMemConsAConvftoull:
5530 ; P9BE: # %bb.0: # %entry
5531 ; P9BE-NEXT: lfs f0, 0(r3)
5532 ; P9BE-NEXT: lfs f1, 4(r3)
5533 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
5534 ; P9BE-NEXT: xvcvdpuxds v2, vs0
5535 ; P9BE-NEXT: blr
5536 ;
5537 ; P9LE-LABEL: fromDiffMemConsAConvftoull:
5538 ; P9LE: # %bb.0: # %entry
5539 ; P9LE-NEXT: lfs f0, 0(r3)
5540 ; P9LE-NEXT: lfs f1, 4(r3)
5541 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
5542 ; P9LE-NEXT: xvcvdpuxds v2, vs0
5543 ; P9LE-NEXT: blr
5544 ;
5545 ; P8BE-LABEL: fromDiffMemConsAConvftoull:
5546 ; P8BE: # %bb.0: # %entry
5547 ; P8BE-NEXT: lfs f0, 0(r3)
5548 ; P8BE-NEXT: lfs f1, 4(r3)
5549 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
5550 ; P8BE-NEXT: xvcvdpuxds v2, vs0
5551 ; P8BE-NEXT: blr
5552 ;
5553 ; P8LE-LABEL: fromDiffMemConsAConvftoull:
5554 ; P8LE: # %bb.0: # %entry
5555 ; P8LE-NEXT: lfs f0, 0(r3)
5556 ; P8LE-NEXT: lfs f1, 4(r3)
5557 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
5558 ; P8LE-NEXT: xvcvdpuxds v2, vs0
5559 ; P8LE-NEXT: blr
5560 entry:
5561 %0 = load float, ptr %ptr, align 4
5562 %conv = fptoui float %0 to i64
5563 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
5564 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 1
5565 %1 = load float, ptr %arrayidx1, align 4
5566 %conv2 = fptoui float %1 to i64
5567 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
5568 ret <2 x i64> %vecinit3
5569 }
5571 define <2 x i64> @fromDiffMemConsDConvftoull(ptr nocapture readonly %ptr) {
5572 ; P9BE-LABEL: fromDiffMemConsDConvftoull:
5573 ; P9BE: # %bb.0: # %entry
5574 ; P9BE-NEXT: lfs f0, 12(r3)
5575 ; P9BE-NEXT: lfs f1, 8(r3)
5576 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
5577 ; P9BE-NEXT: xvcvdpuxds v2, vs0
5578 ; P9BE-NEXT: blr
5579 ;
5580 ; P9LE-LABEL: fromDiffMemConsDConvftoull:
5581 ; P9LE: # %bb.0: # %entry
5582 ; P9LE-NEXT: lfs f0, 12(r3)
5583 ; P9LE-NEXT: lfs f1, 8(r3)
5584 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
5585 ; P9LE-NEXT: xvcvdpuxds v2, vs0
5586 ; P9LE-NEXT: blr
5587 ;
5588 ; P8BE-LABEL: fromDiffMemConsDConvftoull:
5589 ; P8BE: # %bb.0: # %entry
5590 ; P8BE-NEXT: lfs f0, 12(r3)
5591 ; P8BE-NEXT: lfs f1, 8(r3)
5592 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
5593 ; P8BE-NEXT: xvcvdpuxds v2, vs0
5594 ; P8BE-NEXT: blr
5595 ;
5596 ; P8LE-LABEL: fromDiffMemConsDConvftoull:
5597 ; P8LE: # %bb.0: # %entry
5598 ; P8LE-NEXT: lfs f0, 12(r3)
5599 ; P8LE-NEXT: lfs f1, 8(r3)
5600 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
5601 ; P8LE-NEXT: xvcvdpuxds v2, vs0
5602 ; P8LE-NEXT: blr
5603 entry:
5604 %arrayidx = getelementptr inbounds float, ptr %ptr, i64 3
5605 %0 = load float, ptr %arrayidx, align 4
5606 %conv = fptoui float %0 to i64
5607 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
5608 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 2
5609 %1 = load float, ptr %arrayidx1, align 4
5610 %conv2 = fptoui float %1 to i64
5611 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
5612 ret <2 x i64> %vecinit3
5613 }
5615 define <2 x i64> @fromDiffMemVarAConvftoull(ptr nocapture readonly %arr, i32 signext %elem) {
5616 ; P9BE-LABEL: fromDiffMemVarAConvftoull:
5617 ; P9BE: # %bb.0: # %entry
5618 ; P9BE-NEXT: sldi r4, r4, 2
5619 ; P9BE-NEXT: lfsux f0, r3, r4
5620 ; P9BE-NEXT: lfs f1, 4(r3)
5621 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
5622 ; P9BE-NEXT: xvcvdpuxds v2, vs0
5623 ; P9BE-NEXT: blr
5624 ;
5625 ; P9LE-LABEL: fromDiffMemVarAConvftoull:
5626 ; P9LE: # %bb.0: # %entry
5627 ; P9LE-NEXT: sldi r4, r4, 2
5628 ; P9LE-NEXT: lfsux f0, r3, r4
5629 ; P9LE-NEXT: lfs f1, 4(r3)
5630 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
5631 ; P9LE-NEXT: xvcvdpuxds v2, vs0
5632 ; P9LE-NEXT: blr
5633 ;
5634 ; P8BE-LABEL: fromDiffMemVarAConvftoull:
5635 ; P8BE: # %bb.0: # %entry
5636 ; P8BE-NEXT: sldi r4, r4, 2
5637 ; P8BE-NEXT: lfsux f0, r3, r4
5638 ; P8BE-NEXT: lfs f1, 4(r3)
5639 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
5640 ; P8BE-NEXT: xvcvdpuxds v2, vs0
5641 ; P8BE-NEXT: blr
5642 ;
5643 ; P8LE-LABEL: fromDiffMemVarAConvftoull:
5644 ; P8LE: # %bb.0: # %entry
5645 ; P8LE-NEXT: sldi r4, r4, 2
5646 ; P8LE-NEXT: lfsux f0, r3, r4
5647 ; P8LE-NEXT: lfs f1, 4(r3)
5648 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
5649 ; P8LE-NEXT: xvcvdpuxds v2, vs0
5650 ; P8LE-NEXT: blr
5651 entry:
5652 %idxprom = sext i32 %elem to i64
5653 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom
5654 %0 = load float, ptr %arrayidx, align 4
5655 %conv = fptoui float %0 to i64
5656 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
5657 %add = add nsw i32 %elem, 1
5658 %idxprom1 = sext i32 %add to i64
5659 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1
5660 %1 = load float, ptr %arrayidx2, align 4
5661 %conv3 = fptoui float %1 to i64
5662 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
5663 ret <2 x i64> %vecinit4
5664 }
5666 define <2 x i64> @fromDiffMemVarDConvftoull(ptr nocapture readonly %arr, i32 signext %elem) {
5667 ; P9BE-LABEL: fromDiffMemVarDConvftoull:
5668 ; P9BE: # %bb.0: # %entry
5669 ; P9BE-NEXT: sldi r4, r4, 2
5670 ; P9BE-NEXT: lfsux f0, r3, r4
5671 ; P9BE-NEXT: lfs f1, -4(r3)
5672 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
5673 ; P9BE-NEXT: xvcvdpuxds v2, vs0
5674 ; P9BE-NEXT: blr
5675 ;
5676 ; P9LE-LABEL: fromDiffMemVarDConvftoull:
5677 ; P9LE: # %bb.0: # %entry
5678 ; P9LE-NEXT: sldi r4, r4, 2
5679 ; P9LE-NEXT: lfsux f0, r3, r4
5680 ; P9LE-NEXT: lfs f1, -4(r3)
5681 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
5682 ; P9LE-NEXT: xvcvdpuxds v2, vs0
5683 ; P9LE-NEXT: blr
5684 ;
5685 ; P8BE-LABEL: fromDiffMemVarDConvftoull:
5686 ; P8BE: # %bb.0: # %entry
5687 ; P8BE-NEXT: sldi r4, r4, 2
5688 ; P8BE-NEXT: lfsux f0, r3, r4
5689 ; P8BE-NEXT: lfs f1, -4(r3)
5690 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
5691 ; P8BE-NEXT: xvcvdpuxds v2, vs0
5692 ; P8BE-NEXT: blr
5693 ;
5694 ; P8LE-LABEL: fromDiffMemVarDConvftoull:
5695 ; P8LE: # %bb.0: # %entry
5696 ; P8LE-NEXT: sldi r4, r4, 2
5697 ; P8LE-NEXT: lfsux f0, r3, r4
5698 ; P8LE-NEXT: lfs f1, -4(r3)
5699 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
5700 ; P8LE-NEXT: xvcvdpuxds v2, vs0
5701 ; P8LE-NEXT: blr
5702 entry:
5703 %idxprom = sext i32 %elem to i64
5704 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom
5705 %0 = load float, ptr %arrayidx, align 4
5706 %conv = fptoui float %0 to i64
5707 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
5708 %sub = add nsw i32 %elem, -1
5709 %idxprom1 = sext i32 %sub to i64
5710 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1
5711 %1 = load float, ptr %arrayidx2, align 4
5712 %conv3 = fptoui float %1 to i64
5713 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
5714 ret <2 x i64> %vecinit4
5715 }
5717 define <2 x i64> @spltRegValConvftoull(float %val) {
5718 ; P9BE-LABEL: spltRegValConvftoull:
5719 ; P9BE: # %bb.0: # %entry
5720 ; P9BE-NEXT: xscvdpuxds f0, f1
5721 ; P9BE-NEXT: xxspltd v2, f0, 0
5722 ; P9BE-NEXT: blr
5723 ;
5724 ; P9LE-LABEL: spltRegValConvftoull:
5725 ; P9LE: # %bb.0: # %entry
5726 ; P9LE-NEXT: xscvdpuxds f0, f1
5727 ; P9LE-NEXT: xxspltd v2, f0, 0
5728 ; P9LE-NEXT: blr
5729 ;
5730 ; P8BE-LABEL: spltRegValConvftoull:
5731 ; P8BE: # %bb.0: # %entry
5732 ; P8BE-NEXT: xscvdpuxds f0, f1
5733 ; P8BE-NEXT: xxspltd v2, f0, 0
5734 ; P8BE-NEXT: blr
5735 ;
5736 ; P8LE-LABEL: spltRegValConvftoull:
5737 ; P8LE: # %bb.0: # %entry
5738 ; P8LE-NEXT: xscvdpuxds f0, f1
5739 ; P8LE-NEXT: xxspltd v2, f0, 0
5740 ; P8LE-NEXT: blr
5741 entry:
5742 %conv = fptoui float %val to i64
5743 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
5744 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
5745 ret <2 x i64> %splat.splat
5746 }
5748 define <2 x i64> @spltMemValConvftoull(ptr nocapture readonly %ptr) {
5749 ; P9BE-LABEL: spltMemValConvftoull:
5750 ; P9BE: # %bb.0: # %entry
5751 ; P9BE-NEXT: lfs f0, 0(r3)
5752 ; P9BE-NEXT: xscvdpuxds f0, f0
5753 ; P9BE-NEXT: xxspltd v2, f0, 0
5754 ; P9BE-NEXT: blr
5755 ;
5756 ; P9LE-LABEL: spltMemValConvftoull:
5757 ; P9LE: # %bb.0: # %entry
5758 ; P9LE-NEXT: lfs f0, 0(r3)
5759 ; P9LE-NEXT: xscvdpuxds f0, f0
5760 ; P9LE-NEXT: xxspltd v2, vs0, 0
5761 ; P9LE-NEXT: blr
5762 ;
5763 ; P8BE-LABEL: spltMemValConvftoull:
5764 ; P8BE: # %bb.0: # %entry
5765 ; P8BE-NEXT: lfsx f0, 0, r3
5766 ; P8BE-NEXT: xscvdpuxds f0, f0
5767 ; P8BE-NEXT: xxspltd v2, f0, 0
5768 ; P8BE-NEXT: blr
5769 ;
5770 ; P8LE-LABEL: spltMemValConvftoull:
5771 ; P8LE: # %bb.0: # %entry
5772 ; P8LE-NEXT: lfsx f0, 0, r3
5773 ; P8LE-NEXT: xscvdpuxds f0, f0
5774 ; P8LE-NEXT: xxspltd v2, vs0, 0
5775 ; P8LE-NEXT: blr
5776 entry:
5777 %0 = load float, ptr %ptr, align 4
5778 %conv = fptoui float %0 to i64
5779 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
5780 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
5781 ret <2 x i64> %splat.splat
5782 }
5784 define <2 x i64> @spltCnstConvdtoull() {
5785 ; P9BE-LABEL: spltCnstConvdtoull:
5786 ; P9BE: # %bb.0: # %entry
5787 ; P9BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha
5788 ; P9BE-NEXT: addi r3, r3, .LCPI119_0@toc@l
5789 ; P9BE-NEXT: lxv v2, 0(r3)
5790 ; P9BE-NEXT: blr
5791 ;
5792 ; P9LE-LABEL: spltCnstConvdtoull:
5793 ; P9LE: # %bb.0: # %entry
5794 ; P9LE-NEXT: addis r3, r2, .LCPI119_0@toc@ha
5795 ; P9LE-NEXT: addi r3, r3, .LCPI119_0@toc@l
5796 ; P9LE-NEXT: lxv v2, 0(r3)
5797 ; P9LE-NEXT: blr
5798 ;
5799 ; P8BE-LABEL: spltCnstConvdtoull:
5800 ; P8BE: # %bb.0: # %entry
5801 ; P8BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha
5802 ; P8BE-NEXT: addi r3, r3, .LCPI119_0@toc@l
5803 ; P8BE-NEXT: lxvd2x v2, 0, r3
5804 ; P8BE-NEXT: blr
5805 ;
5806 ; P8LE-LABEL: spltCnstConvdtoull:
5807 ; P8LE: # %bb.0: # %entry
5808 ; P8LE-NEXT: addis r3, r2, .LCPI119_0@toc@ha
5809 ; P8LE-NEXT: addi r3, r3, .LCPI119_0@toc@l
5810 ; P8LE-NEXT: lxvd2x v2, 0, r3
5811 ; P8LE-NEXT: blr
5812 entry:
5813 ret <2 x i64> <i64 4, i64 4>
5814 }
5816 define <2 x i64> @fromRegsConvdtoull(double %a, double %b) {
5817 ; P9BE-LABEL: fromRegsConvdtoull:
5818 ; P9BE: # %bb.0: # %entry
5819 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
5820 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
5821 ; P9BE-NEXT: xxmrghd vs0, vs1, vs2
5822 ; P9BE-NEXT: xvcvdpuxds v2, vs0
5823 ; P9BE-NEXT: blr
5824 ;
5825 ; P9LE-LABEL: fromRegsConvdtoull:
5826 ; P9LE: # %bb.0: # %entry
5827 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
5828 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
5829 ; P9LE-NEXT: xxmrghd vs0, vs2, vs1
5830 ; P9LE-NEXT: xvcvdpuxds v2, vs0
5831 ; P9LE-NEXT: blr
5832 ;
5833 ; P8BE-LABEL: fromRegsConvdtoull:
5834 ; P8BE: # %bb.0: # %entry
5835 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
5836 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
5837 ; P8BE-NEXT: xxmrghd vs0, vs1, vs2
5838 ; P8BE-NEXT: xvcvdpuxds v2, vs0
5839 ; P8BE-NEXT: blr
5840 ;
5841 ; P8LE-LABEL: fromRegsConvdtoull:
5842 ; P8LE: # %bb.0: # %entry
5843 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
5844 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
5845 ; P8LE-NEXT: xxmrghd vs0, vs2, vs1
5846 ; P8LE-NEXT: xvcvdpuxds v2, vs0
5847 ; P8LE-NEXT: blr
5848 entry:
5849 %conv = fptoui double %a to i64
5850 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
5851 %conv1 = fptoui double %b to i64
5852 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1
5853 ret <2 x i64> %vecinit2
5854 }
5856 define <2 x i64> @fromDiffConstsConvdtoull() {
5857 ; P9BE-LABEL: fromDiffConstsConvdtoull:
5858 ; P9BE: # %bb.0: # %entry
5859 ; P9BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha
5860 ; P9BE-NEXT: addi r3, r3, .LCPI121_0@toc@l
5861 ; P9BE-NEXT: lxv v2, 0(r3)
5862 ; P9BE-NEXT: blr
5863 ;
5864 ; P9LE-LABEL: fromDiffConstsConvdtoull:
5865 ; P9LE: # %bb.0: # %entry
5866 ; P9LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha
5867 ; P9LE-NEXT: addi r3, r3, .LCPI121_0@toc@l
5868 ; P9LE-NEXT: lxv v2, 0(r3)
5869 ; P9LE-NEXT: blr
5870 ;
5871 ; P8BE-LABEL: fromDiffConstsConvdtoull:
5872 ; P8BE: # %bb.0: # %entry
5873 ; P8BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha
5874 ; P8BE-NEXT: addi r3, r3, .LCPI121_0@toc@l
5875 ; P8BE-NEXT: lxvd2x v2, 0, r3
5876 ; P8BE-NEXT: blr
5877 ;
5878 ; P8LE-LABEL: fromDiffConstsConvdtoull:
5879 ; P8LE: # %bb.0: # %entry
5880 ; P8LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha
5881 ; P8LE-NEXT: addi r3, r3, .LCPI121_0@toc@l
5882 ; P8LE-NEXT: lxvd2x vs0, 0, r3
5883 ; P8LE-NEXT: xxswapd v2, vs0
5884 ; P8LE-NEXT: blr
5885 entry:
5886 ret <2 x i64> <i64 24, i64 234>
5887 }
5889 define <2 x i64> @fromDiffMemConsAConvdtoull(ptr nocapture readonly %ptr) {
5890 ; P9BE-LABEL: fromDiffMemConsAConvdtoull:
5891 ; P9BE: # %bb.0: # %entry
5892 ; P9BE-NEXT: lxv vs0, 0(r3)
5893 ; P9BE-NEXT: xvcvdpuxds v2, vs0
5894 ; P9BE-NEXT: blr
5895 ;
5896 ; P9LE-LABEL: fromDiffMemConsAConvdtoull:
5897 ; P9LE: # %bb.0: # %entry
5898 ; P9LE-NEXT: lxv vs0, 0(r3)
5899 ; P9LE-NEXT: xvcvdpuxds v2, vs0
5900 ; P9LE-NEXT: blr
5901 ;
5902 ; P8BE-LABEL: fromDiffMemConsAConvdtoull:
5903 ; P8BE: # %bb.0: # %entry
5904 ; P8BE-NEXT: lxvd2x vs0, 0, r3
5905 ; P8BE-NEXT: xvcvdpuxds v2, vs0
5906 ; P8BE-NEXT: blr
5907 ;
5908 ; P8LE-LABEL: fromDiffMemConsAConvdtoull:
5909 ; P8LE: # %bb.0: # %entry
5910 ; P8LE-NEXT: lxvd2x vs0, 0, r3
5911 ; P8LE-NEXT: xxswapd vs0, vs0
5912 ; P8LE-NEXT: xvcvdpuxds v2, vs0
5913 ; P8LE-NEXT: blr
5914 entry:
5915 %0 = load <2 x double>, ptr %ptr, align 8
5916 %1 = fptoui <2 x double> %0 to <2 x i64>
5917 ret <2 x i64> %1
5918 }
5920 define <2 x i64> @fromDiffMemConsDConvdtoull(ptr nocapture readonly %ptr) {
5921 ; P9BE-LABEL: fromDiffMemConsDConvdtoull:
5922 ; P9BE: # %bb.0: # %entry
5923 ; P9BE-NEXT: lxv vs0, 16(r3)
5924 ; P9BE-NEXT: xxswapd vs0, vs0
5925 ; P9BE-NEXT: xvcvdpuxds v2, vs0
5926 ; P9BE-NEXT: blr
5927 ;
5928 ; P9LE-LABEL: fromDiffMemConsDConvdtoull:
5929 ; P9LE: # %bb.0: # %entry
5930 ; P9LE-NEXT: addi r3, r3, 16
5931 ; P9LE-NEXT: lxvd2x vs0, 0, r3
5932 ; P9LE-NEXT: xvcvdpuxds v2, vs0
5933 ; P9LE-NEXT: blr
5934 ;
5935 ; P8BE-LABEL: fromDiffMemConsDConvdtoull:
5936 ; P8BE: # %bb.0: # %entry
5937 ; P8BE-NEXT: addi r3, r3, 16
5938 ; P8BE-NEXT: lxvd2x vs0, 0, r3
5939 ; P8BE-NEXT: xxswapd vs0, vs0
5940 ; P8BE-NEXT: xvcvdpuxds v2, vs0
5941 ; P8BE-NEXT: blr
5942 ;
5943 ; P8LE-LABEL: fromDiffMemConsDConvdtoull:
5944 ; P8LE: # %bb.0: # %entry
5945 ; P8LE-NEXT: addi r3, r3, 16
5946 ; P8LE-NEXT: lxvd2x vs0, 0, r3
5947 ; P8LE-NEXT: xvcvdpuxds v2, vs0
5948 ; P8LE-NEXT: blr
5949 entry:
5950 %arrayidx = getelementptr inbounds double, ptr %ptr, i64 3
5951 %0 = load double, ptr %arrayidx, align 8
5952 %conv = fptoui double %0 to i64
5953 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
5954 %arrayidx1 = getelementptr inbounds double, ptr %ptr, i64 2
5955 %1 = load double, ptr %arrayidx1, align 8
5956 %conv2 = fptoui double %1 to i64
5957 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
5958 ret <2 x i64> %vecinit3
5959 }
5961 define <2 x i64> @fromDiffMemVarAConvdtoull(ptr nocapture readonly %arr, i32 signext %elem) {
5962 ; P9BE-LABEL: fromDiffMemVarAConvdtoull:
5963 ; P9BE: # %bb.0: # %entry
5964 ; P9BE-NEXT: sldi r4, r4, 3
5965 ; P9BE-NEXT: lxvx vs0, r3, r4
5966 ; P9BE-NEXT: xvcvdpuxds v2, vs0
5967 ; P9BE-NEXT: blr
5968 ;
5969 ; P9LE-LABEL: fromDiffMemVarAConvdtoull:
5970 ; P9LE: # %bb.0: # %entry
5971 ; P9LE-NEXT: sldi r4, r4, 3
5972 ; P9LE-NEXT: lxvx vs0, r3, r4
5973 ; P9LE-NEXT: xvcvdpuxds v2, vs0
5974 ; P9LE-NEXT: blr
5975 ;
5976 ; P8BE-LABEL: fromDiffMemVarAConvdtoull:
5977 ; P8BE: # %bb.0: # %entry
5978 ; P8BE-NEXT: sldi r4, r4, 3
5979 ; P8BE-NEXT: lxvd2x vs0, r3, r4
5980 ; P8BE-NEXT: xvcvdpuxds v2, vs0
5981 ; P8BE-NEXT: blr
5982 ;
5983 ; P8LE-LABEL: fromDiffMemVarAConvdtoull:
5984 ; P8LE: # %bb.0: # %entry
5985 ; P8LE-NEXT: sldi r4, r4, 3
5986 ; P8LE-NEXT: lxvd2x vs0, r3, r4
5987 ; P8LE-NEXT: xxswapd vs0, vs0
5988 ; P8LE-NEXT: xvcvdpuxds v2, vs0
5989 ; P8LE-NEXT: blr
5990 entry:
5991 %idxprom = sext i32 %elem to i64
5992 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom
5993 %0 = load double, ptr %arrayidx, align 8
5994 %conv = fptoui double %0 to i64
5995 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
5996 %add = add nsw i32 %elem, 1
5997 %idxprom1 = sext i32 %add to i64
5998 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1
5999 %1 = load double, ptr %arrayidx2, align 8
6000 %conv3 = fptoui double %1 to i64
6001 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
6002 ret <2 x i64> %vecinit4
6003 }
6005 define <2 x i64> @fromDiffMemVarDConvdtoull(ptr nocapture readonly %arr, i32 signext %elem) {
6006 ; P9BE-LABEL: fromDiffMemVarDConvdtoull:
6007 ; P9BE: # %bb.0: # %entry
6008 ; P9BE-NEXT: sldi r4, r4, 3
6009 ; P9BE-NEXT: add r3, r3, r4
6010 ; P9BE-NEXT: li r4, -8
6011 ; P9BE-NEXT: lxvx vs0, r3, r4
6012 ; P9BE-NEXT: xxswapd vs0, vs0
6013 ; P9BE-NEXT: xvcvdpuxds v2, vs0
6014 ; P9BE-NEXT: blr
6015 ;
6016 ; P9LE-LABEL: fromDiffMemVarDConvdtoull:
6017 ; P9LE: # %bb.0: # %entry
6018 ; P9LE-NEXT: sldi r4, r4, 3
6019 ; P9LE-NEXT: add r3, r3, r4
6020 ; P9LE-NEXT: addi r3, r3, -8
6021 ; P9LE-NEXT: lxvd2x vs0, 0, r3
6022 ; P9LE-NEXT: xvcvdpuxds v2, vs0
6023 ; P9LE-NEXT: blr
6024 ;
6025 ; P8BE-LABEL: fromDiffMemVarDConvdtoull:
6026 ; P8BE: # %bb.0: # %entry
6027 ; P8BE-NEXT: sldi r4, r4, 3
6028 ; P8BE-NEXT: add r3, r3, r4
6029 ; P8BE-NEXT: addi r3, r3, -8
6030 ; P8BE-NEXT: lxvd2x vs0, 0, r3
6031 ; P8BE-NEXT: xxswapd vs0, vs0
6032 ; P8BE-NEXT: xvcvdpuxds v2, vs0
6033 ; P8BE-NEXT: blr
6034 ;
6035 ; P8LE-LABEL: fromDiffMemVarDConvdtoull:
6036 ; P8LE: # %bb.0: # %entry
6037 ; P8LE-NEXT: sldi r4, r4, 3
6038 ; P8LE-NEXT: add r3, r3, r4
6039 ; P8LE-NEXT: addi r3, r3, -8
6040 ; P8LE-NEXT: lxvd2x vs0, 0, r3
6041 ; P8LE-NEXT: xvcvdpuxds v2, vs0
6042 ; P8LE-NEXT: blr
6043 entry:
6044 %idxprom = sext i32 %elem to i64
6045 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom
6046 %0 = load double, ptr %arrayidx, align 8
6047 %conv = fptoui double %0 to i64
6048 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
6049 %sub = add nsw i32 %elem, -1
6050 %idxprom1 = sext i32 %sub to i64
6051 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1
6052 %1 = load double, ptr %arrayidx2, align 8
6053 %conv3 = fptoui double %1 to i64
6054 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
6055 ret <2 x i64> %vecinit4
6056 }
6058 define <2 x i64> @spltRegValConvdtoull(double %val) {
6059 ; P9BE-LABEL: spltRegValConvdtoull:
6060 ; P9BE: # %bb.0: # %entry
6061 ; P9BE-NEXT: xscvdpuxds f0, f1
6062 ; P9BE-NEXT: xxspltd v2, vs0, 0
6063 ; P9BE-NEXT: blr
6064 ;
6065 ; P9LE-LABEL: spltRegValConvdtoull:
6066 ; P9LE: # %bb.0: # %entry
6067 ; P9LE-NEXT: xscvdpuxds f0, f1
6068 ; P9LE-NEXT: xxspltd v2, vs0, 0
6069 ; P9LE-NEXT: blr
6070 ;
6071 ; P8BE-LABEL: spltRegValConvdtoull:
6072 ; P8BE: # %bb.0: # %entry
6073 ; P8BE-NEXT: xscvdpuxds f0, f1
6074 ; P8BE-NEXT: xxspltd v2, vs0, 0
6075 ; P8BE-NEXT: blr
6076 ;
6077 ; P8LE-LABEL: spltRegValConvdtoull:
6078 ; P8LE: # %bb.0: # %entry
6079 ; P8LE-NEXT: xscvdpuxds f0, f1
6080 ; P8LE-NEXT: xxspltd v2, vs0, 0
6081 ; P8LE-NEXT: blr
6082 entry:
6083 %conv = fptoui double %val to i64
6084 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
6085 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
6086 ret <2 x i64> %splat.splat
6087 }
6089 define <2 x i64> @spltMemValConvdtoull(ptr nocapture readonly %ptr) {
6090 ; P9BE-LABEL: spltMemValConvdtoull:
6091 ; P9BE: # %bb.0: # %entry
6092 ; P9BE-NEXT: lxvdsx vs0, 0, r3
6093 ; P9BE-NEXT: xvcvdpuxds v2, vs0
6094 ; P9BE-NEXT: blr
6095 ;
6096 ; P9LE-LABEL: spltMemValConvdtoull:
6097 ; P9LE: # %bb.0: # %entry
6098 ; P9LE-NEXT: lxvdsx vs0, 0, r3
6099 ; P9LE-NEXT: xvcvdpuxds v2, vs0
6100 ; P9LE-NEXT: blr
6101 ;
6102 ; P8BE-LABEL: spltMemValConvdtoull:
6103 ; P8BE: # %bb.0: # %entry
6104 ; P8BE-NEXT: lxvdsx vs0, 0, r3
6105 ; P8BE-NEXT: xvcvdpuxds v2, vs0
6106 ; P8BE-NEXT: blr
6107 ;
6108 ; P8LE-LABEL: spltMemValConvdtoull:
6109 ; P8LE: # %bb.0: # %entry
6110 ; P8LE-NEXT: lxvdsx vs0, 0, r3
6111 ; P8LE-NEXT: xvcvdpuxds v2, vs0
6112 ; P8LE-NEXT: blr
6113 entry:
6114 %0 = load double, ptr %ptr, align 8
6115 %conv = fptoui double %0 to i64
6116 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
6117 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
6118 ret <2 x i64> %splat.splat
6119 }
6121 ; Some additional patterns that come up in real code.
6122 define dso_local <2 x double> @sint_to_fp_widen02(<4 x i32> %a) {
6123 ; P9BE-LABEL: sint_to_fp_widen02:
6124 ; P9BE: # %bb.0: # %entry
6125 ; P9BE-NEXT: xvcvsxwdp v2, v2
6126 ; P9BE-NEXT: blr
6127 ;
6128 ; P9LE-LABEL: sint_to_fp_widen02:
6129 ; P9LE: # %bb.0: # %entry
6130 ; P9LE-NEXT: xxsldwi vs0, v2, v2, 1
6131 ; P9LE-NEXT: xvcvsxwdp v2, vs0
6132 ; P9LE-NEXT: blr
6133 ;
6134 ; P8BE-LABEL: sint_to_fp_widen02:
6135 ; P8BE: # %bb.0: # %entry
6136 ; P8BE-NEXT: xvcvsxwdp v2, v2
6137 ; P8BE-NEXT: blr
6138 ;
6139 ; P8LE-LABEL: sint_to_fp_widen02:
6140 ; P8LE: # %bb.0: # %entry
6141 ; P8LE-NEXT: xxsldwi vs0, v2, v2, 1
6142 ; P8LE-NEXT: xvcvsxwdp v2, vs0
6143 ; P8LE-NEXT: blr
6144 entry:
6145 %vecext = extractelement <4 x i32> %a, i32 0
6146 %conv = sitofp i32 %vecext to double
6147 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6148 %vecext1 = extractelement <4 x i32> %a, i32 2
6149 %conv2 = sitofp i32 %vecext1 to double
6150 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6151 ret <2 x double> %vecinit3
6152 }
6154 define dso_local <2 x double> @sint_to_fp_widen13(<4 x i32> %a) {
6155 ; P9BE-LABEL: sint_to_fp_widen13:
6156 ; P9BE: # %bb.0: # %entry
6157 ; P9BE-NEXT: xxsldwi vs0, v2, v2, 1
6158 ; P9BE-NEXT: xvcvsxwdp v2, vs0
6159 ; P9BE-NEXT: blr
6160 ;
6161 ; P9LE-LABEL: sint_to_fp_widen13:
6162 ; P9LE: # %bb.0: # %entry
6163 ; P9LE-NEXT: xvcvsxwdp v2, v2
6164 ; P9LE-NEXT: blr
6165 ;
6166 ; P8BE-LABEL: sint_to_fp_widen13:
6167 ; P8BE: # %bb.0: # %entry
6168 ; P8BE-NEXT: xxsldwi vs0, v2, v2, 1
6169 ; P8BE-NEXT: xvcvsxwdp v2, vs0
6170 ; P8BE-NEXT: blr
6171 ;
6172 ; P8LE-LABEL: sint_to_fp_widen13:
6173 ; P8LE: # %bb.0: # %entry
6174 ; P8LE-NEXT: xvcvsxwdp v2, v2
6175 ; P8LE-NEXT: blr
6176 entry:
6177 %vecext = extractelement <4 x i32> %a, i32 1
6178 %conv = sitofp i32 %vecext to double
6179 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6180 %vecext1 = extractelement <4 x i32> %a, i32 3
6181 %conv2 = sitofp i32 %vecext1 to double
6182 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6183 ret <2 x double> %vecinit3
6184 }
6186 define dso_local <2 x double> @uint_to_fp_widen02(<4 x i32> %a) {
6187 ; P9BE-LABEL: uint_to_fp_widen02:
6188 ; P9BE: # %bb.0: # %entry
6189 ; P9BE-NEXT: xvcvuxwdp v2, v2
6190 ; P9BE-NEXT: blr
6191 ;
6192 ; P9LE-LABEL: uint_to_fp_widen02:
6193 ; P9LE: # %bb.0: # %entry
6194 ; P9LE-NEXT: xxsldwi vs0, v2, v2, 1
6195 ; P9LE-NEXT: xvcvuxwdp v2, vs0
6196 ; P9LE-NEXT: blr
6197 ;
6198 ; P8BE-LABEL: uint_to_fp_widen02:
6199 ; P8BE: # %bb.0: # %entry
6200 ; P8BE-NEXT: xvcvuxwdp v2, v2
6201 ; P8BE-NEXT: blr
6202 ;
6203 ; P8LE-LABEL: uint_to_fp_widen02:
6204 ; P8LE: # %bb.0: # %entry
6205 ; P8LE-NEXT: xxsldwi vs0, v2, v2, 1
6206 ; P8LE-NEXT: xvcvuxwdp v2, vs0
6207 ; P8LE-NEXT: blr
6208 entry:
6209 %vecext = extractelement <4 x i32> %a, i32 0
6210 %conv = uitofp i32 %vecext to double
6211 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6212 %vecext1 = extractelement <4 x i32> %a, i32 2
6213 %conv2 = uitofp i32 %vecext1 to double
6214 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6215 ret <2 x double> %vecinit3
6216 }
6218 define dso_local <2 x double> @uint_to_fp_widen13(<4 x i32> %a) {
6219 ; P9BE-LABEL: uint_to_fp_widen13:
6220 ; P9BE: # %bb.0: # %entry
6221 ; P9BE-NEXT: xxsldwi vs0, v2, v2, 1
6222 ; P9BE-NEXT: xvcvuxwdp v2, vs0
6223 ; P9BE-NEXT: blr
6224 ;
6225 ; P9LE-LABEL: uint_to_fp_widen13:
6226 ; P9LE: # %bb.0: # %entry
6227 ; P9LE-NEXT: xvcvuxwdp v2, v2
6228 ; P9LE-NEXT: blr
6229 ;
6230 ; P8BE-LABEL: uint_to_fp_widen13:
6231 ; P8BE: # %bb.0: # %entry
6232 ; P8BE-NEXT: xxsldwi vs0, v2, v2, 1
6233 ; P8BE-NEXT: xvcvuxwdp v2, vs0
6234 ; P8BE-NEXT: blr
6235 ;
6236 ; P8LE-LABEL: uint_to_fp_widen13:
6237 ; P8LE: # %bb.0: # %entry
6238 ; P8LE-NEXT: xvcvuxwdp v2, v2
6239 ; P8LE-NEXT: blr
6240 entry:
6241 %vecext = extractelement <4 x i32> %a, i32 1
6242 %conv = uitofp i32 %vecext to double
6243 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6244 %vecext1 = extractelement <4 x i32> %a, i32 3
6245 %conv2 = uitofp i32 %vecext1 to double
6246 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6247 ret <2 x double> %vecinit3
6248 }
6250 define dso_local <2 x double> @fp_extend01(<4 x float> %a) {
6251 ; P9BE-LABEL: fp_extend01:
6252 ; P9BE: # %bb.0: # %entry
6253 ; P9BE-NEXT: xxmrghw vs0, v2, v2
6254 ; P9BE-NEXT: xvcvspdp v2, vs0
6255 ; P9BE-NEXT: blr
6256 ;
6257 ; P9LE-LABEL: fp_extend01:
6258 ; P9LE: # %bb.0: # %entry
6259 ; P9LE-NEXT: xxmrglw vs0, v2, v2
6260 ; P9LE-NEXT: xvcvspdp v2, vs0
6261 ; P9LE-NEXT: blr
6262 ;
6263 ; P8BE-LABEL: fp_extend01:
6264 ; P8BE: # %bb.0: # %entry
6265 ; P8BE-NEXT: xxmrghw vs0, v2, v2
6266 ; P8BE-NEXT: xvcvspdp v2, vs0
6267 ; P8BE-NEXT: blr
6268 ;
6269 ; P8LE-LABEL: fp_extend01:
6270 ; P8LE: # %bb.0: # %entry
6271 ; P8LE-NEXT: xxmrglw vs0, v2, v2
6272 ; P8LE-NEXT: xvcvspdp v2, vs0
6273 ; P8LE-NEXT: blr
6274 entry:
6275 %vecext = extractelement <4 x float> %a, i32 0
6276 %conv = fpext float %vecext to double
6277 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6278 %vecext1 = extractelement <4 x float> %a, i32 1
6279 %conv2 = fpext float %vecext1 to double
6280 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6281 ret <2 x double> %vecinit3
6282 }
6284 define dso_local <2 x double> @fp_extend10(<4 x float> %a) {
6285 ; P9BE-LABEL: fp_extend10:
6286 ; P9BE: # %bb.0: # %entry
6287 ; P9BE-NEXT: xxmrghw vs0, v2, v2
6288 ; P9BE-NEXT: xvcvspdp vs0, vs0
6289 ; P9BE-NEXT: xxswapd v2, vs0
6290 ; P9BE-NEXT: blr
6291 ;
6292 ; P9LE-LABEL: fp_extend10:
6293 ; P9LE: # %bb.0: # %entry
6294 ; P9LE-NEXT: xxmrglw vs0, v2, v2
6295 ; P9LE-NEXT: xvcvspdp vs0, vs0
6296 ; P9LE-NEXT: xxswapd v2, vs0
6297 ; P9LE-NEXT: blr
6298 ;
6299 ; P8BE-LABEL: fp_extend10:
6300 ; P8BE: # %bb.0: # %entry
6301 ; P8BE-NEXT: xxmrghw vs0, v2, v2
6302 ; P8BE-NEXT: xvcvspdp vs0, vs0
6303 ; P8BE-NEXT: xxswapd v2, vs0
6304 ; P8BE-NEXT: blr
6305 ;
6306 ; P8LE-LABEL: fp_extend10:
6307 ; P8LE: # %bb.0: # %entry
6308 ; P8LE-NEXT: xxmrglw vs0, v2, v2
6309 ; P8LE-NEXT: xvcvspdp vs0, vs0
6310 ; P8LE-NEXT: xxswapd v2, vs0
6311 ; P8LE-NEXT: blr
6312 entry:
6313 %vecext = extractelement <4 x float> %a, i32 1
6314 %conv = fpext float %vecext to double
6315 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6316 %vecext1 = extractelement <4 x float> %a, i32 0
6317 %conv2 = fpext float %vecext1 to double
6318 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6319 ret <2 x double> %vecinit3
6320 }
6322 define dso_local <2 x double> @fp_extend02(<4 x float> %a) {
6323 ; P9BE-LABEL: fp_extend02:
6324 ; P9BE: # %bb.0: # %entry
6325 ; P9BE-NEXT: xvcvspdp v2, v2
6326 ; P9BE-NEXT: blr
6327 ;
6328 ; P9LE-LABEL: fp_extend02:
6329 ; P9LE: # %bb.0: # %entry
6330 ; P9LE-NEXT: xxsldwi vs0, v2, v2, 1
6331 ; P9LE-NEXT: xvcvspdp v2, vs0
6332 ; P9LE-NEXT: blr
6333 ;
6334 ; P8BE-LABEL: fp_extend02:
6335 ; P8BE: # %bb.0: # %entry
6336 ; P8BE-NEXT: xvcvspdp v2, v2
6337 ; P8BE-NEXT: blr
6338 ;
6339 ; P8LE-LABEL: fp_extend02:
6340 ; P8LE: # %bb.0: # %entry
6341 ; P8LE-NEXT: xxsldwi vs0, v2, v2, 1
6342 ; P8LE-NEXT: xvcvspdp v2, vs0
6343 ; P8LE-NEXT: blr
6344 entry:
6345 %vecext = extractelement <4 x float> %a, i32 0
6346 %conv = fpext float %vecext to double
6347 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6348 %vecext1 = extractelement <4 x float> %a, i32 2
6349 %conv2 = fpext float %vecext1 to double
6350 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6351 ret <2 x double> %vecinit3
6352 }
6354 define dso_local <2 x double> @fp_extend13(<4 x float> %a) {
6355 ; P9BE-LABEL: fp_extend13:
6356 ; P9BE: # %bb.0: # %entry
6357 ; P9BE-NEXT: xxsldwi vs0, v2, v2, 1
6358 ; P9BE-NEXT: xvcvspdp v2, vs0
6359 ; P9BE-NEXT: blr
6360 ;
6361 ; P9LE-LABEL: fp_extend13:
6362 ; P9LE: # %bb.0: # %entry
6363 ; P9LE-NEXT: xvcvspdp v2, v2
6364 ; P9LE-NEXT: blr
6365 ;
6366 ; P8BE-LABEL: fp_extend13:
6367 ; P8BE: # %bb.0: # %entry
6368 ; P8BE-NEXT: xxsldwi vs0, v2, v2, 1
6369 ; P8BE-NEXT: xvcvspdp v2, vs0
6370 ; P8BE-NEXT: blr
6371 ;
6372 ; P8LE-LABEL: fp_extend13:
6373 ; P8LE: # %bb.0: # %entry
6374 ; P8LE-NEXT: xvcvspdp v2, v2
6375 ; P8LE-NEXT: blr
6376 entry:
6377 %vecext = extractelement <4 x float> %a, i32 1
6378 %conv = fpext float %vecext to double
6379 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6380 %vecext1 = extractelement <4 x float> %a, i32 3
6381 %conv2 = fpext float %vecext1 to double
6382 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6383 ret <2 x double> %vecinit3
6384 }
6386 define dso_local <2 x double> @fp_extend23(<4 x float> %a) {
6387 ; P9BE-LABEL: fp_extend23:
6388 ; P9BE: # %bb.0: # %entry
6389 ; P9BE-NEXT: xxmrglw vs0, v2, v2
6390 ; P9BE-NEXT: xvcvspdp v2, vs0
6391 ; P9BE-NEXT: blr
6392 ;
6393 ; P9LE-LABEL: fp_extend23:
6394 ; P9LE: # %bb.0: # %entry
6395 ; P9LE-NEXT: xxmrghw vs0, v2, v2
6396 ; P9LE-NEXT: xvcvspdp v2, vs0
6397 ; P9LE-NEXT: blr
6398 ;
6399 ; P8BE-LABEL: fp_extend23:
6400 ; P8BE: # %bb.0: # %entry
6401 ; P8BE-NEXT: xxmrglw vs0, v2, v2
6402 ; P8BE-NEXT: xvcvspdp v2, vs0
6403 ; P8BE-NEXT: blr
6404 ;
6405 ; P8LE-LABEL: fp_extend23:
6406 ; P8LE: # %bb.0: # %entry
6407 ; P8LE-NEXT: xxmrghw vs0, v2, v2
6408 ; P8LE-NEXT: xvcvspdp v2, vs0
6409 ; P8LE-NEXT: blr
6410 entry:
6411 %vecext = extractelement <4 x float> %a, i32 2
6412 %conv = fpext float %vecext to double
6413 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6414 %vecext1 = extractelement <4 x float> %a, i32 3
6415 %conv2 = fpext float %vecext1 to double
6416 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6417 ret <2 x double> %vecinit3
6418 }
6420 define dso_local <2 x double> @fp_extend32(<4 x float> %a) {
6421 ; P9BE-LABEL: fp_extend32:
6422 ; P9BE: # %bb.0: # %entry
6423 ; P9BE-NEXT: xxmrglw vs0, v2, v2
6424 ; P9BE-NEXT: xvcvspdp vs0, vs0
6425 ; P9BE-NEXT: xxswapd v2, vs0
6426 ; P9BE-NEXT: blr
6427 ;
6428 ; P9LE-LABEL: fp_extend32:
6429 ; P9LE: # %bb.0: # %entry
6430 ; P9LE-NEXT: xxmrghw vs0, v2, v2
6431 ; P9LE-NEXT: xvcvspdp vs0, vs0
6432 ; P9LE-NEXT: xxswapd v2, vs0
6433 ; P9LE-NEXT: blr
6434 ;
6435 ; P8BE-LABEL: fp_extend32:
6436 ; P8BE: # %bb.0: # %entry
6437 ; P8BE-NEXT: xxmrglw vs0, v2, v2
6438 ; P8BE-NEXT: xvcvspdp vs0, vs0
6439 ; P8BE-NEXT: xxswapd v2, vs0
6440 ; P8BE-NEXT: blr
6441 ;
6442 ; P8LE-LABEL: fp_extend32:
6443 ; P8LE: # %bb.0: # %entry
6444 ; P8LE-NEXT: xxmrghw vs0, v2, v2
6445 ; P8LE-NEXT: xvcvspdp vs0, vs0
6446 ; P8LE-NEXT: xxswapd v2, vs0
6447 ; P8LE-NEXT: blr
6448 entry:
6449 %vecext = extractelement <4 x float> %a, i32 3
6450 %conv = fpext float %vecext to double
6451 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6452 %vecext1 = extractelement <4 x float> %a, i32 2
6453 %conv2 = fpext float %vecext1 to double
6454 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6455 ret <2 x double> %vecinit3
6456 }
6458 define dso_local <2 x double> @fp_extend_two00(<4 x float> %a, <4 x float> %b) {
6459 ; P9BE-LABEL: fp_extend_two00:
6460 ; P9BE: # %bb.0: # %entry
6461 ; P9BE-NEXT: xxmrghd vs0, v2, v3
6462 ; P9BE-NEXT: xvcvspdp v2, vs0
6463 ; P9BE-NEXT: blr
6464 ;
6465 ; P9LE-LABEL: fp_extend_two00:
6466 ; P9LE: # %bb.0: # %entry
6467 ; P9LE-NEXT: xxmrgld vs0, v3, v2
6468 ; P9LE-NEXT: xxsldwi vs0, vs0, vs0, 1
6469 ; P9LE-NEXT: xvcvspdp v2, vs0
6470 ; P9LE-NEXT: blr
6471 ;
6472 ; P8BE-LABEL: fp_extend_two00:
6473 ; P8BE: # %bb.0: # %entry
6474 ; P8BE-NEXT: xxmrghd vs0, v2, v3
6475 ; P8BE-NEXT: xvcvspdp v2, vs0
6476 ; P8BE-NEXT: blr
6477 ;
6478 ; P8LE-LABEL: fp_extend_two00:
6479 ; P8LE: # %bb.0: # %entry
6480 ; P8LE-NEXT: xxmrgld vs0, v3, v2
6481 ; P8LE-NEXT: xxsldwi vs0, vs0, vs0, 1
6482 ; P8LE-NEXT: xvcvspdp v2, vs0
6483 ; P8LE-NEXT: blr
6484 entry:
6485 %vecext = extractelement <4 x float> %a, i32 0
6486 %conv = fpext float %vecext to double
6487 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6488 %vecext1 = extractelement <4 x float> %b, i32 0
6489 %conv2 = fpext float %vecext1 to double
6490 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6491 ret <2 x double> %vecinit3
6492 }
6494 define dso_local <2 x double> @fp_extend_two33(<4 x float> %a, <4 x float> %b) {
6495 ; P9BE-LABEL: fp_extend_two33:
6496 ; P9BE: # %bb.0: # %entry
6497 ; P9BE-NEXT: xxmrgld vs0, v2, v3
6498 ; P9BE-NEXT: xxsldwi vs0, vs0, vs0, 1
6499 ; P9BE-NEXT: xvcvspdp v2, vs0
6500 ; P9BE-NEXT: blr
6501 ;
6502 ; P9LE-LABEL: fp_extend_two33:
6503 ; P9LE: # %bb.0: # %entry
6504 ; P9LE-NEXT: xxmrghd vs0, v3, v2
6505 ; P9LE-NEXT: xvcvspdp v2, vs0
6506 ; P9LE-NEXT: blr
6507 ;
6508 ; P8BE-LABEL: fp_extend_two33:
6509 ; P8BE: # %bb.0: # %entry
6510 ; P8BE-NEXT: xxmrgld vs0, v2, v3
6511 ; P8BE-NEXT: xxsldwi vs0, vs0, vs0, 1
6512 ; P8BE-NEXT: xvcvspdp v2, vs0
6513 ; P8BE-NEXT: blr
6514 ;
6515 ; P8LE-LABEL: fp_extend_two33:
6516 ; P8LE: # %bb.0: # %entry
6517 ; P8LE-NEXT: xxmrghd vs0, v3, v2
6518 ; P8LE-NEXT: xvcvspdp v2, vs0
6519 ; P8LE-NEXT: blr
6520 entry:
6521 %vecext = extractelement <4 x float> %a, i32 3
6522 %conv = fpext float %vecext to double
6523 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6524 %vecext1 = extractelement <4 x float> %b, i32 3
6525 %conv2 = fpext float %vecext1 to double
6526 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6527 ret <2 x double> %vecinit3
6528 }
6530 define dso_local <2 x i64> @test_xvcvspsxds13(<4 x float> %a) local_unnamed_addr {
6531 ; P9BE-LABEL: test_xvcvspsxds13:
6532 ; P9BE: # %bb.0: # %entry
6533 ; P9BE-NEXT: xxsldwi vs0, v2, v2, 1
6534 ; P9BE-NEXT: xvcvspsxds v2, vs0
6535 ; P9BE-NEXT: blr
6536 ;
6537 ; P9LE-LABEL: test_xvcvspsxds13:
6538 ; P9LE: # %bb.0: # %entry
6539 ; P9LE-NEXT: xvcvspsxds v2, v2
6540 ; P9LE-NEXT: blr
6541 ;
6542 ; P8BE-LABEL: test_xvcvspsxds13:
6543 ; P8BE: # %bb.0: # %entry
6544 ; P8BE-NEXT: xxsldwi vs0, v2, v2, 1
6545 ; P8BE-NEXT: xvcvspsxds v2, vs0
6546 ; P8BE-NEXT: blr
6547 ;
6548 ; P8LE-LABEL: test_xvcvspsxds13:
6549 ; P8LE: # %bb.0: # %entry
6550 ; P8LE-NEXT: xvcvspsxds v2, v2
6551 ; P8LE-NEXT: blr
6552 entry:
6553 %vecext = extractelement <4 x float> %a, i32 1
6554 %conv = fptosi float %vecext to i64
6555 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
6556 %vecext1 = extractelement <4 x float> %a, i32 3
6557 %conv2 = fptosi float %vecext1 to i64
6558 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
6559 ret <2 x i64> %vecinit3
6560 }
6562 define dso_local <2 x i64> @test_xvcvspuxds13(<4 x float> %a) local_unnamed_addr {
6563 ; P9BE-LABEL: test_xvcvspuxds13:
6564 ; P9BE: # %bb.0: # %entry
6565 ; P9BE-NEXT: xxsldwi vs0, v2, v2, 1
6566 ; P9BE-NEXT: xvcvspuxds v2, vs0
6567 ; P9BE-NEXT: blr
6568 ;
6569 ; P9LE-LABEL: test_xvcvspuxds13:
6570 ; P9LE: # %bb.0: # %entry
6571 ; P9LE-NEXT: xvcvspuxds v2, v2
6572 ; P9LE-NEXT: blr
6573 ;
6574 ; P8BE-LABEL: test_xvcvspuxds13:
6575 ; P8BE: # %bb.0: # %entry
6576 ; P8BE-NEXT: xxsldwi vs0, v2, v2, 1
6577 ; P8BE-NEXT: xvcvspuxds v2, vs0
6578 ; P8BE-NEXT: blr
6579 ;
6580 ; P8LE-LABEL: test_xvcvspuxds13:
6581 ; P8LE: # %bb.0: # %entry
6582 ; P8LE-NEXT: xvcvspuxds v2, v2
6583 ; P8LE-NEXT: blr
6584 entry:
6585 %vecext = extractelement <4 x float> %a, i32 1
6586 %conv = fptoui float %vecext to i64
6587 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
6588 %vecext1 = extractelement <4 x float> %a, i32 3
6589 %conv2 = fptoui float %vecext1 to i64
6590 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
6591 ret <2 x i64> %vecinit3
6592 }
6594 define dso_local <2 x i64> @test_xvcvspsxds02(<4 x float> %a) local_unnamed_addr {
6595 ; P9BE-LABEL: test_xvcvspsxds02:
6596 ; P9BE: # %bb.0: # %entry
6597 ; P9BE-NEXT: xvcvspsxds v2, v2
6598 ; P9BE-NEXT: blr
6599 ;
6600 ; P9LE-LABEL: test_xvcvspsxds02:
6601 ; P9LE: # %bb.0: # %entry
6602 ; P9LE-NEXT: xxsldwi vs0, v2, v2, 1
6603 ; P9LE-NEXT: xvcvspsxds v2, vs0
6604 ; P9LE-NEXT: blr
6605 ;
6606 ; P8BE-LABEL: test_xvcvspsxds02:
6607 ; P8BE: # %bb.0: # %entry
6608 ; P8BE-NEXT: xvcvspsxds v2, v2
6609 ; P8BE-NEXT: blr
6610 ;
6611 ; P8LE-LABEL: test_xvcvspsxds02:
6612 ; P8LE: # %bb.0: # %entry
6613 ; P8LE-NEXT: xxsldwi vs0, v2, v2, 1
6614 ; P8LE-NEXT: xvcvspsxds v2, vs0
6615 ; P8LE-NEXT: blr
6616 entry:
6617 %vecext = extractelement <4 x float> %a, i32 0
6618 %conv = fptosi float %vecext to i64
6619 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
6620 %vecext1 = extractelement <4 x float> %a, i32 2
6621 %conv2 = fptosi float %vecext1 to i64
6622 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
6623 ret <2 x i64> %vecinit3
6624 }
6626 define dso_local <2 x i64> @test_xvcvspuxds02(<4 x float> %a) local_unnamed_addr {
6627 ; P9BE-LABEL: test_xvcvspuxds02:
6628 ; P9BE: # %bb.0: # %entry
6629 ; P9BE-NEXT: xvcvspuxds v2, v2
6630 ; P9BE-NEXT: blr
6631 ;
6632 ; P9LE-LABEL: test_xvcvspuxds02:
6633 ; P9LE: # %bb.0: # %entry
6634 ; P9LE-NEXT: xxsldwi vs0, v2, v2, 1
6635 ; P9LE-NEXT: xvcvspuxds v2, vs0
6636 ; P9LE-NEXT: blr
6637 ;
6638 ; P8BE-LABEL: test_xvcvspuxds02:
6639 ; P8BE: # %bb.0: # %entry
6640 ; P8BE-NEXT: xvcvspuxds v2, v2
6641 ; P8BE-NEXT: blr
6642 ;
6643 ; P8LE-LABEL: test_xvcvspuxds02:
6644 ; P8LE: # %bb.0: # %entry
6645 ; P8LE-NEXT: xxsldwi vs0, v2, v2, 1
6646 ; P8LE-NEXT: xvcvspuxds v2, vs0
6647 ; P8LE-NEXT: blr
6648 entry:
6649 %vecext = extractelement <4 x float> %a, i32 0
6650 %conv = fptoui float %vecext to i64
6651 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
6652 %vecext1 = extractelement <4 x float> %a, i32 2
6653 %conv2 = fptoui float %vecext1 to i64
6654 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
6655 ret <2 x i64> %vecinit3
6656 }