| blob | 9dbac7e2f3739dac0fa1d80a20951c8ac67b9890 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; This test is a copy of mma-intrinsics.ll except that it uses mcpu=future.
3 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
4 ; RUN: -mcpu=future -ppc-asm-full-reg-names \
5 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
6 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
7 ; RUN: -mcpu=future -ppc-asm-full-reg-names \
8 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
9 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
10 ; RUN: -mcpu=future -ppc-asm-full-reg-names \
11 ; RUN: -ppc-vsr-nums-as-vr -O0 < %s | FileCheck %s --check-prefix=CHECK-O0
12 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
13 ; RUN: -mcpu=future -ppc-asm-full-reg-names \
14 ; RUN: -ppc-vsr-nums-as-vr -O0 < %s | FileCheck %s --check-prefix=CHECK-O0-BE
15 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-aix- \
16 ; RUN: -mcpu=future -vec-extabi \
17 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-AIX64
18 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-aix- \
19 ; RUN: -mcpu=future -vec-extabi \
20 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-AIX32
22 ; TODO: This test is missing some of the tests from mma-intrinsics.ll because
23 ; those tests do not work for mcpu=future. Once the fixes are in they
24 ; should be added back to this file.
26 ; assemble_acc
27 declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
28 define void @ass_acc(ptr %ptr, <16 x i8> %vc) {
29 ; CHECK-LABEL: ass_acc:
30 ; CHECK: # %bb.0: # %entry
31 ; CHECK-NEXT: vmr v3, v2
32 ; CHECK-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp34, 0
33 ; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
34 ; CHECK-NEXT: stxv v4, 48(r3)
35 ; CHECK-NEXT: stxv v5, 32(r3)
36 ; CHECK-NEXT: stxv v2, 16(r3)
37 ; CHECK-NEXT: stxv v3, 0(r3)
38 ; CHECK-NEXT: blr
39 ;
40 ; CHECK-BE-LABEL: ass_acc:
41 ; CHECK-BE: # %bb.0: # %entry
42 ; CHECK-BE-NEXT: vmr v3, v2
43 ; CHECK-BE-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp34, 0
44 ; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
45 ; CHECK-BE-NEXT: stxv v5, 48(r3)
46 ; CHECK-BE-NEXT: stxv v4, 32(r3)
47 ; CHECK-BE-NEXT: stxv v3, 16(r3)
48 ; CHECK-BE-NEXT: stxv v2, 0(r3)
49 ; CHECK-BE-NEXT: blr
50 ;
51 ; CHECK-O0-LABEL: ass_acc:
52 ; CHECK-O0: # %bb.0: # %entry
53 ; CHECK-O0-NEXT: vmr v4, v2
54 ; CHECK-O0-NEXT: # implicit-def: $vsrp17
55 ; CHECK-O0-NEXT: vmr v3, v4
56 ; CHECK-O0-NEXT: vmr v2, v4
57 ; CHECK-O0-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp34, 0
58 ; CHECK-O0-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
59 ; CHECK-O0-NEXT: xxlor vs0, v4, v4
60 ; CHECK-O0-NEXT: stxv vs0, 48(r3)
61 ; CHECK-O0-NEXT: xxlor vs0, v5, v5
62 ; CHECK-O0-NEXT: stxv vs0, 32(r3)
63 ; CHECK-O0-NEXT: xxlor vs0, v2, v2
64 ; CHECK-O0-NEXT: stxv vs0, 16(r3)
65 ; CHECK-O0-NEXT: xxlor vs0, v3, v3
66 ; CHECK-O0-NEXT: stxv vs0, 0(r3)
67 ; CHECK-O0-NEXT: blr
68 ;
69 ; CHECK-O0-BE-LABEL: ass_acc:
70 ; CHECK-O0-BE: # %bb.0: # %entry
71 ; CHECK-O0-BE-NEXT: vmr v4, v2
72 ; CHECK-O0-BE-NEXT: # implicit-def: $vsrp17
73 ; CHECK-O0-BE-NEXT: vmr v3, v4
74 ; CHECK-O0-BE-NEXT: vmr v2, v4
75 ; CHECK-O0-BE-NEXT: dmxxinstfdmr512 wacc0, vsp34, vsp34, 0
76 ; CHECK-O0-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
77 ; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5
78 ; CHECK-O0-BE-NEXT: stxv vs0, 48(r3)
79 ; CHECK-O0-BE-NEXT: xxlor vs0, v4, v4
80 ; CHECK-O0-BE-NEXT: stxv vs0, 32(r3)
81 ; CHECK-O0-BE-NEXT: xxlor vs0, v3, v3
82 ; CHECK-O0-BE-NEXT: stxv vs0, 16(r3)
83 ; CHECK-O0-BE-NEXT: xxlor vs0, v2, v2
84 ; CHECK-O0-BE-NEXT: stxv vs0, 0(r3)
85 ; CHECK-O0-BE-NEXT: blr
86 ;
87 ; CHECK-AIX64-LABEL: ass_acc:
88 ; CHECK-AIX64: # %bb.0: # %entry
89 ; CHECK-AIX64-NEXT: vmr 3, 2
90 ; CHECK-AIX64-NEXT: dmxxinstfdmr512 0, 34, 34, 0
91 ; CHECK-AIX64-NEXT: dmxxextfdmr512 0, 34, 36, 0
92 ; CHECK-AIX64-NEXT: stxv 5, 48(3)
93 ; CHECK-AIX64-NEXT: stxv 4, 32(3)
94 ; CHECK-AIX64-NEXT: stxv 3, 16(3)
95 ; CHECK-AIX64-NEXT: stxv 2, 0(3)
96 ; CHECK-AIX64-NEXT: blr
97 ;
98 ; CHECK-AIX32-LABEL: ass_acc:
99 ; CHECK-AIX32: # %bb.0: # %entry
100 ; CHECK-AIX32-NEXT: vmr 3, 2
101 ; CHECK-AIX32-NEXT: dmxxinstfdmr512 0, 34, 34, 0
102 ; CHECK-AIX32-NEXT: dmxxextfdmr512 0, 34, 36, 0
103 ; CHECK-AIX32-NEXT: stxv 5, 48(3)
104 ; CHECK-AIX32-NEXT: stxv 4, 32(3)
105 ; CHECK-AIX32-NEXT: stxv 3, 16(3)
106 ; CHECK-AIX32-NEXT: stxv 2, 0(3)
107 ; CHECK-AIX32-NEXT: blr
108 entry:
109 %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
110 store <512 x i1> %0, ptr %ptr, align 64
111 ret void
112 }
114 ; xxsetaccz
115 declare <512 x i1> @llvm.ppc.mma.xxsetaccz()
116 define void @int_xxsetaccz(ptr %ptr) {
117 ; CHECK-LABEL: int_xxsetaccz:
118 ; CHECK: # %bb.0: # %entry
119 ; CHECK-NEXT: xxsetaccz wacc0
120 ; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
121 ; CHECK-NEXT: stxv v4, 48(r3)
122 ; CHECK-NEXT: stxv v5, 32(r3)
123 ; CHECK-NEXT: stxv v2, 16(r3)
124 ; CHECK-NEXT: stxv v3, 0(r3)
125 ; CHECK-NEXT: blr
126 ;
127 ; CHECK-BE-LABEL: int_xxsetaccz:
128 ; CHECK-BE: # %bb.0: # %entry
129 ; CHECK-BE-NEXT: xxsetaccz wacc0
130 ; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
131 ; CHECK-BE-NEXT: stxv v5, 48(r3)
132 ; CHECK-BE-NEXT: stxv v4, 32(r3)
133 ; CHECK-BE-NEXT: stxv v3, 16(r3)
134 ; CHECK-BE-NEXT: stxv v2, 0(r3)
135 ; CHECK-BE-NEXT: blr
136 ;
137 ; CHECK-O0-LABEL: int_xxsetaccz:
138 ; CHECK-O0: # %bb.0: # %entry
139 ; CHECK-O0-NEXT: xxsetaccz wacc0
140 ; CHECK-O0-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
141 ; CHECK-O0-NEXT: xxlor vs0, v4, v4
142 ; CHECK-O0-NEXT: stxv vs0, 48(r3)
143 ; CHECK-O0-NEXT: xxlor vs0, v5, v5
144 ; CHECK-O0-NEXT: stxv vs0, 32(r3)
145 ; CHECK-O0-NEXT: xxlor vs0, v2, v2
146 ; CHECK-O0-NEXT: stxv vs0, 16(r3)
147 ; CHECK-O0-NEXT: xxlor vs0, v3, v3
148 ; CHECK-O0-NEXT: stxv vs0, 0(r3)
149 ; CHECK-O0-NEXT: blr
150 ;
151 ; CHECK-O0-BE-LABEL: int_xxsetaccz:
152 ; CHECK-O0-BE: # %bb.0: # %entry
153 ; CHECK-O0-BE-NEXT: xxsetaccz wacc0
154 ; CHECK-O0-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
155 ; CHECK-O0-BE-NEXT: xxlor vs0, v5, v5
156 ; CHECK-O0-BE-NEXT: stxv vs0, 48(r3)
157 ; CHECK-O0-BE-NEXT: xxlor vs0, v4, v4
158 ; CHECK-O0-BE-NEXT: stxv vs0, 32(r3)
159 ; CHECK-O0-BE-NEXT: xxlor vs0, v3, v3
160 ; CHECK-O0-BE-NEXT: stxv vs0, 16(r3)
161 ; CHECK-O0-BE-NEXT: xxlor vs0, v2, v2
162 ; CHECK-O0-BE-NEXT: stxv vs0, 0(r3)
163 ; CHECK-O0-BE-NEXT: blr
164 ;
165 ; CHECK-AIX64-LABEL: int_xxsetaccz:
166 ; CHECK-AIX64: # %bb.0: # %entry
167 ; CHECK-AIX64-NEXT: xxsetaccz 0
168 ; CHECK-AIX64-NEXT: dmxxextfdmr512 0, 34, 36, 0
169 ; CHECK-AIX64-NEXT: stxv 5, 48(3)
170 ; CHECK-AIX64-NEXT: stxv 4, 32(3)
171 ; CHECK-AIX64-NEXT: stxv 3, 16(3)
172 ; CHECK-AIX64-NEXT: stxv 2, 0(3)
173 ; CHECK-AIX64-NEXT: blr
174 ;
175 ; CHECK-AIX32-LABEL: int_xxsetaccz:
176 ; CHECK-AIX32: # %bb.0: # %entry
177 ; CHECK-AIX32-NEXT: xxsetaccz 0
178 ; CHECK-AIX32-NEXT: dmxxextfdmr512 0, 34, 36, 0
179 ; CHECK-AIX32-NEXT: stxv 5, 48(3)
180 ; CHECK-AIX32-NEXT: stxv 4, 32(3)
181 ; CHECK-AIX32-NEXT: stxv 3, 16(3)
182 ; CHECK-AIX32-NEXT: stxv 2, 0(3)
183 ; CHECK-AIX32-NEXT: blr
184 entry:
185 %0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()
186 store <512 x i1> %0, ptr %ptr, align 64
187 ret void
188 }
190 ; disassemble_acc
191 declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)
192 define void @disass_acc(ptr %ptr1, ptr %ptr2, ptr %ptr3, ptr %ptr4) {
193 ; CHECK-LABEL: disass_acc:
194 ; CHECK: # %bb.0: # %entry
195 ; CHECK-NEXT: xxsetaccz wacc0
196 ; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
197 ; CHECK-NEXT: stxv v5, 0(r3)
198 ; CHECK-NEXT: stxv v4, 0(r4)
199 ; CHECK-NEXT: stxv v3, 0(r5)
200 ; CHECK-NEXT: stxv v2, 0(r6)
201 ; CHECK-NEXT: blr
202 ;
203 ; CHECK-BE-LABEL: disass_acc:
204 ; CHECK-BE: # %bb.0: # %entry
205 ; CHECK-BE-NEXT: xxsetaccz wacc0
206 ; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
207 ; CHECK-BE-NEXT: stxv v2, 0(r3)
208 ; CHECK-BE-NEXT: stxv v3, 0(r4)
209 ; CHECK-BE-NEXT: stxv v4, 0(r5)
210 ; CHECK-BE-NEXT: stxv v5, 0(r6)
211 ; CHECK-BE-NEXT: blr
212 ;
213 ; CHECK-O0-LABEL: disass_acc:
214 ; CHECK-O0: # %bb.0: # %entry
215 ; CHECK-O0-NEXT: xxsetaccz wacc0
216 ; CHECK-O0-NEXT: dmxxextfdmr512 wacc0, vsp32, vsp36, 0
217 ; CHECK-O0-NEXT: vmr v2, v0
218 ; CHECK-O0-NEXT: xxlor vs0, v1, v1
219 ; CHECK-O0-NEXT: xxlor vs1, v4, v4
220 ; CHECK-O0-NEXT: xxlor vs2, v5, v5
221 ; CHECK-O0-NEXT: stxv vs2, 0(r3)
222 ; CHECK-O0-NEXT: stxv vs1, 0(r4)
223 ; CHECK-O0-NEXT: stxv vs0, 0(r5)
224 ; CHECK-O0-NEXT: stxv v2, 0(r6)
225 ; CHECK-O0-NEXT: blr
226 ;
227 ; CHECK-O0-BE-LABEL: disass_acc:
228 ; CHECK-O0-BE: # %bb.0: # %entry
229 ; CHECK-O0-BE-NEXT: xxsetaccz wacc0
230 ; CHECK-O0-BE-NEXT: dmxxextfdmr512 wacc0, vsp36, vsp32, 0
231 ; CHECK-O0-BE-NEXT: vmr v2, v1
232 ; CHECK-O0-BE-NEXT: xxlor vs0, v0, v0
233 ; CHECK-O0-BE-NEXT: xxlor vs1, v5, v5
234 ; CHECK-O0-BE-NEXT: xxlor vs2, v4, v4
235 ; CHECK-O0-BE-NEXT: stxv vs2, 0(r3)
236 ; CHECK-O0-BE-NEXT: stxv vs1, 0(r4)
237 ; CHECK-O0-BE-NEXT: stxv vs0, 0(r5)
238 ; CHECK-O0-BE-NEXT: stxv v2, 0(r6)
239 ; CHECK-O0-BE-NEXT: blr
240 ;
241 ; CHECK-AIX64-LABEL: disass_acc:
242 ; CHECK-AIX64: # %bb.0: # %entry
243 ; CHECK-AIX64-NEXT: xxsetaccz 0
244 ; CHECK-AIX64-NEXT: dmxxextfdmr512 0, 34, 36, 0
245 ; CHECK-AIX64-NEXT: stxv 2, 0(3)
246 ; CHECK-AIX64-NEXT: stxv 3, 0(4)
247 ; CHECK-AIX64-NEXT: stxv 4, 0(5)
248 ; CHECK-AIX64-NEXT: stxv 5, 0(6)
249 ; CHECK-AIX64-NEXT: blr
250 ;
251 ; CHECK-AIX32-LABEL: disass_acc:
252 ; CHECK-AIX32: # %bb.0: # %entry
253 ; CHECK-AIX32-NEXT: xxsetaccz 0
254 ; CHECK-AIX32-NEXT: dmxxextfdmr512 0, 34, 36, 0
255 ; CHECK-AIX32-NEXT: stxv 2, 0(3)
256 ; CHECK-AIX32-NEXT: stxv 3, 0(4)
257 ; CHECK-AIX32-NEXT: stxv 4, 0(5)
258 ; CHECK-AIX32-NEXT: stxv 5, 0(6)
259 ; CHECK-AIX32-NEXT: blr
260 entry:
261 %0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()
262 %1 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %0)
263 %2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 0
264 %3 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 1
265 %4 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2
266 %5 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 3
267 store <16 x i8> %2, ptr %ptr1, align 16
268 store <16 x i8> %3, ptr %ptr2, align 16
269 store <16 x i8> %4, ptr %ptr3, align 16
270 store <16 x i8> %5, ptr %ptr4, align 16
271 ret void
272 }
274 declare <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1>, <16 x i8>, <16 x i8>)
275 declare <512 x i1> @llvm.ppc.mma.xvf32gerpn(<512 x i1>, <16 x i8>, <16 x i8>)
276 declare <512 x i1> @llvm.ppc.mma.xvf32gernp(<512 x i1>, <16 x i8>, <16 x i8>)
278 define void @testcse(ptr %res, <16 x i8> %vc) {
279 ; CHECK-LABEL: testcse:
280 ; CHECK: # %bb.0: # %entry
281 ; CHECK-NEXT: xxsetaccz wacc0
282 ; CHECK-NEXT: xvf32gerpp wacc0, v2, v2
283 ; CHECK-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
284 ; CHECK-NEXT: stxv v4, 48(r3)
285 ; CHECK-NEXT: stxv v5, 32(r3)
286 ; CHECK-NEXT: stxv v2, 16(r3)
287 ; CHECK-NEXT: stxv v3, 0(r3)
288 ; CHECK-NEXT: stxv v4, 112(r3)
289 ; CHECK-NEXT: stxv v5, 96(r3)
290 ; CHECK-NEXT: stxv v2, 80(r3)
291 ; CHECK-NEXT: stxv v3, 64(r3)
292 ; CHECK-NEXT: blr
293 ;
294 ; CHECK-BE-LABEL: testcse:
295 ; CHECK-BE: # %bb.0: # %entry
296 ; CHECK-BE-NEXT: xxsetaccz wacc0
297 ; CHECK-BE-NEXT: xvf32gerpp wacc0, v2, v2
298 ; CHECK-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
299 ; CHECK-BE-NEXT: stxv v5, 48(r3)
300 ; CHECK-BE-NEXT: stxv v4, 32(r3)
301 ; CHECK-BE-NEXT: stxv v3, 16(r3)
302 ; CHECK-BE-NEXT: stxv v2, 0(r3)
303 ; CHECK-BE-NEXT: stxv v5, 112(r3)
304 ; CHECK-BE-NEXT: stxv v4, 96(r3)
305 ; CHECK-BE-NEXT: stxv v3, 80(r3)
306 ; CHECK-BE-NEXT: stxv v2, 64(r3)
307 ; CHECK-BE-NEXT: blr
308 ;
309 ; CHECK-O0-LABEL: testcse:
310 ; CHECK-O0: # %bb.0: # %entry
311 ; CHECK-O0-NEXT: xxsetaccz wacc0
312 ; CHECK-O0-NEXT: xvf32gerpp wacc0, v2, v2
313 ; CHECK-O0-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
314 ; CHECK-O0-NEXT: xxlor vs3, v4, v4
315 ; CHECK-O0-NEXT: stxv vs3, 48(r3)
316 ; CHECK-O0-NEXT: xxlor vs2, v5, v5
317 ; CHECK-O0-NEXT: stxv vs2, 32(r3)
318 ; CHECK-O0-NEXT: xxlor vs1, v2, v2
319 ; CHECK-O0-NEXT: stxv vs1, 16(r3)
320 ; CHECK-O0-NEXT: xxlor vs0, v3, v3
321 ; CHECK-O0-NEXT: stxv vs0, 0(r3)
322 ; CHECK-O0-NEXT: stxv vs3, 112(r3)
323 ; CHECK-O0-NEXT: stxv vs2, 96(r3)
324 ; CHECK-O0-NEXT: stxv vs1, 80(r3)
325 ; CHECK-O0-NEXT: stxv vs0, 64(r3)
326 ; CHECK-O0-NEXT: blr
327 ;
328 ; CHECK-O0-BE-LABEL: testcse:
329 ; CHECK-O0-BE: # %bb.0: # %entry
330 ; CHECK-O0-BE-NEXT: xxsetaccz wacc0
331 ; CHECK-O0-BE-NEXT: xvf32gerpp wacc0, v2, v2
332 ; CHECK-O0-BE-NEXT: dmxxextfdmr512 wacc0, vsp34, vsp36, 0
333 ; CHECK-O0-BE-NEXT: xxlor vs3, v5, v5
334 ; CHECK-O0-BE-NEXT: stxv vs3, 48(r3)
335 ; CHECK-O0-BE-NEXT: xxlor vs2, v4, v4
336 ; CHECK-O0-BE-NEXT: stxv vs2, 32(r3)
337 ; CHECK-O0-BE-NEXT: xxlor vs1, v3, v3
338 ; CHECK-O0-BE-NEXT: stxv vs1, 16(r3)
339 ; CHECK-O0-BE-NEXT: xxlor vs0, v2, v2
340 ; CHECK-O0-BE-NEXT: stxv vs0, 0(r3)
341 ; CHECK-O0-BE-NEXT: stxv vs3, 112(r3)
342 ; CHECK-O0-BE-NEXT: stxv vs2, 96(r3)
343 ; CHECK-O0-BE-NEXT: stxv vs1, 80(r3)
344 ; CHECK-O0-BE-NEXT: stxv vs0, 64(r3)
345 ; CHECK-O0-BE-NEXT: blr
346 ;
347 ; CHECK-AIX64-LABEL: testcse:
348 ; CHECK-AIX64: # %bb.0: # %entry
349 ; CHECK-AIX64-NEXT: xxsetaccz 0
350 ; CHECK-AIX64-NEXT: xvf32gerpp 0, 2, 2
351 ; CHECK-AIX64-NEXT: dmxxextfdmr512 0, 34, 36, 0
352 ; CHECK-AIX64-NEXT: stxv 5, 48(3)
353 ; CHECK-AIX64-NEXT: stxv 4, 32(3)
354 ; CHECK-AIX64-NEXT: stxv 3, 16(3)
355 ; CHECK-AIX64-NEXT: stxv 2, 0(3)
356 ; CHECK-AIX64-NEXT: stxv 5, 112(3)
357 ; CHECK-AIX64-NEXT: stxv 4, 96(3)
358 ; CHECK-AIX64-NEXT: stxv 3, 80(3)
359 ; CHECK-AIX64-NEXT: stxv 2, 64(3)
360 ; CHECK-AIX64-NEXT: blr
361 ;
362 ; CHECK-AIX32-LABEL: testcse:
363 ; CHECK-AIX32: # %bb.0: # %entry
364 ; CHECK-AIX32-NEXT: xxsetaccz 0
365 ; CHECK-AIX32-NEXT: xvf32gerpp 0, 2, 2
366 ; CHECK-AIX32-NEXT: dmxxextfdmr512 0, 34, 36, 0
367 ; CHECK-AIX32-NEXT: stxv 5, 48(3)
368 ; CHECK-AIX32-NEXT: stxv 4, 32(3)
369 ; CHECK-AIX32-NEXT: stxv 3, 16(3)
370 ; CHECK-AIX32-NEXT: stxv 2, 0(3)
371 ; CHECK-AIX32-NEXT: stxv 5, 112(3)
372 ; CHECK-AIX32-NEXT: stxv 4, 96(3)
373 ; CHECK-AIX32-NEXT: stxv 3, 80(3)
374 ; CHECK-AIX32-NEXT: stxv 2, 64(3)
375 ; CHECK-AIX32-NEXT: blr
376 entry:
377 %0 = call <512 x i1> @llvm.ppc.mma.xxsetaccz()
378 %1 = call <512 x i1> @llvm.ppc.mma.xxsetaccz()
379 %2 = call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %0, <16 x i8> %vc, <16 x i8> %vc)
380 %3 = call <512 x i1> @llvm.ppc.mma.xvf32gerpp(<512 x i1> %1, <16 x i8> %vc, <16 x i8> %vc)
381 %4 = getelementptr inbounds <512 x i1>, ptr %res, i64 0
382 %5 = getelementptr inbounds <512 x i1>, ptr %res, i64 1
383 store <512 x i1> %2, ptr %4, align 64
384 store <512 x i1> %3, ptr %5, align 64
385 ret void
386 }