Revert "[LoongArch] Eliminate the redundant sign extension of division (#107971)"
[llvm-project.git] / lldb / test / API / functionalities / gdb_remote_client / TestQemuAArch64TargetXml.py
blob098d912adc123a1257e2b6b8fef9b398d61353b3
1 from lldbsuite.test.lldbtest import *
2 from lldbsuite.test.decorators import *
3 from lldbsuite.test.gdbclientutils import *
4 from textwrap import dedent
5 from lldbsuite.test.lldbgdbclient import GDBRemoteTestBase
8 class MyResponder(MockGDBServerResponder):
9 def qXferRead(self, obj, annex, offset, length):
10 if annex == "target.xml":
11 return (
12 dedent(
13 """\
14 <?xml version="1.0"?>
15 <target version="1.0">
16 <architecture>aarch64</architecture>
17 <feature name="org.gnu.gdb.aarch64.core">
18 <reg name="x0" bitsize="64"/>
19 <reg name="x1" bitsize="64"/>
20 <reg name="x2" bitsize="64"/>
21 <reg name="x3" bitsize="64"/>
22 <reg name="x4" bitsize="64"/>
23 <reg name="x5" bitsize="64"/>
24 <reg name="x6" bitsize="64"/>
25 <reg name="x7" bitsize="64"/>
26 <reg name="x8" bitsize="64"/>
27 <reg name="x9" bitsize="64"/>
28 <reg name="x10" bitsize="64"/>
29 <reg name="x11" bitsize="64"/>
30 <reg name="x12" bitsize="64"/>
31 <reg name="x13" bitsize="64"/>
32 <reg name="x14" bitsize="64"/>
33 <reg name="x15" bitsize="64"/>
34 <reg name="x16" bitsize="64"/>
35 <reg name="x17" bitsize="64"/>
36 <reg name="x18" bitsize="64"/>
37 <reg name="x19" bitsize="64"/>
38 <reg name="x20" bitsize="64"/>
39 <reg name="x21" bitsize="64"/>
40 <reg name="x22" bitsize="64"/>
41 <reg name="x23" bitsize="64"/>
42 <reg name="x24" bitsize="64"/>
43 <reg name="x25" bitsize="64"/>
44 <reg name="x26" bitsize="64"/>
45 <reg name="x27" bitsize="64"/>
46 <reg name="x28" bitsize="64"/>
47 <reg name="x29" bitsize="64"/>
48 <reg name="x30" bitsize="64"/>
49 <reg name="sp" bitsize="64"/>
50 <reg name="pc" bitsize="64"/>
51 </feature>
52 </target>
53 """
55 False,
57 else:
58 return None, False
61 class TestQemuAarch64TargetXml(GDBRemoteTestBase):
62 @skipIfXmlSupportMissing
63 @skipIfRemote
64 @skipIfLLVMTargetMissing("AArch64")
65 def test_register_augmentation(self):
66 """
67 Test that we correctly associate the register info with the eh_frame
68 register numbers.
69 """
71 target = self.createTarget("basic_eh_frame-aarch64.yaml")
72 self.server.responder = MyResponder()
74 process = self.connect(target)
75 lldbutil.expect_state_changes(
76 self, self.dbg.GetListener(), process, [lldb.eStateStopped]
78 self.filecheck("image show-unwind -n foo", __file__, "--check-prefix=UNWIND")
81 # UNWIND: eh_frame UnwindPlan:
82 # UNWIND: row[0]: 0: CFA=x29+16 => x30=[CFA-8]