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[clang] Implement lifetime analysis for lifetime_capture_by(X) (#115921)
[llvm-project.git] / clang / test / CodeGen / SystemZ / zvector.c
blobcbf6a9a1a1bf2ad784b62abdbb00892c978f8d67
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
2 // RUN: %clang_cc1 -triple s390x-linux-gnu -target-cpu z13 -fzvector \
3 // RUN: -emit-llvm -o - -W -Wall -Werror \
4 // RUN: %s | opt -S -passes=mem2reg | FileCheck %s
5
6 volatile vector signed char sc, sc2;
7 volatile vector unsigned char uc, uc2;
8 volatile vector bool char bc, bc2;
9
10 volatile vector signed short ss, ss2;
11 volatile vector unsigned short us, us2;
12 volatile vector bool short bs, bs2;
13
14 volatile vector signed int si, si2;
15 volatile vector unsigned int ui, ui2;
16 volatile vector bool int bi, bi2;
17
18 volatile vector signed long long sl, sl2;
19 volatile vector unsigned long long ul, ul2;
20 volatile vector bool long long bl, bl2;
21
22 volatile vector double fd, fd2;
23
24 volatile int cnt;
25
26 // CHECK-LABEL: define dso_local void @test_assign(
27 // CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
28 // CHECK-NEXT: [[ENTRY:.*:]]
29 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
30 // CHECK-NEXT: store volatile <16 x i8> [[TMP0]], ptr @sc, align 8
31 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
32 // CHECK-NEXT: store volatile <16 x i8> [[TMP1]], ptr @uc, align 8
33 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
34 // CHECK-NEXT: store volatile <8 x i16> [[TMP2]], ptr @ss, align 8
35 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
36 // CHECK-NEXT: store volatile <8 x i16> [[TMP3]], ptr @us, align 8
37 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
38 // CHECK-NEXT: store volatile <4 x i32> [[TMP4]], ptr @si, align 8
39 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
40 // CHECK-NEXT: store volatile <4 x i32> [[TMP5]], ptr @ui, align 8
41 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
42 // CHECK-NEXT: store volatile <2 x i64> [[TMP6]], ptr @sl, align 8
43 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
44 // CHECK-NEXT: store volatile <2 x i64> [[TMP7]], ptr @ul, align 8
45 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <2 x double>, ptr @fd2, align 8
46 // CHECK-NEXT: store volatile <2 x double> [[TMP8]], ptr @fd, align 8
47 // CHECK-NEXT: ret void
48 //
49 void test_assign(void) {
50
51 sc = sc2;
52 uc = uc2;
53
54 ss = ss2;
55 us = us2;
56
57 si = si2;
58 ui = ui2;
59
60 sl = sl2;
61 ul = ul2;
62
63 fd = fd2;
64 }
65
66 // CHECK-LABEL: define dso_local void @test_pos(
67 // CHECK-SAME: ) #[[ATTR0]] {
68 // CHECK-NEXT: [[ENTRY:.*:]]
69 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
70 // CHECK-NEXT: store volatile <16 x i8> [[TMP0]], ptr @sc, align 8
71 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
72 // CHECK-NEXT: store volatile <16 x i8> [[TMP1]], ptr @uc, align 8
73 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
74 // CHECK-NEXT: store volatile <8 x i16> [[TMP2]], ptr @ss, align 8
75 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
76 // CHECK-NEXT: store volatile <8 x i16> [[TMP3]], ptr @us, align 8
77 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
78 // CHECK-NEXT: store volatile <4 x i32> [[TMP4]], ptr @si, align 8
79 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
80 // CHECK-NEXT: store volatile <4 x i32> [[TMP5]], ptr @ui, align 8
81 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
82 // CHECK-NEXT: store volatile <2 x i64> [[TMP6]], ptr @sl, align 8
83 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
84 // CHECK-NEXT: store volatile <2 x i64> [[TMP7]], ptr @ul, align 8
85 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <2 x double>, ptr @fd2, align 8
86 // CHECK-NEXT: store volatile <2 x double> [[TMP8]], ptr @fd, align 8
87 // CHECK-NEXT: ret void
88 //
89 void test_pos(void) {
90
91 sc = +sc2;
92 uc = +uc2;
93
94 ss = +ss2;
95 us = +us2;
96
97 si = +si2;
98 ui = +ui2;
99
100 sl = +sl2;
101 ul = +ul2;
102
103 fd = +fd2;
104 }
105
106 // CHECK-LABEL: define dso_local void @test_neg(
107 // CHECK-SAME: ) #[[ATTR0]] {
108 // CHECK-NEXT: [[ENTRY:.*:]]
109 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
110 // CHECK-NEXT: [[SUB:%.*]] = sub <16 x i8> zeroinitializer, [[TMP0]]
111 // CHECK-NEXT: store volatile <16 x i8> [[SUB]], ptr @sc, align 8
112 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
113 // CHECK-NEXT: [[SUB1:%.*]] = sub <8 x i16> zeroinitializer, [[TMP1]]
114 // CHECK-NEXT: store volatile <8 x i16> [[SUB1]], ptr @ss, align 8
115 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
116 // CHECK-NEXT: [[SUB2:%.*]] = sub <4 x i32> zeroinitializer, [[TMP2]]
117 // CHECK-NEXT: store volatile <4 x i32> [[SUB2]], ptr @si, align 8
118 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
119 // CHECK-NEXT: [[SUB3:%.*]] = sub <2 x i64> zeroinitializer, [[TMP3]]
120 // CHECK-NEXT: store volatile <2 x i64> [[SUB3]], ptr @sl, align 8
121 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <2 x double>, ptr @fd2, align 8
122 // CHECK-NEXT: [[FNEG:%.*]] = fneg <2 x double> [[TMP4]]
123 // CHECK-NEXT: store volatile <2 x double> [[FNEG]], ptr @fd, align 8
124 // CHECK-NEXT: ret void
125 //
126 void test_neg(void) {
127
128 sc = -sc2;
129 ss = -ss2;
130 si = -si2;
131 sl = -sl2;
132 fd = -fd2;
133 }
134
135 // CHECK-LABEL: define dso_local void @test_preinc(
136 // CHECK-SAME: ) #[[ATTR0]] {
137 // CHECK-NEXT: [[ENTRY:.*:]]
138 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
139 // CHECK-NEXT: [[INC:%.*]] = add <16 x i8> [[TMP0]], splat (i8 1)
140 // CHECK-NEXT: store volatile <16 x i8> [[INC]], ptr @sc2, align 8
141 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
142 // CHECK-NEXT: [[INC1:%.*]] = add <16 x i8> [[TMP1]], splat (i8 1)
143 // CHECK-NEXT: store volatile <16 x i8> [[INC1]], ptr @uc2, align 8
144 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
145 // CHECK-NEXT: [[INC2:%.*]] = add <8 x i16> [[TMP2]], splat (i16 1)
146 // CHECK-NEXT: store volatile <8 x i16> [[INC2]], ptr @ss2, align 8
147 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
148 // CHECK-NEXT: [[INC3:%.*]] = add <8 x i16> [[TMP3]], splat (i16 1)
149 // CHECK-NEXT: store volatile <8 x i16> [[INC3]], ptr @us2, align 8
150 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
151 // CHECK-NEXT: [[INC4:%.*]] = add <4 x i32> [[TMP4]], splat (i32 1)
152 // CHECK-NEXT: store volatile <4 x i32> [[INC4]], ptr @si2, align 8
153 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
154 // CHECK-NEXT: [[INC5:%.*]] = add <4 x i32> [[TMP5]], splat (i32 1)
155 // CHECK-NEXT: store volatile <4 x i32> [[INC5]], ptr @ui2, align 8
156 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
157 // CHECK-NEXT: [[INC6:%.*]] = add <2 x i64> [[TMP6]], splat (i64 1)
158 // CHECK-NEXT: store volatile <2 x i64> [[INC6]], ptr @sl2, align 8
159 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
160 // CHECK-NEXT: [[INC7:%.*]] = add <2 x i64> [[TMP7]], splat (i64 1)
161 // CHECK-NEXT: store volatile <2 x i64> [[INC7]], ptr @ul2, align 8
162 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <2 x double>, ptr @fd2, align 8
163 // CHECK-NEXT: [[INC8:%.*]] = fadd <2 x double> [[TMP8]], splat (double 1.000000e+00)
164 // CHECK-NEXT: store volatile <2 x double> [[INC8]], ptr @fd2, align 8
165 // CHECK-NEXT: ret void
166 //
167 void test_preinc(void) {
168
169 ++sc2;
170 ++uc2;
171
172 ++ss2;
173 ++us2;
174
175 ++si2;
176 ++ui2;
177
178 ++sl2;
179 ++ul2;
180
181 ++fd2;
182 }
183
184 // CHECK-LABEL: define dso_local void @test_postinc(
185 // CHECK-SAME: ) #[[ATTR0]] {
186 // CHECK-NEXT: [[ENTRY:.*:]]
187 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
188 // CHECK-NEXT: [[INC:%.*]] = add <16 x i8> [[TMP0]], splat (i8 1)
189 // CHECK-NEXT: store volatile <16 x i8> [[INC]], ptr @sc2, align 8
190 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
191 // CHECK-NEXT: [[INC1:%.*]] = add <16 x i8> [[TMP1]], splat (i8 1)
192 // CHECK-NEXT: store volatile <16 x i8> [[INC1]], ptr @uc2, align 8
193 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
194 // CHECK-NEXT: [[INC2:%.*]] = add <8 x i16> [[TMP2]], splat (i16 1)
195 // CHECK-NEXT: store volatile <8 x i16> [[INC2]], ptr @ss2, align 8
196 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
197 // CHECK-NEXT: [[INC3:%.*]] = add <8 x i16> [[TMP3]], splat (i16 1)
198 // CHECK-NEXT: store volatile <8 x i16> [[INC3]], ptr @us2, align 8
199 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
200 // CHECK-NEXT: [[INC4:%.*]] = add <4 x i32> [[TMP4]], splat (i32 1)
201 // CHECK-NEXT: store volatile <4 x i32> [[INC4]], ptr @si2, align 8
202 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
203 // CHECK-NEXT: [[INC5:%.*]] = add <4 x i32> [[TMP5]], splat (i32 1)
204 // CHECK-NEXT: store volatile <4 x i32> [[INC5]], ptr @ui2, align 8
205 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
206 // CHECK-NEXT: [[INC6:%.*]] = add <2 x i64> [[TMP6]], splat (i64 1)
207 // CHECK-NEXT: store volatile <2 x i64> [[INC6]], ptr @sl2, align 8
208 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
209 // CHECK-NEXT: [[INC7:%.*]] = add <2 x i64> [[TMP7]], splat (i64 1)
210 // CHECK-NEXT: store volatile <2 x i64> [[INC7]], ptr @ul2, align 8
211 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <2 x double>, ptr @fd2, align 8
212 // CHECK-NEXT: [[INC8:%.*]] = fadd <2 x double> [[TMP8]], splat (double 1.000000e+00)
213 // CHECK-NEXT: store volatile <2 x double> [[INC8]], ptr @fd2, align 8
214 // CHECK-NEXT: ret void
215 //
216 void test_postinc(void) {
217
218 sc2++;
219 uc2++;
220
221 ss2++;
222 us2++;
223
224 si2++;
225 ui2++;
226
227 sl2++;
228 ul2++;
229
230 fd2++;
231 }
232
233 // CHECK-LABEL: define dso_local void @test_predec(
234 // CHECK-SAME: ) #[[ATTR0]] {
235 // CHECK-NEXT: [[ENTRY:.*:]]
236 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
237 // CHECK-NEXT: [[DEC:%.*]] = add <16 x i8> [[TMP0]], splat (i8 -1)
238 // CHECK-NEXT: store volatile <16 x i8> [[DEC]], ptr @sc2, align 8
239 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
240 // CHECK-NEXT: [[DEC1:%.*]] = add <16 x i8> [[TMP1]], splat (i8 -1)
241 // CHECK-NEXT: store volatile <16 x i8> [[DEC1]], ptr @uc2, align 8
242 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
243 // CHECK-NEXT: [[DEC2:%.*]] = add <8 x i16> [[TMP2]], splat (i16 -1)
244 // CHECK-NEXT: store volatile <8 x i16> [[DEC2]], ptr @ss2, align 8
245 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
246 // CHECK-NEXT: [[DEC3:%.*]] = add <8 x i16> [[TMP3]], splat (i16 -1)
247 // CHECK-NEXT: store volatile <8 x i16> [[DEC3]], ptr @us2, align 8
248 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
249 // CHECK-NEXT: [[DEC4:%.*]] = add <4 x i32> [[TMP4]], splat (i32 -1)
250 // CHECK-NEXT: store volatile <4 x i32> [[DEC4]], ptr @si2, align 8
251 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
252 // CHECK-NEXT: [[DEC5:%.*]] = add <4 x i32> [[TMP5]], splat (i32 -1)
253 // CHECK-NEXT: store volatile <4 x i32> [[DEC5]], ptr @ui2, align 8
254 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
255 // CHECK-NEXT: [[DEC6:%.*]] = add <2 x i64> [[TMP6]], splat (i64 -1)
256 // CHECK-NEXT: store volatile <2 x i64> [[DEC6]], ptr @sl2, align 8
257 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
258 // CHECK-NEXT: [[DEC7:%.*]] = add <2 x i64> [[TMP7]], splat (i64 -1)
259 // CHECK-NEXT: store volatile <2 x i64> [[DEC7]], ptr @ul2, align 8
260 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <2 x double>, ptr @fd2, align 8
261 // CHECK-NEXT: [[DEC8:%.*]] = fadd <2 x double> [[TMP8]], splat (double -1.000000e+00)
262 // CHECK-NEXT: store volatile <2 x double> [[DEC8]], ptr @fd2, align 8
263 // CHECK-NEXT: ret void
264 //
265 void test_predec(void) {
266
267 --sc2;
268 --uc2;
269
270 --ss2;
271 --us2;
272
273 --si2;
274 --ui2;
275
276 --sl2;
277 --ul2;
278
279 --fd2;
280 }
281
282 // CHECK-LABEL: define dso_local void @test_postdec(
283 // CHECK-SAME: ) #[[ATTR0]] {
284 // CHECK-NEXT: [[ENTRY:.*:]]
285 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
286 // CHECK-NEXT: [[DEC:%.*]] = add <16 x i8> [[TMP0]], splat (i8 -1)
287 // CHECK-NEXT: store volatile <16 x i8> [[DEC]], ptr @sc2, align 8
288 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
289 // CHECK-NEXT: [[DEC1:%.*]] = add <16 x i8> [[TMP1]], splat (i8 -1)
290 // CHECK-NEXT: store volatile <16 x i8> [[DEC1]], ptr @uc2, align 8
291 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
292 // CHECK-NEXT: [[DEC2:%.*]] = add <8 x i16> [[TMP2]], splat (i16 -1)
293 // CHECK-NEXT: store volatile <8 x i16> [[DEC2]], ptr @ss2, align 8
294 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
295 // CHECK-NEXT: [[DEC3:%.*]] = add <8 x i16> [[TMP3]], splat (i16 -1)
296 // CHECK-NEXT: store volatile <8 x i16> [[DEC3]], ptr @us2, align 8
297 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
298 // CHECK-NEXT: [[DEC4:%.*]] = add <4 x i32> [[TMP4]], splat (i32 -1)
299 // CHECK-NEXT: store volatile <4 x i32> [[DEC4]], ptr @si2, align 8
300 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
301 // CHECK-NEXT: [[DEC5:%.*]] = add <4 x i32> [[TMP5]], splat (i32 -1)
302 // CHECK-NEXT: store volatile <4 x i32> [[DEC5]], ptr @ui2, align 8
303 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
304 // CHECK-NEXT: [[DEC6:%.*]] = add <2 x i64> [[TMP6]], splat (i64 -1)
305 // CHECK-NEXT: store volatile <2 x i64> [[DEC6]], ptr @sl2, align 8
306 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
307 // CHECK-NEXT: [[DEC7:%.*]] = add <2 x i64> [[TMP7]], splat (i64 -1)
308 // CHECK-NEXT: store volatile <2 x i64> [[DEC7]], ptr @ul2, align 8
309 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <2 x double>, ptr @fd2, align 8
310 // CHECK-NEXT: [[DEC8:%.*]] = fadd <2 x double> [[TMP8]], splat (double -1.000000e+00)
311 // CHECK-NEXT: store volatile <2 x double> [[DEC8]], ptr @fd2, align 8
312 // CHECK-NEXT: ret void
313 //
314 void test_postdec(void) {
315
316 sc2--;
317 uc2--;
318
319 ss2--;
320 us2--;
321
322 si2--;
323 ui2--;
324
325 sl2--;
326 ul2--;
327
328 fd2--;
329 }
330
331 // CHECK-LABEL: define dso_local void @test_add(
332 // CHECK-SAME: ) #[[ATTR0]] {
333 // CHECK-NEXT: [[ENTRY:.*:]]
334 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
335 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
336 // CHECK-NEXT: [[ADD:%.*]] = add <16 x i8> [[TMP0]], [[TMP1]]
337 // CHECK-NEXT: store volatile <16 x i8> [[ADD]], ptr @sc, align 8
338 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
339 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
340 // CHECK-NEXT: [[ADD1:%.*]] = add <16 x i8> [[TMP2]], [[TMP3]]
341 // CHECK-NEXT: store volatile <16 x i8> [[ADD1]], ptr @sc, align 8
342 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
343 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
344 // CHECK-NEXT: [[ADD2:%.*]] = add <16 x i8> [[TMP4]], [[TMP5]]
345 // CHECK-NEXT: store volatile <16 x i8> [[ADD2]], ptr @sc, align 8
346 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
347 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
348 // CHECK-NEXT: [[ADD3:%.*]] = add <16 x i8> [[TMP6]], [[TMP7]]
349 // CHECK-NEXT: store volatile <16 x i8> [[ADD3]], ptr @uc, align 8
350 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
351 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
352 // CHECK-NEXT: [[ADD4:%.*]] = add <16 x i8> [[TMP8]], [[TMP9]]
353 // CHECK-NEXT: store volatile <16 x i8> [[ADD4]], ptr @uc, align 8
354 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
355 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
356 // CHECK-NEXT: [[ADD5:%.*]] = add <16 x i8> [[TMP10]], [[TMP11]]
357 // CHECK-NEXT: store volatile <16 x i8> [[ADD5]], ptr @uc, align 8
358 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
359 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
360 // CHECK-NEXT: [[ADD6:%.*]] = add <8 x i16> [[TMP12]], [[TMP13]]
361 // CHECK-NEXT: store volatile <8 x i16> [[ADD6]], ptr @ss, align 8
362 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
363 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
364 // CHECK-NEXT: [[ADD7:%.*]] = add <8 x i16> [[TMP14]], [[TMP15]]
365 // CHECK-NEXT: store volatile <8 x i16> [[ADD7]], ptr @ss, align 8
366 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
367 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
368 // CHECK-NEXT: [[ADD8:%.*]] = add <8 x i16> [[TMP16]], [[TMP17]]
369 // CHECK-NEXT: store volatile <8 x i16> [[ADD8]], ptr @ss, align 8
370 // CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @us, align 8
371 // CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
372 // CHECK-NEXT: [[ADD9:%.*]] = add <8 x i16> [[TMP18]], [[TMP19]]
373 // CHECK-NEXT: store volatile <8 x i16> [[ADD9]], ptr @us, align 8
374 // CHECK-NEXT: [[TMP20:%.*]] = load volatile <8 x i16>, ptr @us, align 8
375 // CHECK-NEXT: [[TMP21:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
376 // CHECK-NEXT: [[ADD10:%.*]] = add <8 x i16> [[TMP20]], [[TMP21]]
377 // CHECK-NEXT: store volatile <8 x i16> [[ADD10]], ptr @us, align 8
378 // CHECK-NEXT: [[TMP22:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
379 // CHECK-NEXT: [[TMP23:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
380 // CHECK-NEXT: [[ADD11:%.*]] = add <8 x i16> [[TMP22]], [[TMP23]]
381 // CHECK-NEXT: store volatile <8 x i16> [[ADD11]], ptr @us, align 8
382 // CHECK-NEXT: [[TMP24:%.*]] = load volatile <4 x i32>, ptr @si, align 8
383 // CHECK-NEXT: [[TMP25:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
384 // CHECK-NEXT: [[ADD12:%.*]] = add <4 x i32> [[TMP24]], [[TMP25]]
385 // CHECK-NEXT: store volatile <4 x i32> [[ADD12]], ptr @si, align 8
386 // CHECK-NEXT: [[TMP26:%.*]] = load volatile <4 x i32>, ptr @si, align 8
387 // CHECK-NEXT: [[TMP27:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
388 // CHECK-NEXT: [[ADD13:%.*]] = add <4 x i32> [[TMP26]], [[TMP27]]
389 // CHECK-NEXT: store volatile <4 x i32> [[ADD13]], ptr @si, align 8
390 // CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
391 // CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
392 // CHECK-NEXT: [[ADD14:%.*]] = add <4 x i32> [[TMP28]], [[TMP29]]
393 // CHECK-NEXT: store volatile <4 x i32> [[ADD14]], ptr @si, align 8
394 // CHECK-NEXT: [[TMP30:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
395 // CHECK-NEXT: [[TMP31:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
396 // CHECK-NEXT: [[ADD15:%.*]] = add <4 x i32> [[TMP30]], [[TMP31]]
397 // CHECK-NEXT: store volatile <4 x i32> [[ADD15]], ptr @ui, align 8
398 // CHECK-NEXT: [[TMP32:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
399 // CHECK-NEXT: [[TMP33:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
400 // CHECK-NEXT: [[ADD16:%.*]] = add <4 x i32> [[TMP32]], [[TMP33]]
401 // CHECK-NEXT: store volatile <4 x i32> [[ADD16]], ptr @ui, align 8
402 // CHECK-NEXT: [[TMP34:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
403 // CHECK-NEXT: [[TMP35:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
404 // CHECK-NEXT: [[ADD17:%.*]] = add <4 x i32> [[TMP34]], [[TMP35]]
405 // CHECK-NEXT: store volatile <4 x i32> [[ADD17]], ptr @ui, align 8
406 // CHECK-NEXT: [[TMP36:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
407 // CHECK-NEXT: [[TMP37:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
408 // CHECK-NEXT: [[ADD18:%.*]] = add <2 x i64> [[TMP36]], [[TMP37]]
409 // CHECK-NEXT: store volatile <2 x i64> [[ADD18]], ptr @sl, align 8
410 // CHECK-NEXT: [[TMP38:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
411 // CHECK-NEXT: [[TMP39:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
412 // CHECK-NEXT: [[ADD19:%.*]] = add <2 x i64> [[TMP38]], [[TMP39]]
413 // CHECK-NEXT: store volatile <2 x i64> [[ADD19]], ptr @sl, align 8
414 // CHECK-NEXT: [[TMP40:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
415 // CHECK-NEXT: [[TMP41:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
416 // CHECK-NEXT: [[ADD20:%.*]] = add <2 x i64> [[TMP40]], [[TMP41]]
417 // CHECK-NEXT: store volatile <2 x i64> [[ADD20]], ptr @sl, align 8
418 // CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
419 // CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
420 // CHECK-NEXT: [[ADD21:%.*]] = add <2 x i64> [[TMP42]], [[TMP43]]
421 // CHECK-NEXT: store volatile <2 x i64> [[ADD21]], ptr @ul, align 8
422 // CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
423 // CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
424 // CHECK-NEXT: [[ADD22:%.*]] = add <2 x i64> [[TMP44]], [[TMP45]]
425 // CHECK-NEXT: store volatile <2 x i64> [[ADD22]], ptr @ul, align 8
426 // CHECK-NEXT: [[TMP46:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
427 // CHECK-NEXT: [[TMP47:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
428 // CHECK-NEXT: [[ADD23:%.*]] = add <2 x i64> [[TMP46]], [[TMP47]]
429 // CHECK-NEXT: store volatile <2 x i64> [[ADD23]], ptr @ul, align 8
430 // CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x double>, ptr @fd, align 8
431 // CHECK-NEXT: [[TMP49:%.*]] = load volatile <2 x double>, ptr @fd2, align 8
432 // CHECK-NEXT: [[ADD24:%.*]] = fadd <2 x double> [[TMP48]], [[TMP49]]
433 // CHECK-NEXT: store volatile <2 x double> [[ADD24]], ptr @fd, align 8
434 // CHECK-NEXT: ret void
435 //
436 void test_add(void) {
437
438 sc = sc + sc2;
439 sc = sc + bc2;
440 sc = bc + sc2;
441 uc = uc + uc2;
442 uc = uc + bc2;
443 uc = bc + uc2;
444
445 ss = ss + ss2;
446 ss = ss + bs2;
447 ss = bs + ss2;
448 us = us + us2;
449 us = us + bs2;
450 us = bs + us2;
451
452 si = si + si2;
453 si = si + bi2;
454 si = bi + si2;
455 ui = ui + ui2;
456 ui = ui + bi2;
457 ui = bi + ui2;
458
459 sl = sl + sl2;
460 sl = sl + bl2;
461 sl = bl + sl2;
462 ul = ul + ul2;
463 ul = ul + bl2;
464 ul = bl + ul2;
465
466 fd = fd + fd2;
467 }
468
469 // CHECK-LABEL: define dso_local void @test_add_assign(
470 // CHECK-SAME: ) #[[ATTR0]] {
471 // CHECK-NEXT: [[ENTRY:.*:]]
472 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
473 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
474 // CHECK-NEXT: [[ADD:%.*]] = add <16 x i8> [[TMP1]], [[TMP0]]
475 // CHECK-NEXT: store volatile <16 x i8> [[ADD]], ptr @sc, align 8
476 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
477 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
478 // CHECK-NEXT: [[ADD1:%.*]] = add <16 x i8> [[TMP3]], [[TMP2]]
479 // CHECK-NEXT: store volatile <16 x i8> [[ADD1]], ptr @sc, align 8
480 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
481 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
482 // CHECK-NEXT: [[ADD2:%.*]] = add <16 x i8> [[TMP5]], [[TMP4]]
483 // CHECK-NEXT: store volatile <16 x i8> [[ADD2]], ptr @uc, align 8
484 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
485 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
486 // CHECK-NEXT: [[ADD3:%.*]] = add <16 x i8> [[TMP7]], [[TMP6]]
487 // CHECK-NEXT: store volatile <16 x i8> [[ADD3]], ptr @uc, align 8
488 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
489 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
490 // CHECK-NEXT: [[ADD4:%.*]] = add <8 x i16> [[TMP9]], [[TMP8]]
491 // CHECK-NEXT: store volatile <8 x i16> [[ADD4]], ptr @ss, align 8
492 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
493 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
494 // CHECK-NEXT: [[ADD5:%.*]] = add <8 x i16> [[TMP11]], [[TMP10]]
495 // CHECK-NEXT: store volatile <8 x i16> [[ADD5]], ptr @ss, align 8
496 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
497 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <8 x i16>, ptr @us, align 8
498 // CHECK-NEXT: [[ADD6:%.*]] = add <8 x i16> [[TMP13]], [[TMP12]]
499 // CHECK-NEXT: store volatile <8 x i16> [[ADD6]], ptr @us, align 8
500 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
501 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @us, align 8
502 // CHECK-NEXT: [[ADD7:%.*]] = add <8 x i16> [[TMP15]], [[TMP14]]
503 // CHECK-NEXT: store volatile <8 x i16> [[ADD7]], ptr @us, align 8
504 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
505 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <4 x i32>, ptr @si, align 8
506 // CHECK-NEXT: [[ADD8:%.*]] = add <4 x i32> [[TMP17]], [[TMP16]]
507 // CHECK-NEXT: store volatile <4 x i32> [[ADD8]], ptr @si, align 8
508 // CHECK-NEXT: [[TMP18:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
509 // CHECK-NEXT: [[TMP19:%.*]] = load volatile <4 x i32>, ptr @si, align 8
510 // CHECK-NEXT: [[ADD9:%.*]] = add <4 x i32> [[TMP19]], [[TMP18]]
511 // CHECK-NEXT: store volatile <4 x i32> [[ADD9]], ptr @si, align 8
512 // CHECK-NEXT: [[TMP20:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
513 // CHECK-NEXT: [[TMP21:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
514 // CHECK-NEXT: [[ADD10:%.*]] = add <4 x i32> [[TMP21]], [[TMP20]]
515 // CHECK-NEXT: store volatile <4 x i32> [[ADD10]], ptr @ui, align 8
516 // CHECK-NEXT: [[TMP22:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
517 // CHECK-NEXT: [[TMP23:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
518 // CHECK-NEXT: [[ADD11:%.*]] = add <4 x i32> [[TMP23]], [[TMP22]]
519 // CHECK-NEXT: store volatile <4 x i32> [[ADD11]], ptr @ui, align 8
520 // CHECK-NEXT: [[TMP24:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
521 // CHECK-NEXT: [[TMP25:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
522 // CHECK-NEXT: [[ADD12:%.*]] = add <2 x i64> [[TMP25]], [[TMP24]]
523 // CHECK-NEXT: store volatile <2 x i64> [[ADD12]], ptr @sl, align 8
524 // CHECK-NEXT: [[TMP26:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
525 // CHECK-NEXT: [[TMP27:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
526 // CHECK-NEXT: [[ADD13:%.*]] = add <2 x i64> [[TMP27]], [[TMP26]]
527 // CHECK-NEXT: store volatile <2 x i64> [[ADD13]], ptr @sl, align 8
528 // CHECK-NEXT: [[TMP28:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
529 // CHECK-NEXT: [[TMP29:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
530 // CHECK-NEXT: [[ADD14:%.*]] = add <2 x i64> [[TMP29]], [[TMP28]]
531 // CHECK-NEXT: store volatile <2 x i64> [[ADD14]], ptr @ul, align 8
532 // CHECK-NEXT: [[TMP30:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
533 // CHECK-NEXT: [[TMP31:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
534 // CHECK-NEXT: [[ADD15:%.*]] = add <2 x i64> [[TMP31]], [[TMP30]]
535 // CHECK-NEXT: store volatile <2 x i64> [[ADD15]], ptr @ul, align 8
536 // CHECK-NEXT: [[TMP32:%.*]] = load volatile <2 x double>, ptr @fd2, align 8
537 // CHECK-NEXT: [[TMP33:%.*]] = load volatile <2 x double>, ptr @fd, align 8
538 // CHECK-NEXT: [[ADD16:%.*]] = fadd <2 x double> [[TMP33]], [[TMP32]]
539 // CHECK-NEXT: store volatile <2 x double> [[ADD16]], ptr @fd, align 8
540 // CHECK-NEXT: ret void
541 //
542 void test_add_assign(void) {
543
544 sc += sc2;
545 sc += bc2;
546 uc += uc2;
547 uc += bc2;
548
549 ss += ss2;
550 ss += bs2;
551 us += us2;
552 us += bs2;
553
554 si += si2;
555 si += bi2;
556 ui += ui2;
557 ui += bi2;
558
559 sl += sl2;
560 sl += bl2;
561 ul += ul2;
562 ul += bl2;
563
564 fd += fd2;
565 }
566
567 // CHECK-LABEL: define dso_local void @test_sub(
568 // CHECK-SAME: ) #[[ATTR0]] {
569 // CHECK-NEXT: [[ENTRY:.*:]]
570 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
571 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
572 // CHECK-NEXT: [[SUB:%.*]] = sub <16 x i8> [[TMP0]], [[TMP1]]
573 // CHECK-NEXT: store volatile <16 x i8> [[SUB]], ptr @sc, align 8
574 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
575 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
576 // CHECK-NEXT: [[SUB1:%.*]] = sub <16 x i8> [[TMP2]], [[TMP3]]
577 // CHECK-NEXT: store volatile <16 x i8> [[SUB1]], ptr @sc, align 8
578 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
579 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
580 // CHECK-NEXT: [[SUB2:%.*]] = sub <16 x i8> [[TMP4]], [[TMP5]]
581 // CHECK-NEXT: store volatile <16 x i8> [[SUB2]], ptr @sc, align 8
582 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
583 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
584 // CHECK-NEXT: [[SUB3:%.*]] = sub <16 x i8> [[TMP6]], [[TMP7]]
585 // CHECK-NEXT: store volatile <16 x i8> [[SUB3]], ptr @uc, align 8
586 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
587 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
588 // CHECK-NEXT: [[SUB4:%.*]] = sub <16 x i8> [[TMP8]], [[TMP9]]
589 // CHECK-NEXT: store volatile <16 x i8> [[SUB4]], ptr @uc, align 8
590 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
591 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
592 // CHECK-NEXT: [[SUB5:%.*]] = sub <16 x i8> [[TMP10]], [[TMP11]]
593 // CHECK-NEXT: store volatile <16 x i8> [[SUB5]], ptr @uc, align 8
594 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
595 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
596 // CHECK-NEXT: [[SUB6:%.*]] = sub <8 x i16> [[TMP12]], [[TMP13]]
597 // CHECK-NEXT: store volatile <8 x i16> [[SUB6]], ptr @ss, align 8
598 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
599 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
600 // CHECK-NEXT: [[SUB7:%.*]] = sub <8 x i16> [[TMP14]], [[TMP15]]
601 // CHECK-NEXT: store volatile <8 x i16> [[SUB7]], ptr @ss, align 8
602 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
603 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
604 // CHECK-NEXT: [[SUB8:%.*]] = sub <8 x i16> [[TMP16]], [[TMP17]]
605 // CHECK-NEXT: store volatile <8 x i16> [[SUB8]], ptr @ss, align 8
606 // CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @us, align 8
607 // CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
608 // CHECK-NEXT: [[SUB9:%.*]] = sub <8 x i16> [[TMP18]], [[TMP19]]
609 // CHECK-NEXT: store volatile <8 x i16> [[SUB9]], ptr @us, align 8
610 // CHECK-NEXT: [[TMP20:%.*]] = load volatile <8 x i16>, ptr @us, align 8
611 // CHECK-NEXT: [[TMP21:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
612 // CHECK-NEXT: [[SUB10:%.*]] = sub <8 x i16> [[TMP20]], [[TMP21]]
613 // CHECK-NEXT: store volatile <8 x i16> [[SUB10]], ptr @us, align 8
614 // CHECK-NEXT: [[TMP22:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
615 // CHECK-NEXT: [[TMP23:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
616 // CHECK-NEXT: [[SUB11:%.*]] = sub <8 x i16> [[TMP22]], [[TMP23]]
617 // CHECK-NEXT: store volatile <8 x i16> [[SUB11]], ptr @us, align 8
618 // CHECK-NEXT: [[TMP24:%.*]] = load volatile <4 x i32>, ptr @si, align 8
619 // CHECK-NEXT: [[TMP25:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
620 // CHECK-NEXT: [[SUB12:%.*]] = sub <4 x i32> [[TMP24]], [[TMP25]]
621 // CHECK-NEXT: store volatile <4 x i32> [[SUB12]], ptr @si, align 8
622 // CHECK-NEXT: [[TMP26:%.*]] = load volatile <4 x i32>, ptr @si, align 8
623 // CHECK-NEXT: [[TMP27:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
624 // CHECK-NEXT: [[SUB13:%.*]] = sub <4 x i32> [[TMP26]], [[TMP27]]
625 // CHECK-NEXT: store volatile <4 x i32> [[SUB13]], ptr @si, align 8
626 // CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
627 // CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
628 // CHECK-NEXT: [[SUB14:%.*]] = sub <4 x i32> [[TMP28]], [[TMP29]]
629 // CHECK-NEXT: store volatile <4 x i32> [[SUB14]], ptr @si, align 8
630 // CHECK-NEXT: [[TMP30:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
631 // CHECK-NEXT: [[TMP31:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
632 // CHECK-NEXT: [[SUB15:%.*]] = sub <4 x i32> [[TMP30]], [[TMP31]]
633 // CHECK-NEXT: store volatile <4 x i32> [[SUB15]], ptr @ui, align 8
634 // CHECK-NEXT: [[TMP32:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
635 // CHECK-NEXT: [[TMP33:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
636 // CHECK-NEXT: [[SUB16:%.*]] = sub <4 x i32> [[TMP32]], [[TMP33]]
637 // CHECK-NEXT: store volatile <4 x i32> [[SUB16]], ptr @ui, align 8
638 // CHECK-NEXT: [[TMP34:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
639 // CHECK-NEXT: [[TMP35:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
640 // CHECK-NEXT: [[SUB17:%.*]] = sub <4 x i32> [[TMP34]], [[TMP35]]
641 // CHECK-NEXT: store volatile <4 x i32> [[SUB17]], ptr @ui, align 8
642 // CHECK-NEXT: [[TMP36:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
643 // CHECK-NEXT: [[TMP37:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
644 // CHECK-NEXT: [[SUB18:%.*]] = sub <2 x i64> [[TMP36]], [[TMP37]]
645 // CHECK-NEXT: store volatile <2 x i64> [[SUB18]], ptr @sl, align 8
646 // CHECK-NEXT: [[TMP38:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
647 // CHECK-NEXT: [[TMP39:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
648 // CHECK-NEXT: [[SUB19:%.*]] = sub <2 x i64> [[TMP38]], [[TMP39]]
649 // CHECK-NEXT: store volatile <2 x i64> [[SUB19]], ptr @sl, align 8
650 // CHECK-NEXT: [[TMP40:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
651 // CHECK-NEXT: [[TMP41:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
652 // CHECK-NEXT: [[SUB20:%.*]] = sub <2 x i64> [[TMP40]], [[TMP41]]
653 // CHECK-NEXT: store volatile <2 x i64> [[SUB20]], ptr @sl, align 8
654 // CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
655 // CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
656 // CHECK-NEXT: [[SUB21:%.*]] = sub <2 x i64> [[TMP42]], [[TMP43]]
657 // CHECK-NEXT: store volatile <2 x i64> [[SUB21]], ptr @ul, align 8
658 // CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
659 // CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
660 // CHECK-NEXT: [[SUB22:%.*]] = sub <2 x i64> [[TMP44]], [[TMP45]]
661 // CHECK-NEXT: store volatile <2 x i64> [[SUB22]], ptr @ul, align 8
662 // CHECK-NEXT: [[TMP46:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
663 // CHECK-NEXT: [[TMP47:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
664 // CHECK-NEXT: [[SUB23:%.*]] = sub <2 x i64> [[TMP46]], [[TMP47]]
665 // CHECK-NEXT: store volatile <2 x i64> [[SUB23]], ptr @ul, align 8
666 // CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x double>, ptr @fd, align 8
667 // CHECK-NEXT: [[TMP49:%.*]] = load volatile <2 x double>, ptr @fd2, align 8
668 // CHECK-NEXT: [[SUB24:%.*]] = fsub <2 x double> [[TMP48]], [[TMP49]]
669 // CHECK-NEXT: store volatile <2 x double> [[SUB24]], ptr @fd, align 8
670 // CHECK-NEXT: ret void
671 //
672 void test_sub(void) {
673
674 sc = sc - sc2;
675 sc = sc - bc2;
676 sc = bc - sc2;
677 uc = uc - uc2;
678 uc = uc - bc2;
679 uc = bc - uc2;
680
681 ss = ss - ss2;
682 ss = ss - bs2;
683 ss = bs - ss2;
684 us = us - us2;
685 us = us - bs2;
686 us = bs - us2;
687
688 si = si - si2;
689 si = si - bi2;
690 si = bi - si2;
691 ui = ui - ui2;
692 ui = ui - bi2;
693 ui = bi - ui2;
694
695 sl = sl - sl2;
696 sl = sl - bl2;
697 sl = bl - sl2;
698 ul = ul - ul2;
699 ul = ul - bl2;
700 ul = bl - ul2;
701
702 fd = fd - fd2;
703 }
704
705 // CHECK-LABEL: define dso_local void @test_sub_assign(
706 // CHECK-SAME: ) #[[ATTR0]] {
707 // CHECK-NEXT: [[ENTRY:.*:]]
708 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
709 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
710 // CHECK-NEXT: [[SUB:%.*]] = sub <16 x i8> [[TMP1]], [[TMP0]]
711 // CHECK-NEXT: store volatile <16 x i8> [[SUB]], ptr @sc, align 8
712 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
713 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
714 // CHECK-NEXT: [[SUB1:%.*]] = sub <16 x i8> [[TMP3]], [[TMP2]]
715 // CHECK-NEXT: store volatile <16 x i8> [[SUB1]], ptr @sc, align 8
716 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
717 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
718 // CHECK-NEXT: [[SUB2:%.*]] = sub <16 x i8> [[TMP5]], [[TMP4]]
719 // CHECK-NEXT: store volatile <16 x i8> [[SUB2]], ptr @uc, align 8
720 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
721 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
722 // CHECK-NEXT: [[SUB3:%.*]] = sub <16 x i8> [[TMP7]], [[TMP6]]
723 // CHECK-NEXT: store volatile <16 x i8> [[SUB3]], ptr @uc, align 8
724 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
725 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
726 // CHECK-NEXT: [[SUB4:%.*]] = sub <8 x i16> [[TMP9]], [[TMP8]]
727 // CHECK-NEXT: store volatile <8 x i16> [[SUB4]], ptr @ss, align 8
728 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
729 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
730 // CHECK-NEXT: [[SUB5:%.*]] = sub <8 x i16> [[TMP11]], [[TMP10]]
731 // CHECK-NEXT: store volatile <8 x i16> [[SUB5]], ptr @ss, align 8
732 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
733 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <8 x i16>, ptr @us, align 8
734 // CHECK-NEXT: [[SUB6:%.*]] = sub <8 x i16> [[TMP13]], [[TMP12]]
735 // CHECK-NEXT: store volatile <8 x i16> [[SUB6]], ptr @us, align 8
736 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
737 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @us, align 8
738 // CHECK-NEXT: [[SUB7:%.*]] = sub <8 x i16> [[TMP15]], [[TMP14]]
739 // CHECK-NEXT: store volatile <8 x i16> [[SUB7]], ptr @us, align 8
740 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
741 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <4 x i32>, ptr @si, align 8
742 // CHECK-NEXT: [[SUB8:%.*]] = sub <4 x i32> [[TMP17]], [[TMP16]]
743 // CHECK-NEXT: store volatile <4 x i32> [[SUB8]], ptr @si, align 8
744 // CHECK-NEXT: [[TMP18:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
745 // CHECK-NEXT: [[TMP19:%.*]] = load volatile <4 x i32>, ptr @si, align 8
746 // CHECK-NEXT: [[SUB9:%.*]] = sub <4 x i32> [[TMP19]], [[TMP18]]
747 // CHECK-NEXT: store volatile <4 x i32> [[SUB9]], ptr @si, align 8
748 // CHECK-NEXT: [[TMP20:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
749 // CHECK-NEXT: [[TMP21:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
750 // CHECK-NEXT: [[SUB10:%.*]] = sub <4 x i32> [[TMP21]], [[TMP20]]
751 // CHECK-NEXT: store volatile <4 x i32> [[SUB10]], ptr @ui, align 8
752 // CHECK-NEXT: [[TMP22:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
753 // CHECK-NEXT: [[TMP23:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
754 // CHECK-NEXT: [[SUB11:%.*]] = sub <4 x i32> [[TMP23]], [[TMP22]]
755 // CHECK-NEXT: store volatile <4 x i32> [[SUB11]], ptr @ui, align 8
756 // CHECK-NEXT: [[TMP24:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
757 // CHECK-NEXT: [[TMP25:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
758 // CHECK-NEXT: [[SUB12:%.*]] = sub <2 x i64> [[TMP25]], [[TMP24]]
759 // CHECK-NEXT: store volatile <2 x i64> [[SUB12]], ptr @sl, align 8
760 // CHECK-NEXT: [[TMP26:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
761 // CHECK-NEXT: [[TMP27:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
762 // CHECK-NEXT: [[SUB13:%.*]] = sub <2 x i64> [[TMP27]], [[TMP26]]
763 // CHECK-NEXT: store volatile <2 x i64> [[SUB13]], ptr @sl, align 8
764 // CHECK-NEXT: [[TMP28:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
765 // CHECK-NEXT: [[TMP29:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
766 // CHECK-NEXT: [[SUB14:%.*]] = sub <2 x i64> [[TMP29]], [[TMP28]]
767 // CHECK-NEXT: store volatile <2 x i64> [[SUB14]], ptr @ul, align 8
768 // CHECK-NEXT: [[TMP30:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
769 // CHECK-NEXT: [[TMP31:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
770 // CHECK-NEXT: [[SUB15:%.*]] = sub <2 x i64> [[TMP31]], [[TMP30]]
771 // CHECK-NEXT: store volatile <2 x i64> [[SUB15]], ptr @ul, align 8
772 // CHECK-NEXT: [[TMP32:%.*]] = load volatile <2 x double>, ptr @fd2, align 8
773 // CHECK-NEXT: [[TMP33:%.*]] = load volatile <2 x double>, ptr @fd, align 8
774 // CHECK-NEXT: [[SUB16:%.*]] = fsub <2 x double> [[TMP33]], [[TMP32]]
775 // CHECK-NEXT: store volatile <2 x double> [[SUB16]], ptr @fd, align 8
776 // CHECK-NEXT: ret void
777 //
778 void test_sub_assign(void) {
779
780 sc -= sc2;
781 sc -= bc2;
782 uc -= uc2;
783 uc -= bc2;
784
785 ss -= ss2;
786 ss -= bs2;
787 us -= us2;
788 us -= bs2;
789
790 si -= si2;
791 si -= bi2;
792 ui -= ui2;
793 ui -= bi2;
794
795 sl -= sl2;
796 sl -= bl2;
797 ul -= ul2;
798 ul -= bl2;
799
800 fd -= fd2;
801 }
802
803 // CHECK-LABEL: define dso_local void @test_mul(
804 // CHECK-SAME: ) #[[ATTR0]] {
805 // CHECK-NEXT: [[ENTRY:.*:]]
806 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
807 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
808 // CHECK-NEXT: [[MUL:%.*]] = mul <16 x i8> [[TMP0]], [[TMP1]]
809 // CHECK-NEXT: store volatile <16 x i8> [[MUL]], ptr @sc, align 8
810 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
811 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
812 // CHECK-NEXT: [[MUL1:%.*]] = mul <16 x i8> [[TMP2]], [[TMP3]]
813 // CHECK-NEXT: store volatile <16 x i8> [[MUL1]], ptr @uc, align 8
814 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
815 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
816 // CHECK-NEXT: [[MUL2:%.*]] = mul <8 x i16> [[TMP4]], [[TMP5]]
817 // CHECK-NEXT: store volatile <8 x i16> [[MUL2]], ptr @ss, align 8
818 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <8 x i16>, ptr @us, align 8
819 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
820 // CHECK-NEXT: [[MUL3:%.*]] = mul <8 x i16> [[TMP6]], [[TMP7]]
821 // CHECK-NEXT: store volatile <8 x i16> [[MUL3]], ptr @us, align 8
822 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <4 x i32>, ptr @si, align 8
823 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
824 // CHECK-NEXT: [[MUL4:%.*]] = mul <4 x i32> [[TMP8]], [[TMP9]]
825 // CHECK-NEXT: store volatile <4 x i32> [[MUL4]], ptr @si, align 8
826 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
827 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
828 // CHECK-NEXT: [[MUL5:%.*]] = mul <4 x i32> [[TMP10]], [[TMP11]]
829 // CHECK-NEXT: store volatile <4 x i32> [[MUL5]], ptr @ui, align 8
830 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
831 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
832 // CHECK-NEXT: [[MUL6:%.*]] = mul <2 x i64> [[TMP12]], [[TMP13]]
833 // CHECK-NEXT: store volatile <2 x i64> [[MUL6]], ptr @sl, align 8
834 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
835 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
836 // CHECK-NEXT: [[MUL7:%.*]] = mul <2 x i64> [[TMP14]], [[TMP15]]
837 // CHECK-NEXT: store volatile <2 x i64> [[MUL7]], ptr @ul, align 8
838 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <2 x double>, ptr @fd, align 8
839 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <2 x double>, ptr @fd2, align 8
840 // CHECK-NEXT: [[MUL8:%.*]] = fmul <2 x double> [[TMP16]], [[TMP17]]
841 // CHECK-NEXT: store volatile <2 x double> [[MUL8]], ptr @fd, align 8
842 // CHECK-NEXT: ret void
843 //
844 void test_mul(void) {
845
846 sc = sc * sc2;
847 uc = uc * uc2;
848
849 ss = ss * ss2;
850 us = us * us2;
851
852 si = si * si2;
853 ui = ui * ui2;
854
855 sl = sl * sl2;
856 ul = ul * ul2;
857
858 fd = fd * fd2;
859 }
860
861 // CHECK-LABEL: define dso_local void @test_mul_assign(
862 // CHECK-SAME: ) #[[ATTR0]] {
863 // CHECK-NEXT: [[ENTRY:.*:]]
864 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
865 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
866 // CHECK-NEXT: [[MUL:%.*]] = mul <16 x i8> [[TMP1]], [[TMP0]]
867 // CHECK-NEXT: store volatile <16 x i8> [[MUL]], ptr @sc, align 8
868 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
869 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
870 // CHECK-NEXT: [[MUL1:%.*]] = mul <16 x i8> [[TMP3]], [[TMP2]]
871 // CHECK-NEXT: store volatile <16 x i8> [[MUL1]], ptr @uc, align 8
872 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
873 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
874 // CHECK-NEXT: [[MUL2:%.*]] = mul <8 x i16> [[TMP5]], [[TMP4]]
875 // CHECK-NEXT: store volatile <8 x i16> [[MUL2]], ptr @ss, align 8
876 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
877 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <8 x i16>, ptr @us, align 8
878 // CHECK-NEXT: [[MUL3:%.*]] = mul <8 x i16> [[TMP7]], [[TMP6]]
879 // CHECK-NEXT: store volatile <8 x i16> [[MUL3]], ptr @us, align 8
880 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
881 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <4 x i32>, ptr @si, align 8
882 // CHECK-NEXT: [[MUL4:%.*]] = mul <4 x i32> [[TMP9]], [[TMP8]]
883 // CHECK-NEXT: store volatile <4 x i32> [[MUL4]], ptr @si, align 8
884 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
885 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
886 // CHECK-NEXT: [[MUL5:%.*]] = mul <4 x i32> [[TMP11]], [[TMP10]]
887 // CHECK-NEXT: store volatile <4 x i32> [[MUL5]], ptr @ui, align 8
888 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
889 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
890 // CHECK-NEXT: [[MUL6:%.*]] = mul <2 x i64> [[TMP13]], [[TMP12]]
891 // CHECK-NEXT: store volatile <2 x i64> [[MUL6]], ptr @sl, align 8
892 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
893 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
894 // CHECK-NEXT: [[MUL7:%.*]] = mul <2 x i64> [[TMP15]], [[TMP14]]
895 // CHECK-NEXT: store volatile <2 x i64> [[MUL7]], ptr @ul, align 8
896 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <2 x double>, ptr @fd2, align 8
897 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <2 x double>, ptr @fd, align 8
898 // CHECK-NEXT: [[MUL8:%.*]] = fmul <2 x double> [[TMP17]], [[TMP16]]
899 // CHECK-NEXT: store volatile <2 x double> [[MUL8]], ptr @fd, align 8
900 // CHECK-NEXT: ret void
901 //
902 void test_mul_assign(void) {
903
904 sc *= sc2;
905 uc *= uc2;
906
907 ss *= ss2;
908 us *= us2;
909
910 si *= si2;
911 ui *= ui2;
912
913 sl *= sl2;
914 ul *= ul2;
915
916 fd *= fd2;
917 }
918
919 // CHECK-LABEL: define dso_local void @test_div(
920 // CHECK-SAME: ) #[[ATTR0]] {
921 // CHECK-NEXT: [[ENTRY:.*:]]
922 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
923 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
924 // CHECK-NEXT: [[DIV:%.*]] = sdiv <16 x i8> [[TMP0]], [[TMP1]]
925 // CHECK-NEXT: store volatile <16 x i8> [[DIV]], ptr @sc, align 8
926 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
927 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
928 // CHECK-NEXT: [[DIV1:%.*]] = udiv <16 x i8> [[TMP2]], [[TMP3]]
929 // CHECK-NEXT: store volatile <16 x i8> [[DIV1]], ptr @uc, align 8
930 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
931 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
932 // CHECK-NEXT: [[DIV2:%.*]] = sdiv <8 x i16> [[TMP4]], [[TMP5]]
933 // CHECK-NEXT: store volatile <8 x i16> [[DIV2]], ptr @ss, align 8
934 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <8 x i16>, ptr @us, align 8
935 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
936 // CHECK-NEXT: [[DIV3:%.*]] = udiv <8 x i16> [[TMP6]], [[TMP7]]
937 // CHECK-NEXT: store volatile <8 x i16> [[DIV3]], ptr @us, align 8
938 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <4 x i32>, ptr @si, align 8
939 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
940 // CHECK-NEXT: [[DIV4:%.*]] = sdiv <4 x i32> [[TMP8]], [[TMP9]]
941 // CHECK-NEXT: store volatile <4 x i32> [[DIV4]], ptr @si, align 8
942 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
943 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
944 // CHECK-NEXT: [[DIV5:%.*]] = udiv <4 x i32> [[TMP10]], [[TMP11]]
945 // CHECK-NEXT: store volatile <4 x i32> [[DIV5]], ptr @ui, align 8
946 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
947 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
948 // CHECK-NEXT: [[DIV6:%.*]] = sdiv <2 x i64> [[TMP12]], [[TMP13]]
949 // CHECK-NEXT: store volatile <2 x i64> [[DIV6]], ptr @sl, align 8
950 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
951 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
952 // CHECK-NEXT: [[DIV7:%.*]] = udiv <2 x i64> [[TMP14]], [[TMP15]]
953 // CHECK-NEXT: store volatile <2 x i64> [[DIV7]], ptr @ul, align 8
954 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <2 x double>, ptr @fd, align 8
955 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <2 x double>, ptr @fd2, align 8
956 // CHECK-NEXT: [[DIV8:%.*]] = fdiv <2 x double> [[TMP16]], [[TMP17]]
957 // CHECK-NEXT: store volatile <2 x double> [[DIV8]], ptr @fd, align 8
958 // CHECK-NEXT: ret void
959 //
960 void test_div(void) {
961
962 sc = sc / sc2;
963 uc = uc / uc2;
964
965 ss = ss / ss2;
966 us = us / us2;
967
968 si = si / si2;
969 ui = ui / ui2;
970
971 sl = sl / sl2;
972 ul = ul / ul2;
973
974 fd = fd / fd2;
975 }
976
977 // CHECK-LABEL: define dso_local void @test_div_assign(
978 // CHECK-SAME: ) #[[ATTR0]] {
979 // CHECK-NEXT: [[ENTRY:.*:]]
980 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
981 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
982 // CHECK-NEXT: [[DIV:%.*]] = sdiv <16 x i8> [[TMP1]], [[TMP0]]
983 // CHECK-NEXT: store volatile <16 x i8> [[DIV]], ptr @sc, align 8
984 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
985 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
986 // CHECK-NEXT: [[DIV1:%.*]] = udiv <16 x i8> [[TMP3]], [[TMP2]]
987 // CHECK-NEXT: store volatile <16 x i8> [[DIV1]], ptr @uc, align 8
988 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
989 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
990 // CHECK-NEXT: [[DIV2:%.*]] = sdiv <8 x i16> [[TMP5]], [[TMP4]]
991 // CHECK-NEXT: store volatile <8 x i16> [[DIV2]], ptr @ss, align 8
992 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
993 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <8 x i16>, ptr @us, align 8
994 // CHECK-NEXT: [[DIV3:%.*]] = udiv <8 x i16> [[TMP7]], [[TMP6]]
995 // CHECK-NEXT: store volatile <8 x i16> [[DIV3]], ptr @us, align 8
996 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
997 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <4 x i32>, ptr @si, align 8
998 // CHECK-NEXT: [[DIV4:%.*]] = sdiv <4 x i32> [[TMP9]], [[TMP8]]
999 // CHECK-NEXT: store volatile <4 x i32> [[DIV4]], ptr @si, align 8
1000 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
1001 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
1002 // CHECK-NEXT: [[DIV5:%.*]] = udiv <4 x i32> [[TMP11]], [[TMP10]]
1003 // CHECK-NEXT: store volatile <4 x i32> [[DIV5]], ptr @ui, align 8
1004 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
1005 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1006 // CHECK-NEXT: [[DIV6:%.*]] = sdiv <2 x i64> [[TMP13]], [[TMP12]]
1007 // CHECK-NEXT: store volatile <2 x i64> [[DIV6]], ptr @sl, align 8
1008 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
1009 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
1010 // CHECK-NEXT: [[DIV7:%.*]] = udiv <2 x i64> [[TMP15]], [[TMP14]]
1011 // CHECK-NEXT: store volatile <2 x i64> [[DIV7]], ptr @ul, align 8
1012 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <2 x double>, ptr @fd2, align 8
1013 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <2 x double>, ptr @fd, align 8
1014 // CHECK-NEXT: [[DIV8:%.*]] = fdiv <2 x double> [[TMP17]], [[TMP16]]
1015 // CHECK-NEXT: store volatile <2 x double> [[DIV8]], ptr @fd, align 8
1016 // CHECK-NEXT: ret void
1017 //
1018 void test_div_assign(void) {
1019
1020 sc /= sc2;
1021 uc /= uc2;
1022
1023 ss /= ss2;
1024 us /= us2;
1025
1026 si /= si2;
1027 ui /= ui2;
1028
1029 sl /= sl2;
1030 ul /= ul2;
1031
1032 fd /= fd2;
1033 }
1034
1035 // CHECK-LABEL: define dso_local void @test_rem(
1036 // CHECK-SAME: ) #[[ATTR0]] {
1037 // CHECK-NEXT: [[ENTRY:.*:]]
1038 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
1039 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
1040 // CHECK-NEXT: [[REM:%.*]] = srem <16 x i8> [[TMP0]], [[TMP1]]
1041 // CHECK-NEXT: store volatile <16 x i8> [[REM]], ptr @sc, align 8
1042 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
1043 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
1044 // CHECK-NEXT: [[REM1:%.*]] = urem <16 x i8> [[TMP2]], [[TMP3]]
1045 // CHECK-NEXT: store volatile <16 x i8> [[REM1]], ptr @uc, align 8
1046 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
1047 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
1048 // CHECK-NEXT: [[REM2:%.*]] = srem <8 x i16> [[TMP4]], [[TMP5]]
1049 // CHECK-NEXT: store volatile <8 x i16> [[REM2]], ptr @ss, align 8
1050 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <8 x i16>, ptr @us, align 8
1051 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
1052 // CHECK-NEXT: [[REM3:%.*]] = urem <8 x i16> [[TMP6]], [[TMP7]]
1053 // CHECK-NEXT: store volatile <8 x i16> [[REM3]], ptr @us, align 8
1054 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <4 x i32>, ptr @si, align 8
1055 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
1056 // CHECK-NEXT: [[REM4:%.*]] = srem <4 x i32> [[TMP8]], [[TMP9]]
1057 // CHECK-NEXT: store volatile <4 x i32> [[REM4]], ptr @si, align 8
1058 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
1059 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
1060 // CHECK-NEXT: [[REM5:%.*]] = urem <4 x i32> [[TMP10]], [[TMP11]]
1061 // CHECK-NEXT: store volatile <4 x i32> [[REM5]], ptr @ui, align 8
1062 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1063 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
1064 // CHECK-NEXT: [[REM6:%.*]] = srem <2 x i64> [[TMP12]], [[TMP13]]
1065 // CHECK-NEXT: store volatile <2 x i64> [[REM6]], ptr @sl, align 8
1066 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
1067 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
1068 // CHECK-NEXT: [[REM7:%.*]] = urem <2 x i64> [[TMP14]], [[TMP15]]
1069 // CHECK-NEXT: store volatile <2 x i64> [[REM7]], ptr @ul, align 8
1070 // CHECK-NEXT: ret void
1071 //
1072 void test_rem(void) {
1073
1074 sc = sc % sc2;
1075 uc = uc % uc2;
1076
1077 ss = ss % ss2;
1078 us = us % us2;
1079
1080 si = si % si2;
1081 ui = ui % ui2;
1082
1083 sl = sl % sl2;
1084 ul = ul % ul2;
1085 }
1086
1087 // CHECK-LABEL: define dso_local void @test_rem_assign(
1088 // CHECK-SAME: ) #[[ATTR0]] {
1089 // CHECK-NEXT: [[ENTRY:.*:]]
1090 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
1091 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
1092 // CHECK-NEXT: [[REM:%.*]] = srem <16 x i8> [[TMP1]], [[TMP0]]
1093 // CHECK-NEXT: store volatile <16 x i8> [[REM]], ptr @sc, align 8
1094 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
1095 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
1096 // CHECK-NEXT: [[REM1:%.*]] = urem <16 x i8> [[TMP3]], [[TMP2]]
1097 // CHECK-NEXT: store volatile <16 x i8> [[REM1]], ptr @uc, align 8
1098 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
1099 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
1100 // CHECK-NEXT: [[REM2:%.*]] = srem <8 x i16> [[TMP5]], [[TMP4]]
1101 // CHECK-NEXT: store volatile <8 x i16> [[REM2]], ptr @ss, align 8
1102 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
1103 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <8 x i16>, ptr @us, align 8
1104 // CHECK-NEXT: [[REM3:%.*]] = urem <8 x i16> [[TMP7]], [[TMP6]]
1105 // CHECK-NEXT: store volatile <8 x i16> [[REM3]], ptr @us, align 8
1106 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
1107 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <4 x i32>, ptr @si, align 8
1108 // CHECK-NEXT: [[REM4:%.*]] = srem <4 x i32> [[TMP9]], [[TMP8]]
1109 // CHECK-NEXT: store volatile <4 x i32> [[REM4]], ptr @si, align 8
1110 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
1111 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
1112 // CHECK-NEXT: [[REM5:%.*]] = urem <4 x i32> [[TMP11]], [[TMP10]]
1113 // CHECK-NEXT: store volatile <4 x i32> [[REM5]], ptr @ui, align 8
1114 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
1115 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1116 // CHECK-NEXT: [[REM6:%.*]] = srem <2 x i64> [[TMP13]], [[TMP12]]
1117 // CHECK-NEXT: store volatile <2 x i64> [[REM6]], ptr @sl, align 8
1118 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
1119 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
1120 // CHECK-NEXT: [[REM7:%.*]] = urem <2 x i64> [[TMP15]], [[TMP14]]
1121 // CHECK-NEXT: store volatile <2 x i64> [[REM7]], ptr @ul, align 8
1122 // CHECK-NEXT: ret void
1123 //
1124 void test_rem_assign(void) {
1125
1126 sc %= sc2;
1127 uc %= uc2;
1128
1129 ss %= ss2;
1130 us %= us2;
1131
1132 si %= si2;
1133 ui %= ui2;
1134
1135 sl %= sl2;
1136 ul %= ul2;
1137 }
1138
1139 // CHECK-LABEL: define dso_local void @test_not(
1140 // CHECK-SAME: ) #[[ATTR0]] {
1141 // CHECK-NEXT: [[ENTRY:.*:]]
1142 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
1143 // CHECK-NEXT: [[NOT:%.*]] = xor <16 x i8> [[TMP0]], splat (i8 -1)
1144 // CHECK-NEXT: store volatile <16 x i8> [[NOT]], ptr @sc, align 8
1145 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
1146 // CHECK-NEXT: [[NOT1:%.*]] = xor <16 x i8> [[TMP1]], splat (i8 -1)
1147 // CHECK-NEXT: store volatile <16 x i8> [[NOT1]], ptr @uc, align 8
1148 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
1149 // CHECK-NEXT: [[NOT2:%.*]] = xor <16 x i8> [[TMP2]], splat (i8 -1)
1150 // CHECK-NEXT: store volatile <16 x i8> [[NOT2]], ptr @bc, align 8
1151 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
1152 // CHECK-NEXT: [[NOT3:%.*]] = xor <8 x i16> [[TMP3]], splat (i16 -1)
1153 // CHECK-NEXT: store volatile <8 x i16> [[NOT3]], ptr @ss, align 8
1154 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
1155 // CHECK-NEXT: [[NOT4:%.*]] = xor <8 x i16> [[TMP4]], splat (i16 -1)
1156 // CHECK-NEXT: store volatile <8 x i16> [[NOT4]], ptr @us, align 8
1157 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
1158 // CHECK-NEXT: [[NOT5:%.*]] = xor <8 x i16> [[TMP5]], splat (i16 -1)
1159 // CHECK-NEXT: store volatile <8 x i16> [[NOT5]], ptr @bs, align 8
1160 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
1161 // CHECK-NEXT: [[NOT6:%.*]] = xor <4 x i32> [[TMP6]], splat (i32 -1)
1162 // CHECK-NEXT: store volatile <4 x i32> [[NOT6]], ptr @si, align 8
1163 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
1164 // CHECK-NEXT: [[NOT7:%.*]] = xor <4 x i32> [[TMP7]], splat (i32 -1)
1165 // CHECK-NEXT: store volatile <4 x i32> [[NOT7]], ptr @ui, align 8
1166 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
1167 // CHECK-NEXT: [[NOT8:%.*]] = xor <4 x i32> [[TMP8]], splat (i32 -1)
1168 // CHECK-NEXT: store volatile <4 x i32> [[NOT8]], ptr @bi, align 8
1169 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
1170 // CHECK-NEXT: [[NOT9:%.*]] = xor <2 x i64> [[TMP9]], splat (i64 -1)
1171 // CHECK-NEXT: store volatile <2 x i64> [[NOT9]], ptr @sl, align 8
1172 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
1173 // CHECK-NEXT: [[NOT10:%.*]] = xor <2 x i64> [[TMP10]], splat (i64 -1)
1174 // CHECK-NEXT: store volatile <2 x i64> [[NOT10]], ptr @ul, align 8
1175 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
1176 // CHECK-NEXT: [[NOT11:%.*]] = xor <2 x i64> [[TMP11]], splat (i64 -1)
1177 // CHECK-NEXT: store volatile <2 x i64> [[NOT11]], ptr @bl, align 8
1178 // CHECK-NEXT: ret void
1179 //
1180 void test_not(void) {
1181
1182 sc = ~sc2;
1183 uc = ~uc2;
1184 bc = ~bc2;
1185
1186 ss = ~ss2;
1187 us = ~us2;
1188 bs = ~bs2;
1189
1190 si = ~si2;
1191 ui = ~ui2;
1192 bi = ~bi2;
1193
1194 sl = ~sl2;
1195 ul = ~ul2;
1196 bl = ~bl2;
1197 }
1198
1199 // CHECK-LABEL: define dso_local void @test_and(
1200 // CHECK-SAME: ) #[[ATTR0]] {
1201 // CHECK-NEXT: [[ENTRY:.*:]]
1202 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
1203 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
1204 // CHECK-NEXT: [[AND:%.*]] = and <16 x i8> [[TMP0]], [[TMP1]]
1205 // CHECK-NEXT: store volatile <16 x i8> [[AND]], ptr @sc, align 8
1206 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
1207 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
1208 // CHECK-NEXT: [[AND1:%.*]] = and <16 x i8> [[TMP2]], [[TMP3]]
1209 // CHECK-NEXT: store volatile <16 x i8> [[AND1]], ptr @sc, align 8
1210 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
1211 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
1212 // CHECK-NEXT: [[AND2:%.*]] = and <16 x i8> [[TMP4]], [[TMP5]]
1213 // CHECK-NEXT: store volatile <16 x i8> [[AND2]], ptr @sc, align 8
1214 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
1215 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
1216 // CHECK-NEXT: [[AND3:%.*]] = and <16 x i8> [[TMP6]], [[TMP7]]
1217 // CHECK-NEXT: store volatile <16 x i8> [[AND3]], ptr @uc, align 8
1218 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
1219 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
1220 // CHECK-NEXT: [[AND4:%.*]] = and <16 x i8> [[TMP8]], [[TMP9]]
1221 // CHECK-NEXT: store volatile <16 x i8> [[AND4]], ptr @uc, align 8
1222 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
1223 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
1224 // CHECK-NEXT: [[AND5:%.*]] = and <16 x i8> [[TMP10]], [[TMP11]]
1225 // CHECK-NEXT: store volatile <16 x i8> [[AND5]], ptr @uc, align 8
1226 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
1227 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
1228 // CHECK-NEXT: [[AND6:%.*]] = and <16 x i8> [[TMP12]], [[TMP13]]
1229 // CHECK-NEXT: store volatile <16 x i8> [[AND6]], ptr @bc, align 8
1230 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
1231 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
1232 // CHECK-NEXT: [[AND7:%.*]] = and <8 x i16> [[TMP14]], [[TMP15]]
1233 // CHECK-NEXT: store volatile <8 x i16> [[AND7]], ptr @ss, align 8
1234 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
1235 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
1236 // CHECK-NEXT: [[AND8:%.*]] = and <8 x i16> [[TMP16]], [[TMP17]]
1237 // CHECK-NEXT: store volatile <8 x i16> [[AND8]], ptr @ss, align 8
1238 // CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
1239 // CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
1240 // CHECK-NEXT: [[AND9:%.*]] = and <8 x i16> [[TMP18]], [[TMP19]]
1241 // CHECK-NEXT: store volatile <8 x i16> [[AND9]], ptr @ss, align 8
1242 // CHECK-NEXT: [[TMP20:%.*]] = load volatile <8 x i16>, ptr @us, align 8
1243 // CHECK-NEXT: [[TMP21:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
1244 // CHECK-NEXT: [[AND10:%.*]] = and <8 x i16> [[TMP20]], [[TMP21]]
1245 // CHECK-NEXT: store volatile <8 x i16> [[AND10]], ptr @us, align 8
1246 // CHECK-NEXT: [[TMP22:%.*]] = load volatile <8 x i16>, ptr @us, align 8
1247 // CHECK-NEXT: [[TMP23:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
1248 // CHECK-NEXT: [[AND11:%.*]] = and <8 x i16> [[TMP22]], [[TMP23]]
1249 // CHECK-NEXT: store volatile <8 x i16> [[AND11]], ptr @us, align 8
1250 // CHECK-NEXT: [[TMP24:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
1251 // CHECK-NEXT: [[TMP25:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
1252 // CHECK-NEXT: [[AND12:%.*]] = and <8 x i16> [[TMP24]], [[TMP25]]
1253 // CHECK-NEXT: store volatile <8 x i16> [[AND12]], ptr @us, align 8
1254 // CHECK-NEXT: [[TMP26:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
1255 // CHECK-NEXT: [[TMP27:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
1256 // CHECK-NEXT: [[AND13:%.*]] = and <8 x i16> [[TMP26]], [[TMP27]]
1257 // CHECK-NEXT: store volatile <8 x i16> [[AND13]], ptr @bs, align 8
1258 // CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @si, align 8
1259 // CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
1260 // CHECK-NEXT: [[AND14:%.*]] = and <4 x i32> [[TMP28]], [[TMP29]]
1261 // CHECK-NEXT: store volatile <4 x i32> [[AND14]], ptr @si, align 8
1262 // CHECK-NEXT: [[TMP30:%.*]] = load volatile <4 x i32>, ptr @si, align 8
1263 // CHECK-NEXT: [[TMP31:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
1264 // CHECK-NEXT: [[AND15:%.*]] = and <4 x i32> [[TMP30]], [[TMP31]]
1265 // CHECK-NEXT: store volatile <4 x i32> [[AND15]], ptr @si, align 8
1266 // CHECK-NEXT: [[TMP32:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
1267 // CHECK-NEXT: [[TMP33:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
1268 // CHECK-NEXT: [[AND16:%.*]] = and <4 x i32> [[TMP32]], [[TMP33]]
1269 // CHECK-NEXT: store volatile <4 x i32> [[AND16]], ptr @si, align 8
1270 // CHECK-NEXT: [[TMP34:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
1271 // CHECK-NEXT: [[TMP35:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
1272 // CHECK-NEXT: [[AND17:%.*]] = and <4 x i32> [[TMP34]], [[TMP35]]
1273 // CHECK-NEXT: store volatile <4 x i32> [[AND17]], ptr @ui, align 8
1274 // CHECK-NEXT: [[TMP36:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
1275 // CHECK-NEXT: [[TMP37:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
1276 // CHECK-NEXT: [[AND18:%.*]] = and <4 x i32> [[TMP36]], [[TMP37]]
1277 // CHECK-NEXT: store volatile <4 x i32> [[AND18]], ptr @ui, align 8
1278 // CHECK-NEXT: [[TMP38:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
1279 // CHECK-NEXT: [[TMP39:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
1280 // CHECK-NEXT: [[AND19:%.*]] = and <4 x i32> [[TMP38]], [[TMP39]]
1281 // CHECK-NEXT: store volatile <4 x i32> [[AND19]], ptr @ui, align 8
1282 // CHECK-NEXT: [[TMP40:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
1283 // CHECK-NEXT: [[TMP41:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
1284 // CHECK-NEXT: [[AND20:%.*]] = and <4 x i32> [[TMP40]], [[TMP41]]
1285 // CHECK-NEXT: store volatile <4 x i32> [[AND20]], ptr @bi, align 8
1286 // CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1287 // CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
1288 // CHECK-NEXT: [[AND21:%.*]] = and <2 x i64> [[TMP42]], [[TMP43]]
1289 // CHECK-NEXT: store volatile <2 x i64> [[AND21]], ptr @sl, align 8
1290 // CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1291 // CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
1292 // CHECK-NEXT: [[AND22:%.*]] = and <2 x i64> [[TMP44]], [[TMP45]]
1293 // CHECK-NEXT: store volatile <2 x i64> [[AND22]], ptr @sl, align 8
1294 // CHECK-NEXT: [[TMP46:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
1295 // CHECK-NEXT: [[TMP47:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
1296 // CHECK-NEXT: [[AND23:%.*]] = and <2 x i64> [[TMP46]], [[TMP47]]
1297 // CHECK-NEXT: store volatile <2 x i64> [[AND23]], ptr @sl, align 8
1298 // CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
1299 // CHECK-NEXT: [[TMP49:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
1300 // CHECK-NEXT: [[AND24:%.*]] = and <2 x i64> [[TMP48]], [[TMP49]]
1301 // CHECK-NEXT: store volatile <2 x i64> [[AND24]], ptr @ul, align 8
1302 // CHECK-NEXT: [[TMP50:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
1303 // CHECK-NEXT: [[TMP51:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
1304 // CHECK-NEXT: [[AND25:%.*]] = and <2 x i64> [[TMP50]], [[TMP51]]
1305 // CHECK-NEXT: store volatile <2 x i64> [[AND25]], ptr @ul, align 8
1306 // CHECK-NEXT: [[TMP52:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
1307 // CHECK-NEXT: [[TMP53:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
1308 // CHECK-NEXT: [[AND26:%.*]] = and <2 x i64> [[TMP52]], [[TMP53]]
1309 // CHECK-NEXT: store volatile <2 x i64> [[AND26]], ptr @ul, align 8
1310 // CHECK-NEXT: [[TMP54:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
1311 // CHECK-NEXT: [[TMP55:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
1312 // CHECK-NEXT: [[AND27:%.*]] = and <2 x i64> [[TMP54]], [[TMP55]]
1313 // CHECK-NEXT: store volatile <2 x i64> [[AND27]], ptr @bl, align 8
1314 // CHECK-NEXT: ret void
1315 //
1316 void test_and(void) {
1317
1318 sc = sc & sc2;
1319 sc = sc & bc2;
1320 sc = bc & sc2;
1321 uc = uc & uc2;
1322 uc = uc & bc2;
1323 uc = bc & uc2;
1324 bc = bc & bc2;
1325
1326 ss = ss & ss2;
1327 ss = ss & bs2;
1328 ss = bs & ss2;
1329 us = us & us2;
1330 us = us & bs2;
1331 us = bs & us2;
1332 bs = bs & bs2;
1333
1334 si = si & si2;
1335 si = si & bi2;
1336 si = bi & si2;
1337 ui = ui & ui2;
1338 ui = ui & bi2;
1339 ui = bi & ui2;
1340 bi = bi & bi2;
1341
1342 sl = sl & sl2;
1343 sl = sl & bl2;
1344 sl = bl & sl2;
1345 ul = ul & ul2;
1346 ul = ul & bl2;
1347 ul = bl & ul2;
1348 bl = bl & bl2;
1349 }
1350
1351 // CHECK-LABEL: define dso_local void @test_and_assign(
1352 // CHECK-SAME: ) #[[ATTR0]] {
1353 // CHECK-NEXT: [[ENTRY:.*:]]
1354 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
1355 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
1356 // CHECK-NEXT: [[AND:%.*]] = and <16 x i8> [[TMP1]], [[TMP0]]
1357 // CHECK-NEXT: store volatile <16 x i8> [[AND]], ptr @sc, align 8
1358 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
1359 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
1360 // CHECK-NEXT: [[AND1:%.*]] = and <16 x i8> [[TMP3]], [[TMP2]]
1361 // CHECK-NEXT: store volatile <16 x i8> [[AND1]], ptr @sc, align 8
1362 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
1363 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
1364 // CHECK-NEXT: [[AND2:%.*]] = and <16 x i8> [[TMP5]], [[TMP4]]
1365 // CHECK-NEXT: store volatile <16 x i8> [[AND2]], ptr @uc, align 8
1366 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
1367 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
1368 // CHECK-NEXT: [[AND3:%.*]] = and <16 x i8> [[TMP7]], [[TMP6]]
1369 // CHECK-NEXT: store volatile <16 x i8> [[AND3]], ptr @uc, align 8
1370 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
1371 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
1372 // CHECK-NEXT: [[AND4:%.*]] = and <16 x i8> [[TMP9]], [[TMP8]]
1373 // CHECK-NEXT: store volatile <16 x i8> [[AND4]], ptr @bc, align 8
1374 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
1375 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
1376 // CHECK-NEXT: [[AND5:%.*]] = and <8 x i16> [[TMP11]], [[TMP10]]
1377 // CHECK-NEXT: store volatile <8 x i16> [[AND5]], ptr @ss, align 8
1378 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
1379 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
1380 // CHECK-NEXT: [[AND6:%.*]] = and <8 x i16> [[TMP13]], [[TMP12]]
1381 // CHECK-NEXT: store volatile <8 x i16> [[AND6]], ptr @ss, align 8
1382 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
1383 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @us, align 8
1384 // CHECK-NEXT: [[AND7:%.*]] = and <8 x i16> [[TMP15]], [[TMP14]]
1385 // CHECK-NEXT: store volatile <8 x i16> [[AND7]], ptr @us, align 8
1386 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
1387 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @us, align 8
1388 // CHECK-NEXT: [[AND8:%.*]] = and <8 x i16> [[TMP17]], [[TMP16]]
1389 // CHECK-NEXT: store volatile <8 x i16> [[AND8]], ptr @us, align 8
1390 // CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
1391 // CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
1392 // CHECK-NEXT: [[AND9:%.*]] = and <8 x i16> [[TMP19]], [[TMP18]]
1393 // CHECK-NEXT: store volatile <8 x i16> [[AND9]], ptr @bs, align 8
1394 // CHECK-NEXT: [[TMP20:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
1395 // CHECK-NEXT: [[TMP21:%.*]] = load volatile <4 x i32>, ptr @si, align 8
1396 // CHECK-NEXT: [[AND10:%.*]] = and <4 x i32> [[TMP21]], [[TMP20]]
1397 // CHECK-NEXT: store volatile <4 x i32> [[AND10]], ptr @si, align 8
1398 // CHECK-NEXT: [[TMP22:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
1399 // CHECK-NEXT: [[TMP23:%.*]] = load volatile <4 x i32>, ptr @si, align 8
1400 // CHECK-NEXT: [[AND11:%.*]] = and <4 x i32> [[TMP23]], [[TMP22]]
1401 // CHECK-NEXT: store volatile <4 x i32> [[AND11]], ptr @si, align 8
1402 // CHECK-NEXT: [[TMP24:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
1403 // CHECK-NEXT: [[TMP25:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
1404 // CHECK-NEXT: [[AND12:%.*]] = and <4 x i32> [[TMP25]], [[TMP24]]
1405 // CHECK-NEXT: store volatile <4 x i32> [[AND12]], ptr @ui, align 8
1406 // CHECK-NEXT: [[TMP26:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
1407 // CHECK-NEXT: [[TMP27:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
1408 // CHECK-NEXT: [[AND13:%.*]] = and <4 x i32> [[TMP27]], [[TMP26]]
1409 // CHECK-NEXT: store volatile <4 x i32> [[AND13]], ptr @ui, align 8
1410 // CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
1411 // CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
1412 // CHECK-NEXT: [[AND14:%.*]] = and <4 x i32> [[TMP29]], [[TMP28]]
1413 // CHECK-NEXT: store volatile <4 x i32> [[AND14]], ptr @bi, align 8
1414 // CHECK-NEXT: [[TMP30:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
1415 // CHECK-NEXT: [[TMP31:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1416 // CHECK-NEXT: [[AND15:%.*]] = and <2 x i64> [[TMP31]], [[TMP30]]
1417 // CHECK-NEXT: store volatile <2 x i64> [[AND15]], ptr @sl, align 8
1418 // CHECK-NEXT: [[TMP32:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
1419 // CHECK-NEXT: [[TMP33:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1420 // CHECK-NEXT: [[AND16:%.*]] = and <2 x i64> [[TMP33]], [[TMP32]]
1421 // CHECK-NEXT: store volatile <2 x i64> [[AND16]], ptr @sl, align 8
1422 // CHECK-NEXT: [[TMP34:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
1423 // CHECK-NEXT: [[TMP35:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
1424 // CHECK-NEXT: [[AND17:%.*]] = and <2 x i64> [[TMP35]], [[TMP34]]
1425 // CHECK-NEXT: store volatile <2 x i64> [[AND17]], ptr @ul, align 8
1426 // CHECK-NEXT: [[TMP36:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
1427 // CHECK-NEXT: [[TMP37:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
1428 // CHECK-NEXT: [[AND18:%.*]] = and <2 x i64> [[TMP37]], [[TMP36]]
1429 // CHECK-NEXT: store volatile <2 x i64> [[AND18]], ptr @ul, align 8
1430 // CHECK-NEXT: [[TMP38:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
1431 // CHECK-NEXT: [[TMP39:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
1432 // CHECK-NEXT: [[AND19:%.*]] = and <2 x i64> [[TMP39]], [[TMP38]]
1433 // CHECK-NEXT: store volatile <2 x i64> [[AND19]], ptr @bl, align 8
1434 // CHECK-NEXT: ret void
1435 //
1436 void test_and_assign(void) {
1437
1438 sc &= sc2;
1439 sc &= bc2;
1440 uc &= uc2;
1441 uc &= bc2;
1442 bc &= bc2;
1443
1444 ss &= ss2;
1445 ss &= bs2;
1446 us &= us2;
1447 us &= bs2;
1448 bs &= bs2;
1449
1450 si &= si2;
1451 si &= bi2;
1452 ui &= ui2;
1453 ui &= bi2;
1454 bi &= bi2;
1455
1456 sl &= sl2;
1457 sl &= bl2;
1458 ul &= ul2;
1459 ul &= bl2;
1460 bl &= bl2;
1461 }
1462
1463 // CHECK-LABEL: define dso_local void @test_or(
1464 // CHECK-SAME: ) #[[ATTR0]] {
1465 // CHECK-NEXT: [[ENTRY:.*:]]
1466 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
1467 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
1468 // CHECK-NEXT: [[OR:%.*]] = or <16 x i8> [[TMP0]], [[TMP1]]
1469 // CHECK-NEXT: store volatile <16 x i8> [[OR]], ptr @sc, align 8
1470 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
1471 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
1472 // CHECK-NEXT: [[OR1:%.*]] = or <16 x i8> [[TMP2]], [[TMP3]]
1473 // CHECK-NEXT: store volatile <16 x i8> [[OR1]], ptr @sc, align 8
1474 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
1475 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
1476 // CHECK-NEXT: [[OR2:%.*]] = or <16 x i8> [[TMP4]], [[TMP5]]
1477 // CHECK-NEXT: store volatile <16 x i8> [[OR2]], ptr @sc, align 8
1478 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
1479 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
1480 // CHECK-NEXT: [[OR3:%.*]] = or <16 x i8> [[TMP6]], [[TMP7]]
1481 // CHECK-NEXT: store volatile <16 x i8> [[OR3]], ptr @uc, align 8
1482 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
1483 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
1484 // CHECK-NEXT: [[OR4:%.*]] = or <16 x i8> [[TMP8]], [[TMP9]]
1485 // CHECK-NEXT: store volatile <16 x i8> [[OR4]], ptr @uc, align 8
1486 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
1487 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
1488 // CHECK-NEXT: [[OR5:%.*]] = or <16 x i8> [[TMP10]], [[TMP11]]
1489 // CHECK-NEXT: store volatile <16 x i8> [[OR5]], ptr @uc, align 8
1490 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
1491 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
1492 // CHECK-NEXT: [[OR6:%.*]] = or <16 x i8> [[TMP12]], [[TMP13]]
1493 // CHECK-NEXT: store volatile <16 x i8> [[OR6]], ptr @bc, align 8
1494 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
1495 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
1496 // CHECK-NEXT: [[OR7:%.*]] = or <8 x i16> [[TMP14]], [[TMP15]]
1497 // CHECK-NEXT: store volatile <8 x i16> [[OR7]], ptr @ss, align 8
1498 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
1499 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
1500 // CHECK-NEXT: [[OR8:%.*]] = or <8 x i16> [[TMP16]], [[TMP17]]
1501 // CHECK-NEXT: store volatile <8 x i16> [[OR8]], ptr @ss, align 8
1502 // CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
1503 // CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
1504 // CHECK-NEXT: [[OR9:%.*]] = or <8 x i16> [[TMP18]], [[TMP19]]
1505 // CHECK-NEXT: store volatile <8 x i16> [[OR9]], ptr @ss, align 8
1506 // CHECK-NEXT: [[TMP20:%.*]] = load volatile <8 x i16>, ptr @us, align 8
1507 // CHECK-NEXT: [[TMP21:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
1508 // CHECK-NEXT: [[OR10:%.*]] = or <8 x i16> [[TMP20]], [[TMP21]]
1509 // CHECK-NEXT: store volatile <8 x i16> [[OR10]], ptr @us, align 8
1510 // CHECK-NEXT: [[TMP22:%.*]] = load volatile <8 x i16>, ptr @us, align 8
1511 // CHECK-NEXT: [[TMP23:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
1512 // CHECK-NEXT: [[OR11:%.*]] = or <8 x i16> [[TMP22]], [[TMP23]]
1513 // CHECK-NEXT: store volatile <8 x i16> [[OR11]], ptr @us, align 8
1514 // CHECK-NEXT: [[TMP24:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
1515 // CHECK-NEXT: [[TMP25:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
1516 // CHECK-NEXT: [[OR12:%.*]] = or <8 x i16> [[TMP24]], [[TMP25]]
1517 // CHECK-NEXT: store volatile <8 x i16> [[OR12]], ptr @us, align 8
1518 // CHECK-NEXT: [[TMP26:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
1519 // CHECK-NEXT: [[TMP27:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
1520 // CHECK-NEXT: [[OR13:%.*]] = or <8 x i16> [[TMP26]], [[TMP27]]
1521 // CHECK-NEXT: store volatile <8 x i16> [[OR13]], ptr @bs, align 8
1522 // CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @si, align 8
1523 // CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
1524 // CHECK-NEXT: [[OR14:%.*]] = or <4 x i32> [[TMP28]], [[TMP29]]
1525 // CHECK-NEXT: store volatile <4 x i32> [[OR14]], ptr @si, align 8
1526 // CHECK-NEXT: [[TMP30:%.*]] = load volatile <4 x i32>, ptr @si, align 8
1527 // CHECK-NEXT: [[TMP31:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
1528 // CHECK-NEXT: [[OR15:%.*]] = or <4 x i32> [[TMP30]], [[TMP31]]
1529 // CHECK-NEXT: store volatile <4 x i32> [[OR15]], ptr @si, align 8
1530 // CHECK-NEXT: [[TMP32:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
1531 // CHECK-NEXT: [[TMP33:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
1532 // CHECK-NEXT: [[OR16:%.*]] = or <4 x i32> [[TMP32]], [[TMP33]]
1533 // CHECK-NEXT: store volatile <4 x i32> [[OR16]], ptr @si, align 8
1534 // CHECK-NEXT: [[TMP34:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
1535 // CHECK-NEXT: [[TMP35:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
1536 // CHECK-NEXT: [[OR17:%.*]] = or <4 x i32> [[TMP34]], [[TMP35]]
1537 // CHECK-NEXT: store volatile <4 x i32> [[OR17]], ptr @ui, align 8
1538 // CHECK-NEXT: [[TMP36:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
1539 // CHECK-NEXT: [[TMP37:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
1540 // CHECK-NEXT: [[OR18:%.*]] = or <4 x i32> [[TMP36]], [[TMP37]]
1541 // CHECK-NEXT: store volatile <4 x i32> [[OR18]], ptr @ui, align 8
1542 // CHECK-NEXT: [[TMP38:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
1543 // CHECK-NEXT: [[TMP39:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
1544 // CHECK-NEXT: [[OR19:%.*]] = or <4 x i32> [[TMP38]], [[TMP39]]
1545 // CHECK-NEXT: store volatile <4 x i32> [[OR19]], ptr @ui, align 8
1546 // CHECK-NEXT: [[TMP40:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
1547 // CHECK-NEXT: [[TMP41:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
1548 // CHECK-NEXT: [[OR20:%.*]] = or <4 x i32> [[TMP40]], [[TMP41]]
1549 // CHECK-NEXT: store volatile <4 x i32> [[OR20]], ptr @bi, align 8
1550 // CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1551 // CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
1552 // CHECK-NEXT: [[OR21:%.*]] = or <2 x i64> [[TMP42]], [[TMP43]]
1553 // CHECK-NEXT: store volatile <2 x i64> [[OR21]], ptr @sl, align 8
1554 // CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1555 // CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
1556 // CHECK-NEXT: [[OR22:%.*]] = or <2 x i64> [[TMP44]], [[TMP45]]
1557 // CHECK-NEXT: store volatile <2 x i64> [[OR22]], ptr @sl, align 8
1558 // CHECK-NEXT: [[TMP46:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
1559 // CHECK-NEXT: [[TMP47:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
1560 // CHECK-NEXT: [[OR23:%.*]] = or <2 x i64> [[TMP46]], [[TMP47]]
1561 // CHECK-NEXT: store volatile <2 x i64> [[OR23]], ptr @sl, align 8
1562 // CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
1563 // CHECK-NEXT: [[TMP49:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
1564 // CHECK-NEXT: [[OR24:%.*]] = or <2 x i64> [[TMP48]], [[TMP49]]
1565 // CHECK-NEXT: store volatile <2 x i64> [[OR24]], ptr @ul, align 8
1566 // CHECK-NEXT: [[TMP50:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
1567 // CHECK-NEXT: [[TMP51:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
1568 // CHECK-NEXT: [[OR25:%.*]] = or <2 x i64> [[TMP50]], [[TMP51]]
1569 // CHECK-NEXT: store volatile <2 x i64> [[OR25]], ptr @ul, align 8
1570 // CHECK-NEXT: [[TMP52:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
1571 // CHECK-NEXT: [[TMP53:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
1572 // CHECK-NEXT: [[OR26:%.*]] = or <2 x i64> [[TMP52]], [[TMP53]]
1573 // CHECK-NEXT: store volatile <2 x i64> [[OR26]], ptr @ul, align 8
1574 // CHECK-NEXT: [[TMP54:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
1575 // CHECK-NEXT: [[TMP55:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
1576 // CHECK-NEXT: [[OR27:%.*]] = or <2 x i64> [[TMP54]], [[TMP55]]
1577 // CHECK-NEXT: store volatile <2 x i64> [[OR27]], ptr @bl, align 8
1578 // CHECK-NEXT: ret void
1579 //
1580 void test_or(void) {
1581
1582 sc = sc | sc2;
1583 sc = sc | bc2;
1584 sc = bc | sc2;
1585 uc = uc | uc2;
1586 uc = uc | bc2;
1587 uc = bc | uc2;
1588 bc = bc | bc2;
1589
1590 ss = ss | ss2;
1591 ss = ss | bs2;
1592 ss = bs | ss2;
1593 us = us | us2;
1594 us = us | bs2;
1595 us = bs | us2;
1596 bs = bs | bs2;
1597
1598 si = si | si2;
1599 si = si | bi2;
1600 si = bi | si2;
1601 ui = ui | ui2;
1602 ui = ui | bi2;
1603 ui = bi | ui2;
1604 bi = bi | bi2;
1605
1606 sl = sl | sl2;
1607 sl = sl | bl2;
1608 sl = bl | sl2;
1609 ul = ul | ul2;
1610 ul = ul | bl2;
1611 ul = bl | ul2;
1612 bl = bl | bl2;
1613 }
1614
1615 // CHECK-LABEL: define dso_local void @test_or_assign(
1616 // CHECK-SAME: ) #[[ATTR0]] {
1617 // CHECK-NEXT: [[ENTRY:.*:]]
1618 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
1619 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
1620 // CHECK-NEXT: [[OR:%.*]] = or <16 x i8> [[TMP1]], [[TMP0]]
1621 // CHECK-NEXT: store volatile <16 x i8> [[OR]], ptr @sc, align 8
1622 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
1623 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
1624 // CHECK-NEXT: [[OR1:%.*]] = or <16 x i8> [[TMP3]], [[TMP2]]
1625 // CHECK-NEXT: store volatile <16 x i8> [[OR1]], ptr @sc, align 8
1626 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
1627 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
1628 // CHECK-NEXT: [[OR2:%.*]] = or <16 x i8> [[TMP5]], [[TMP4]]
1629 // CHECK-NEXT: store volatile <16 x i8> [[OR2]], ptr @uc, align 8
1630 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
1631 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
1632 // CHECK-NEXT: [[OR3:%.*]] = or <16 x i8> [[TMP7]], [[TMP6]]
1633 // CHECK-NEXT: store volatile <16 x i8> [[OR3]], ptr @uc, align 8
1634 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
1635 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
1636 // CHECK-NEXT: [[OR4:%.*]] = or <16 x i8> [[TMP9]], [[TMP8]]
1637 // CHECK-NEXT: store volatile <16 x i8> [[OR4]], ptr @bc, align 8
1638 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
1639 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
1640 // CHECK-NEXT: [[OR5:%.*]] = or <8 x i16> [[TMP11]], [[TMP10]]
1641 // CHECK-NEXT: store volatile <8 x i16> [[OR5]], ptr @ss, align 8
1642 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
1643 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
1644 // CHECK-NEXT: [[OR6:%.*]] = or <8 x i16> [[TMP13]], [[TMP12]]
1645 // CHECK-NEXT: store volatile <8 x i16> [[OR6]], ptr @ss, align 8
1646 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
1647 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @us, align 8
1648 // CHECK-NEXT: [[OR7:%.*]] = or <8 x i16> [[TMP15]], [[TMP14]]
1649 // CHECK-NEXT: store volatile <8 x i16> [[OR7]], ptr @us, align 8
1650 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
1651 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @us, align 8
1652 // CHECK-NEXT: [[OR8:%.*]] = or <8 x i16> [[TMP17]], [[TMP16]]
1653 // CHECK-NEXT: store volatile <8 x i16> [[OR8]], ptr @us, align 8
1654 // CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
1655 // CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
1656 // CHECK-NEXT: [[OR9:%.*]] = or <8 x i16> [[TMP19]], [[TMP18]]
1657 // CHECK-NEXT: store volatile <8 x i16> [[OR9]], ptr @bs, align 8
1658 // CHECK-NEXT: [[TMP20:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
1659 // CHECK-NEXT: [[TMP21:%.*]] = load volatile <4 x i32>, ptr @si, align 8
1660 // CHECK-NEXT: [[OR10:%.*]] = or <4 x i32> [[TMP21]], [[TMP20]]
1661 // CHECK-NEXT: store volatile <4 x i32> [[OR10]], ptr @si, align 8
1662 // CHECK-NEXT: [[TMP22:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
1663 // CHECK-NEXT: [[TMP23:%.*]] = load volatile <4 x i32>, ptr @si, align 8
1664 // CHECK-NEXT: [[OR11:%.*]] = or <4 x i32> [[TMP23]], [[TMP22]]
1665 // CHECK-NEXT: store volatile <4 x i32> [[OR11]], ptr @si, align 8
1666 // CHECK-NEXT: [[TMP24:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
1667 // CHECK-NEXT: [[TMP25:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
1668 // CHECK-NEXT: [[OR12:%.*]] = or <4 x i32> [[TMP25]], [[TMP24]]
1669 // CHECK-NEXT: store volatile <4 x i32> [[OR12]], ptr @ui, align 8
1670 // CHECK-NEXT: [[TMP26:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
1671 // CHECK-NEXT: [[TMP27:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
1672 // CHECK-NEXT: [[OR13:%.*]] = or <4 x i32> [[TMP27]], [[TMP26]]
1673 // CHECK-NEXT: store volatile <4 x i32> [[OR13]], ptr @ui, align 8
1674 // CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
1675 // CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
1676 // CHECK-NEXT: [[OR14:%.*]] = or <4 x i32> [[TMP29]], [[TMP28]]
1677 // CHECK-NEXT: store volatile <4 x i32> [[OR14]], ptr @bi, align 8
1678 // CHECK-NEXT: [[TMP30:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
1679 // CHECK-NEXT: [[TMP31:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1680 // CHECK-NEXT: [[OR15:%.*]] = or <2 x i64> [[TMP31]], [[TMP30]]
1681 // CHECK-NEXT: store volatile <2 x i64> [[OR15]], ptr @sl, align 8
1682 // CHECK-NEXT: [[TMP32:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
1683 // CHECK-NEXT: [[TMP33:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1684 // CHECK-NEXT: [[OR16:%.*]] = or <2 x i64> [[TMP33]], [[TMP32]]
1685 // CHECK-NEXT: store volatile <2 x i64> [[OR16]], ptr @sl, align 8
1686 // CHECK-NEXT: [[TMP34:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
1687 // CHECK-NEXT: [[TMP35:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
1688 // CHECK-NEXT: [[OR17:%.*]] = or <2 x i64> [[TMP35]], [[TMP34]]
1689 // CHECK-NEXT: store volatile <2 x i64> [[OR17]], ptr @ul, align 8
1690 // CHECK-NEXT: [[TMP36:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
1691 // CHECK-NEXT: [[TMP37:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
1692 // CHECK-NEXT: [[OR18:%.*]] = or <2 x i64> [[TMP37]], [[TMP36]]
1693 // CHECK-NEXT: store volatile <2 x i64> [[OR18]], ptr @ul, align 8
1694 // CHECK-NEXT: [[TMP38:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
1695 // CHECK-NEXT: [[TMP39:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
1696 // CHECK-NEXT: [[OR19:%.*]] = or <2 x i64> [[TMP39]], [[TMP38]]
1697 // CHECK-NEXT: store volatile <2 x i64> [[OR19]], ptr @bl, align 8
1698 // CHECK-NEXT: ret void
1699 //
1700 void test_or_assign(void) {
1701
1702 sc |= sc2;
1703 sc |= bc2;
1704 uc |= uc2;
1705 uc |= bc2;
1706 bc |= bc2;
1707
1708 ss |= ss2;
1709 ss |= bs2;
1710 us |= us2;
1711 us |= bs2;
1712 bs |= bs2;
1713
1714 si |= si2;
1715 si |= bi2;
1716 ui |= ui2;
1717 ui |= bi2;
1718 bi |= bi2;
1719
1720 sl |= sl2;
1721 sl |= bl2;
1722 ul |= ul2;
1723 ul |= bl2;
1724 bl |= bl2;
1725 }
1726
1727 // CHECK-LABEL: define dso_local void @test_xor(
1728 // CHECK-SAME: ) #[[ATTR0]] {
1729 // CHECK-NEXT: [[ENTRY:.*:]]
1730 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
1731 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
1732 // CHECK-NEXT: [[XOR:%.*]] = xor <16 x i8> [[TMP0]], [[TMP1]]
1733 // CHECK-NEXT: store volatile <16 x i8> [[XOR]], ptr @sc, align 8
1734 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
1735 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
1736 // CHECK-NEXT: [[XOR1:%.*]] = xor <16 x i8> [[TMP2]], [[TMP3]]
1737 // CHECK-NEXT: store volatile <16 x i8> [[XOR1]], ptr @sc, align 8
1738 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
1739 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
1740 // CHECK-NEXT: [[XOR2:%.*]] = xor <16 x i8> [[TMP4]], [[TMP5]]
1741 // CHECK-NEXT: store volatile <16 x i8> [[XOR2]], ptr @sc, align 8
1742 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
1743 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
1744 // CHECK-NEXT: [[XOR3:%.*]] = xor <16 x i8> [[TMP6]], [[TMP7]]
1745 // CHECK-NEXT: store volatile <16 x i8> [[XOR3]], ptr @uc, align 8
1746 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
1747 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
1748 // CHECK-NEXT: [[XOR4:%.*]] = xor <16 x i8> [[TMP8]], [[TMP9]]
1749 // CHECK-NEXT: store volatile <16 x i8> [[XOR4]], ptr @uc, align 8
1750 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
1751 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
1752 // CHECK-NEXT: [[XOR5:%.*]] = xor <16 x i8> [[TMP10]], [[TMP11]]
1753 // CHECK-NEXT: store volatile <16 x i8> [[XOR5]], ptr @uc, align 8
1754 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
1755 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
1756 // CHECK-NEXT: [[XOR6:%.*]] = xor <16 x i8> [[TMP12]], [[TMP13]]
1757 // CHECK-NEXT: store volatile <16 x i8> [[XOR6]], ptr @bc, align 8
1758 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
1759 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
1760 // CHECK-NEXT: [[XOR7:%.*]] = xor <8 x i16> [[TMP14]], [[TMP15]]
1761 // CHECK-NEXT: store volatile <8 x i16> [[XOR7]], ptr @ss, align 8
1762 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
1763 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
1764 // CHECK-NEXT: [[XOR8:%.*]] = xor <8 x i16> [[TMP16]], [[TMP17]]
1765 // CHECK-NEXT: store volatile <8 x i16> [[XOR8]], ptr @ss, align 8
1766 // CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
1767 // CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
1768 // CHECK-NEXT: [[XOR9:%.*]] = xor <8 x i16> [[TMP18]], [[TMP19]]
1769 // CHECK-NEXT: store volatile <8 x i16> [[XOR9]], ptr @ss, align 8
1770 // CHECK-NEXT: [[TMP20:%.*]] = load volatile <8 x i16>, ptr @us, align 8
1771 // CHECK-NEXT: [[TMP21:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
1772 // CHECK-NEXT: [[XOR10:%.*]] = xor <8 x i16> [[TMP20]], [[TMP21]]
1773 // CHECK-NEXT: store volatile <8 x i16> [[XOR10]], ptr @us, align 8
1774 // CHECK-NEXT: [[TMP22:%.*]] = load volatile <8 x i16>, ptr @us, align 8
1775 // CHECK-NEXT: [[TMP23:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
1776 // CHECK-NEXT: [[XOR11:%.*]] = xor <8 x i16> [[TMP22]], [[TMP23]]
1777 // CHECK-NEXT: store volatile <8 x i16> [[XOR11]], ptr @us, align 8
1778 // CHECK-NEXT: [[TMP24:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
1779 // CHECK-NEXT: [[TMP25:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
1780 // CHECK-NEXT: [[XOR12:%.*]] = xor <8 x i16> [[TMP24]], [[TMP25]]
1781 // CHECK-NEXT: store volatile <8 x i16> [[XOR12]], ptr @us, align 8
1782 // CHECK-NEXT: [[TMP26:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
1783 // CHECK-NEXT: [[TMP27:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
1784 // CHECK-NEXT: [[XOR13:%.*]] = xor <8 x i16> [[TMP26]], [[TMP27]]
1785 // CHECK-NEXT: store volatile <8 x i16> [[XOR13]], ptr @bs, align 8
1786 // CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @si, align 8
1787 // CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
1788 // CHECK-NEXT: [[XOR14:%.*]] = xor <4 x i32> [[TMP28]], [[TMP29]]
1789 // CHECK-NEXT: store volatile <4 x i32> [[XOR14]], ptr @si, align 8
1790 // CHECK-NEXT: [[TMP30:%.*]] = load volatile <4 x i32>, ptr @si, align 8
1791 // CHECK-NEXT: [[TMP31:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
1792 // CHECK-NEXT: [[XOR15:%.*]] = xor <4 x i32> [[TMP30]], [[TMP31]]
1793 // CHECK-NEXT: store volatile <4 x i32> [[XOR15]], ptr @si, align 8
1794 // CHECK-NEXT: [[TMP32:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
1795 // CHECK-NEXT: [[TMP33:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
1796 // CHECK-NEXT: [[XOR16:%.*]] = xor <4 x i32> [[TMP32]], [[TMP33]]
1797 // CHECK-NEXT: store volatile <4 x i32> [[XOR16]], ptr @si, align 8
1798 // CHECK-NEXT: [[TMP34:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
1799 // CHECK-NEXT: [[TMP35:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
1800 // CHECK-NEXT: [[XOR17:%.*]] = xor <4 x i32> [[TMP34]], [[TMP35]]
1801 // CHECK-NEXT: store volatile <4 x i32> [[XOR17]], ptr @ui, align 8
1802 // CHECK-NEXT: [[TMP36:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
1803 // CHECK-NEXT: [[TMP37:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
1804 // CHECK-NEXT: [[XOR18:%.*]] = xor <4 x i32> [[TMP36]], [[TMP37]]
1805 // CHECK-NEXT: store volatile <4 x i32> [[XOR18]], ptr @ui, align 8
1806 // CHECK-NEXT: [[TMP38:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
1807 // CHECK-NEXT: [[TMP39:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
1808 // CHECK-NEXT: [[XOR19:%.*]] = xor <4 x i32> [[TMP38]], [[TMP39]]
1809 // CHECK-NEXT: store volatile <4 x i32> [[XOR19]], ptr @ui, align 8
1810 // CHECK-NEXT: [[TMP40:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
1811 // CHECK-NEXT: [[TMP41:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
1812 // CHECK-NEXT: [[XOR20:%.*]] = xor <4 x i32> [[TMP40]], [[TMP41]]
1813 // CHECK-NEXT: store volatile <4 x i32> [[XOR20]], ptr @bi, align 8
1814 // CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1815 // CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
1816 // CHECK-NEXT: [[XOR21:%.*]] = xor <2 x i64> [[TMP42]], [[TMP43]]
1817 // CHECK-NEXT: store volatile <2 x i64> [[XOR21]], ptr @sl, align 8
1818 // CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1819 // CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
1820 // CHECK-NEXT: [[XOR22:%.*]] = xor <2 x i64> [[TMP44]], [[TMP45]]
1821 // CHECK-NEXT: store volatile <2 x i64> [[XOR22]], ptr @sl, align 8
1822 // CHECK-NEXT: [[TMP46:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
1823 // CHECK-NEXT: [[TMP47:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
1824 // CHECK-NEXT: [[XOR23:%.*]] = xor <2 x i64> [[TMP46]], [[TMP47]]
1825 // CHECK-NEXT: store volatile <2 x i64> [[XOR23]], ptr @sl, align 8
1826 // CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
1827 // CHECK-NEXT: [[TMP49:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
1828 // CHECK-NEXT: [[XOR24:%.*]] = xor <2 x i64> [[TMP48]], [[TMP49]]
1829 // CHECK-NEXT: store volatile <2 x i64> [[XOR24]], ptr @ul, align 8
1830 // CHECK-NEXT: [[TMP50:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
1831 // CHECK-NEXT: [[TMP51:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
1832 // CHECK-NEXT: [[XOR25:%.*]] = xor <2 x i64> [[TMP50]], [[TMP51]]
1833 // CHECK-NEXT: store volatile <2 x i64> [[XOR25]], ptr @ul, align 8
1834 // CHECK-NEXT: [[TMP52:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
1835 // CHECK-NEXT: [[TMP53:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
1836 // CHECK-NEXT: [[XOR26:%.*]] = xor <2 x i64> [[TMP52]], [[TMP53]]
1837 // CHECK-NEXT: store volatile <2 x i64> [[XOR26]], ptr @ul, align 8
1838 // CHECK-NEXT: [[TMP54:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
1839 // CHECK-NEXT: [[TMP55:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
1840 // CHECK-NEXT: [[XOR27:%.*]] = xor <2 x i64> [[TMP54]], [[TMP55]]
1841 // CHECK-NEXT: store volatile <2 x i64> [[XOR27]], ptr @bl, align 8
1842 // CHECK-NEXT: ret void
1843 //
1844 void test_xor(void) {
1845
1846 sc = sc ^ sc2;
1847 sc = sc ^ bc2;
1848 sc = bc ^ sc2;
1849 uc = uc ^ uc2;
1850 uc = uc ^ bc2;
1851 uc = bc ^ uc2;
1852 bc = bc ^ bc2;
1853
1854 ss = ss ^ ss2;
1855 ss = ss ^ bs2;
1856 ss = bs ^ ss2;
1857 us = us ^ us2;
1858 us = us ^ bs2;
1859 us = bs ^ us2;
1860 bs = bs ^ bs2;
1861
1862 si = si ^ si2;
1863 si = si ^ bi2;
1864 si = bi ^ si2;
1865 ui = ui ^ ui2;
1866 ui = ui ^ bi2;
1867 ui = bi ^ ui2;
1868 bi = bi ^ bi2;
1869
1870 sl = sl ^ sl2;
1871 sl = sl ^ bl2;
1872 sl = bl ^ sl2;
1873 ul = ul ^ ul2;
1874 ul = ul ^ bl2;
1875 ul = bl ^ ul2;
1876 bl = bl ^ bl2;
1877 }
1878
1879 // CHECK-LABEL: define dso_local void @test_xor_assign(
1880 // CHECK-SAME: ) #[[ATTR0]] {
1881 // CHECK-NEXT: [[ENTRY:.*:]]
1882 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
1883 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
1884 // CHECK-NEXT: [[XOR:%.*]] = xor <16 x i8> [[TMP1]], [[TMP0]]
1885 // CHECK-NEXT: store volatile <16 x i8> [[XOR]], ptr @sc, align 8
1886 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
1887 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
1888 // CHECK-NEXT: [[XOR1:%.*]] = xor <16 x i8> [[TMP3]], [[TMP2]]
1889 // CHECK-NEXT: store volatile <16 x i8> [[XOR1]], ptr @sc, align 8
1890 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
1891 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
1892 // CHECK-NEXT: [[XOR2:%.*]] = xor <16 x i8> [[TMP5]], [[TMP4]]
1893 // CHECK-NEXT: store volatile <16 x i8> [[XOR2]], ptr @uc, align 8
1894 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
1895 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
1896 // CHECK-NEXT: [[XOR3:%.*]] = xor <16 x i8> [[TMP7]], [[TMP6]]
1897 // CHECK-NEXT: store volatile <16 x i8> [[XOR3]], ptr @uc, align 8
1898 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
1899 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
1900 // CHECK-NEXT: [[XOR4:%.*]] = xor <16 x i8> [[TMP9]], [[TMP8]]
1901 // CHECK-NEXT: store volatile <16 x i8> [[XOR4]], ptr @bc, align 8
1902 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
1903 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
1904 // CHECK-NEXT: [[XOR5:%.*]] = xor <8 x i16> [[TMP11]], [[TMP10]]
1905 // CHECK-NEXT: store volatile <8 x i16> [[XOR5]], ptr @ss, align 8
1906 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
1907 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
1908 // CHECK-NEXT: [[XOR6:%.*]] = xor <8 x i16> [[TMP13]], [[TMP12]]
1909 // CHECK-NEXT: store volatile <8 x i16> [[XOR6]], ptr @ss, align 8
1910 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
1911 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @us, align 8
1912 // CHECK-NEXT: [[XOR7:%.*]] = xor <8 x i16> [[TMP15]], [[TMP14]]
1913 // CHECK-NEXT: store volatile <8 x i16> [[XOR7]], ptr @us, align 8
1914 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
1915 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @us, align 8
1916 // CHECK-NEXT: [[XOR8:%.*]] = xor <8 x i16> [[TMP17]], [[TMP16]]
1917 // CHECK-NEXT: store volatile <8 x i16> [[XOR8]], ptr @us, align 8
1918 // CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
1919 // CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
1920 // CHECK-NEXT: [[XOR9:%.*]] = xor <8 x i16> [[TMP19]], [[TMP18]]
1921 // CHECK-NEXT: store volatile <8 x i16> [[XOR9]], ptr @bs, align 8
1922 // CHECK-NEXT: [[TMP20:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
1923 // CHECK-NEXT: [[TMP21:%.*]] = load volatile <4 x i32>, ptr @si, align 8
1924 // CHECK-NEXT: [[XOR10:%.*]] = xor <4 x i32> [[TMP21]], [[TMP20]]
1925 // CHECK-NEXT: store volatile <4 x i32> [[XOR10]], ptr @si, align 8
1926 // CHECK-NEXT: [[TMP22:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
1927 // CHECK-NEXT: [[TMP23:%.*]] = load volatile <4 x i32>, ptr @si, align 8
1928 // CHECK-NEXT: [[XOR11:%.*]] = xor <4 x i32> [[TMP23]], [[TMP22]]
1929 // CHECK-NEXT: store volatile <4 x i32> [[XOR11]], ptr @si, align 8
1930 // CHECK-NEXT: [[TMP24:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
1931 // CHECK-NEXT: [[TMP25:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
1932 // CHECK-NEXT: [[XOR12:%.*]] = xor <4 x i32> [[TMP25]], [[TMP24]]
1933 // CHECK-NEXT: store volatile <4 x i32> [[XOR12]], ptr @ui, align 8
1934 // CHECK-NEXT: [[TMP26:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
1935 // CHECK-NEXT: [[TMP27:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
1936 // CHECK-NEXT: [[XOR13:%.*]] = xor <4 x i32> [[TMP27]], [[TMP26]]
1937 // CHECK-NEXT: store volatile <4 x i32> [[XOR13]], ptr @ui, align 8
1938 // CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
1939 // CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
1940 // CHECK-NEXT: [[XOR14:%.*]] = xor <4 x i32> [[TMP29]], [[TMP28]]
1941 // CHECK-NEXT: store volatile <4 x i32> [[XOR14]], ptr @bi, align 8
1942 // CHECK-NEXT: [[TMP30:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
1943 // CHECK-NEXT: [[TMP31:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1944 // CHECK-NEXT: [[XOR15:%.*]] = xor <2 x i64> [[TMP31]], [[TMP30]]
1945 // CHECK-NEXT: store volatile <2 x i64> [[XOR15]], ptr @sl, align 8
1946 // CHECK-NEXT: [[TMP32:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
1947 // CHECK-NEXT: [[TMP33:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1948 // CHECK-NEXT: [[XOR16:%.*]] = xor <2 x i64> [[TMP33]], [[TMP32]]
1949 // CHECK-NEXT: store volatile <2 x i64> [[XOR16]], ptr @sl, align 8
1950 // CHECK-NEXT: [[TMP34:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
1951 // CHECK-NEXT: [[TMP35:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
1952 // CHECK-NEXT: [[XOR17:%.*]] = xor <2 x i64> [[TMP35]], [[TMP34]]
1953 // CHECK-NEXT: store volatile <2 x i64> [[XOR17]], ptr @ul, align 8
1954 // CHECK-NEXT: [[TMP36:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
1955 // CHECK-NEXT: [[TMP37:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
1956 // CHECK-NEXT: [[XOR18:%.*]] = xor <2 x i64> [[TMP37]], [[TMP36]]
1957 // CHECK-NEXT: store volatile <2 x i64> [[XOR18]], ptr @ul, align 8
1958 // CHECK-NEXT: [[TMP38:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
1959 // CHECK-NEXT: [[TMP39:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
1960 // CHECK-NEXT: [[XOR19:%.*]] = xor <2 x i64> [[TMP39]], [[TMP38]]
1961 // CHECK-NEXT: store volatile <2 x i64> [[XOR19]], ptr @bl, align 8
1962 // CHECK-NEXT: ret void
1963 //
1964 void test_xor_assign(void) {
1965
1966 sc ^= sc2;
1967 sc ^= bc2;
1968 uc ^= uc2;
1969 uc ^= bc2;
1970 bc ^= bc2;
1971
1972 ss ^= ss2;
1973 ss ^= bs2;
1974 us ^= us2;
1975 us ^= bs2;
1976 bs ^= bs2;
1977
1978 si ^= si2;
1979 si ^= bi2;
1980 ui ^= ui2;
1981 ui ^= bi2;
1982 bi ^= bi2;
1983
1984 sl ^= sl2;
1985 sl ^= bl2;
1986 ul ^= ul2;
1987 ul ^= bl2;
1988 bl ^= bl2;
1989 }
1990
1991 // CHECK-LABEL: define dso_local void @test_sl(
1992 // CHECK-SAME: ) #[[ATTR0]] {
1993 // CHECK-NEXT: [[ENTRY:.*:]]
1994 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
1995 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
1996 // CHECK-NEXT: [[SHL:%.*]] = shl <16 x i8> [[TMP0]], [[TMP1]]
1997 // CHECK-NEXT: store volatile <16 x i8> [[SHL]], ptr @sc, align 8
1998 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
1999 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
2000 // CHECK-NEXT: [[SHL1:%.*]] = shl <16 x i8> [[TMP2]], [[TMP3]]
2001 // CHECK-NEXT: store volatile <16 x i8> [[SHL1]], ptr @sc, align 8
2002 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
2003 // CHECK-NEXT: [[TMP5:%.*]] = load volatile i32, ptr @cnt, align 4
2004 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[TMP5]], i64 0
2005 // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
2006 // CHECK-NEXT: [[SH_PROM:%.*]] = trunc <16 x i32> [[SPLAT_SPLAT]] to <16 x i8>
2007 // CHECK-NEXT: [[SHL2:%.*]] = shl <16 x i8> [[TMP4]], [[SH_PROM]]
2008 // CHECK-NEXT: store volatile <16 x i8> [[SHL2]], ptr @sc, align 8
2009 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
2010 // CHECK-NEXT: [[SHL3:%.*]] = shl <16 x i8> [[TMP6]], splat (i8 5)
2011 // CHECK-NEXT: store volatile <16 x i8> [[SHL3]], ptr @sc, align 8
2012 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
2013 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
2014 // CHECK-NEXT: [[SHL4:%.*]] = shl <16 x i8> [[TMP7]], [[TMP8]]
2015 // CHECK-NEXT: store volatile <16 x i8> [[SHL4]], ptr @uc, align 8
2016 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
2017 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
2018 // CHECK-NEXT: [[SHL5:%.*]] = shl <16 x i8> [[TMP9]], [[TMP10]]
2019 // CHECK-NEXT: store volatile <16 x i8> [[SHL5]], ptr @uc, align 8
2020 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
2021 // CHECK-NEXT: [[TMP12:%.*]] = load volatile i32, ptr @cnt, align 4
2022 // CHECK-NEXT: [[SPLAT_SPLATINSERT6:%.*]] = insertelement <16 x i32> poison, i32 [[TMP12]], i64 0
2023 // CHECK-NEXT: [[SPLAT_SPLAT7:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT6]], <16 x i32> poison, <16 x i32> zeroinitializer
2024 // CHECK-NEXT: [[SH_PROM8:%.*]] = trunc <16 x i32> [[SPLAT_SPLAT7]] to <16 x i8>
2025 // CHECK-NEXT: [[SHL9:%.*]] = shl <16 x i8> [[TMP11]], [[SH_PROM8]]
2026 // CHECK-NEXT: store volatile <16 x i8> [[SHL9]], ptr @uc, align 8
2027 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
2028 // CHECK-NEXT: [[SHL10:%.*]] = shl <16 x i8> [[TMP13]], splat (i8 5)
2029 // CHECK-NEXT: store volatile <16 x i8> [[SHL10]], ptr @uc, align 8
2030 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
2031 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
2032 // CHECK-NEXT: [[SHL11:%.*]] = shl <8 x i16> [[TMP14]], [[TMP15]]
2033 // CHECK-NEXT: store volatile <8 x i16> [[SHL11]], ptr @ss, align 8
2034 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
2035 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
2036 // CHECK-NEXT: [[SHL12:%.*]] = shl <8 x i16> [[TMP16]], [[TMP17]]
2037 // CHECK-NEXT: store volatile <8 x i16> [[SHL12]], ptr @ss, align 8
2038 // CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
2039 // CHECK-NEXT: [[TMP19:%.*]] = load volatile i32, ptr @cnt, align 4
2040 // CHECK-NEXT: [[SPLAT_SPLATINSERT13:%.*]] = insertelement <8 x i32> poison, i32 [[TMP19]], i64 0
2041 // CHECK-NEXT: [[SPLAT_SPLAT14:%.*]] = shufflevector <8 x i32> [[SPLAT_SPLATINSERT13]], <8 x i32> poison, <8 x i32> zeroinitializer
2042 // CHECK-NEXT: [[SH_PROM15:%.*]] = trunc <8 x i32> [[SPLAT_SPLAT14]] to <8 x i16>
2043 // CHECK-NEXT: [[SHL16:%.*]] = shl <8 x i16> [[TMP18]], [[SH_PROM15]]
2044 // CHECK-NEXT: store volatile <8 x i16> [[SHL16]], ptr @ss, align 8
2045 // CHECK-NEXT: [[TMP20:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
2046 // CHECK-NEXT: [[SHL17:%.*]] = shl <8 x i16> [[TMP20]], splat (i16 5)
2047 // CHECK-NEXT: store volatile <8 x i16> [[SHL17]], ptr @ss, align 8
2048 // CHECK-NEXT: [[TMP21:%.*]] = load volatile <8 x i16>, ptr @us, align 8
2049 // CHECK-NEXT: [[TMP22:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
2050 // CHECK-NEXT: [[SHL18:%.*]] = shl <8 x i16> [[TMP21]], [[TMP22]]
2051 // CHECK-NEXT: store volatile <8 x i16> [[SHL18]], ptr @us, align 8
2052 // CHECK-NEXT: [[TMP23:%.*]] = load volatile <8 x i16>, ptr @us, align 8
2053 // CHECK-NEXT: [[TMP24:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
2054 // CHECK-NEXT: [[SHL19:%.*]] = shl <8 x i16> [[TMP23]], [[TMP24]]
2055 // CHECK-NEXT: store volatile <8 x i16> [[SHL19]], ptr @us, align 8
2056 // CHECK-NEXT: [[TMP25:%.*]] = load volatile <8 x i16>, ptr @us, align 8
2057 // CHECK-NEXT: [[TMP26:%.*]] = load volatile i32, ptr @cnt, align 4
2058 // CHECK-NEXT: [[SPLAT_SPLATINSERT20:%.*]] = insertelement <8 x i32> poison, i32 [[TMP26]], i64 0
2059 // CHECK-NEXT: [[SPLAT_SPLAT21:%.*]] = shufflevector <8 x i32> [[SPLAT_SPLATINSERT20]], <8 x i32> poison, <8 x i32> zeroinitializer
2060 // CHECK-NEXT: [[SH_PROM22:%.*]] = trunc <8 x i32> [[SPLAT_SPLAT21]] to <8 x i16>
2061 // CHECK-NEXT: [[SHL23:%.*]] = shl <8 x i16> [[TMP25]], [[SH_PROM22]]
2062 // CHECK-NEXT: store volatile <8 x i16> [[SHL23]], ptr @us, align 8
2063 // CHECK-NEXT: [[TMP27:%.*]] = load volatile <8 x i16>, ptr @us, align 8
2064 // CHECK-NEXT: [[SHL24:%.*]] = shl <8 x i16> [[TMP27]], splat (i16 5)
2065 // CHECK-NEXT: store volatile <8 x i16> [[SHL24]], ptr @us, align 8
2066 // CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @si, align 8
2067 // CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
2068 // CHECK-NEXT: [[SHL25:%.*]] = shl <4 x i32> [[TMP28]], [[TMP29]]
2069 // CHECK-NEXT: store volatile <4 x i32> [[SHL25]], ptr @si, align 8
2070 // CHECK-NEXT: [[TMP30:%.*]] = load volatile <4 x i32>, ptr @si, align 8
2071 // CHECK-NEXT: [[TMP31:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
2072 // CHECK-NEXT: [[SHL26:%.*]] = shl <4 x i32> [[TMP30]], [[TMP31]]
2073 // CHECK-NEXT: store volatile <4 x i32> [[SHL26]], ptr @si, align 8
2074 // CHECK-NEXT: [[TMP32:%.*]] = load volatile <4 x i32>, ptr @si, align 8
2075 // CHECK-NEXT: [[TMP33:%.*]] = load volatile i32, ptr @cnt, align 4
2076 // CHECK-NEXT: [[SPLAT_SPLATINSERT27:%.*]] = insertelement <4 x i32> poison, i32 [[TMP33]], i64 0
2077 // CHECK-NEXT: [[SPLAT_SPLAT28:%.*]] = shufflevector <4 x i32> [[SPLAT_SPLATINSERT27]], <4 x i32> poison, <4 x i32> zeroinitializer
2078 // CHECK-NEXT: [[SHL29:%.*]] = shl <4 x i32> [[TMP32]], [[SPLAT_SPLAT28]]
2079 // CHECK-NEXT: store volatile <4 x i32> [[SHL29]], ptr @si, align 8
2080 // CHECK-NEXT: [[TMP34:%.*]] = load volatile <4 x i32>, ptr @si, align 8
2081 // CHECK-NEXT: [[SHL30:%.*]] = shl <4 x i32> [[TMP34]], splat (i32 5)
2082 // CHECK-NEXT: store volatile <4 x i32> [[SHL30]], ptr @si, align 8
2083 // CHECK-NEXT: [[TMP35:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
2084 // CHECK-NEXT: [[TMP36:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
2085 // CHECK-NEXT: [[SHL31:%.*]] = shl <4 x i32> [[TMP35]], [[TMP36]]
2086 // CHECK-NEXT: store volatile <4 x i32> [[SHL31]], ptr @ui, align 8
2087 // CHECK-NEXT: [[TMP37:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
2088 // CHECK-NEXT: [[TMP38:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
2089 // CHECK-NEXT: [[SHL32:%.*]] = shl <4 x i32> [[TMP37]], [[TMP38]]
2090 // CHECK-NEXT: store volatile <4 x i32> [[SHL32]], ptr @ui, align 8
2091 // CHECK-NEXT: [[TMP39:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
2092 // CHECK-NEXT: [[TMP40:%.*]] = load volatile i32, ptr @cnt, align 4
2093 // CHECK-NEXT: [[SPLAT_SPLATINSERT33:%.*]] = insertelement <4 x i32> poison, i32 [[TMP40]], i64 0
2094 // CHECK-NEXT: [[SPLAT_SPLAT34:%.*]] = shufflevector <4 x i32> [[SPLAT_SPLATINSERT33]], <4 x i32> poison, <4 x i32> zeroinitializer
2095 // CHECK-NEXT: [[SHL35:%.*]] = shl <4 x i32> [[TMP39]], [[SPLAT_SPLAT34]]
2096 // CHECK-NEXT: store volatile <4 x i32> [[SHL35]], ptr @ui, align 8
2097 // CHECK-NEXT: [[TMP41:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
2098 // CHECK-NEXT: [[SHL36:%.*]] = shl <4 x i32> [[TMP41]], splat (i32 5)
2099 // CHECK-NEXT: store volatile <4 x i32> [[SHL36]], ptr @ui, align 8
2100 // CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2101 // CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
2102 // CHECK-NEXT: [[SHL37:%.*]] = shl <2 x i64> [[TMP42]], [[TMP43]]
2103 // CHECK-NEXT: store volatile <2 x i64> [[SHL37]], ptr @sl, align 8
2104 // CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2105 // CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
2106 // CHECK-NEXT: [[SHL38:%.*]] = shl <2 x i64> [[TMP44]], [[TMP45]]
2107 // CHECK-NEXT: store volatile <2 x i64> [[SHL38]], ptr @sl, align 8
2108 // CHECK-NEXT: [[TMP46:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2109 // CHECK-NEXT: [[TMP47:%.*]] = load volatile i32, ptr @cnt, align 4
2110 // CHECK-NEXT: [[SPLAT_SPLATINSERT39:%.*]] = insertelement <2 x i32> poison, i32 [[TMP47]], i64 0
2111 // CHECK-NEXT: [[SPLAT_SPLAT40:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT39]], <2 x i32> poison, <2 x i32> zeroinitializer
2112 // CHECK-NEXT: [[SH_PROM41:%.*]] = zext <2 x i32> [[SPLAT_SPLAT40]] to <2 x i64>
2113 // CHECK-NEXT: [[SHL42:%.*]] = shl <2 x i64> [[TMP46]], [[SH_PROM41]]
2114 // CHECK-NEXT: store volatile <2 x i64> [[SHL42]], ptr @sl, align 8
2115 // CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2116 // CHECK-NEXT: [[SHL43:%.*]] = shl <2 x i64> [[TMP48]], splat (i64 5)
2117 // CHECK-NEXT: store volatile <2 x i64> [[SHL43]], ptr @sl, align 8
2118 // CHECK-NEXT: [[TMP49:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
2119 // CHECK-NEXT: [[TMP50:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
2120 // CHECK-NEXT: [[SHL44:%.*]] = shl <2 x i64> [[TMP49]], [[TMP50]]
2121 // CHECK-NEXT: store volatile <2 x i64> [[SHL44]], ptr @ul, align 8
2122 // CHECK-NEXT: [[TMP51:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
2123 // CHECK-NEXT: [[TMP52:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
2124 // CHECK-NEXT: [[SHL45:%.*]] = shl <2 x i64> [[TMP51]], [[TMP52]]
2125 // CHECK-NEXT: store volatile <2 x i64> [[SHL45]], ptr @ul, align 8
2126 // CHECK-NEXT: [[TMP53:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
2127 // CHECK-NEXT: [[TMP54:%.*]] = load volatile i32, ptr @cnt, align 4
2128 // CHECK-NEXT: [[SPLAT_SPLATINSERT46:%.*]] = insertelement <2 x i32> poison, i32 [[TMP54]], i64 0
2129 // CHECK-NEXT: [[SPLAT_SPLAT47:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT46]], <2 x i32> poison, <2 x i32> zeroinitializer
2130 // CHECK-NEXT: [[SH_PROM48:%.*]] = zext <2 x i32> [[SPLAT_SPLAT47]] to <2 x i64>
2131 // CHECK-NEXT: [[SHL49:%.*]] = shl <2 x i64> [[TMP53]], [[SH_PROM48]]
2132 // CHECK-NEXT: store volatile <2 x i64> [[SHL49]], ptr @ul, align 8
2133 // CHECK-NEXT: [[TMP55:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
2134 // CHECK-NEXT: [[SHL50:%.*]] = shl <2 x i64> [[TMP55]], splat (i64 5)
2135 // CHECK-NEXT: store volatile <2 x i64> [[SHL50]], ptr @ul, align 8
2136 // CHECK-NEXT: ret void
2137 //
2138 void test_sl(void) {
2139
2140 sc = sc << sc2;
2141 sc = sc << uc2;
2142 sc = sc << cnt;
2143 sc = sc << 5;
2144 uc = uc << sc2;
2145 uc = uc << uc2;
2146 uc = uc << cnt;
2147 uc = uc << 5;
2148
2149 ss = ss << ss2;
2150 ss = ss << us2;
2151 ss = ss << cnt;
2152 ss = ss << 5;
2153 us = us << ss2;
2154 us = us << us2;
2155 us = us << cnt;
2156 us = us << 5;
2157
2158 si = si << si2;
2159 si = si << ui2;
2160 si = si << cnt;
2161 si = si << 5;
2162 ui = ui << si2;
2163 ui = ui << ui2;
2164 ui = ui << cnt;
2165 ui = ui << 5;
2166
2167 sl = sl << sl2;
2168 sl = sl << ul2;
2169 sl = sl << cnt;
2170 sl = sl << 5;
2171 ul = ul << sl2;
2172 ul = ul << ul2;
2173 ul = ul << cnt;
2174 ul = ul << 5;
2175 }
2176
2177 // CHECK-LABEL: define dso_local void @test_sl_assign(
2178 // CHECK-SAME: ) #[[ATTR0]] {
2179 // CHECK-NEXT: [[ENTRY:.*:]]
2180 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
2181 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
2182 // CHECK-NEXT: [[SHL:%.*]] = shl <16 x i8> [[TMP1]], [[TMP0]]
2183 // CHECK-NEXT: store volatile <16 x i8> [[SHL]], ptr @sc, align 8
2184 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
2185 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
2186 // CHECK-NEXT: [[SHL1:%.*]] = shl <16 x i8> [[TMP3]], [[TMP2]]
2187 // CHECK-NEXT: store volatile <16 x i8> [[SHL1]], ptr @sc, align 8
2188 // CHECK-NEXT: [[TMP4:%.*]] = load volatile i32, ptr @cnt, align 4
2189 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[TMP4]], i64 0
2190 // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
2191 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
2192 // CHECK-NEXT: [[SH_PROM:%.*]] = trunc <16 x i32> [[SPLAT_SPLAT]] to <16 x i8>
2193 // CHECK-NEXT: [[SHL2:%.*]] = shl <16 x i8> [[TMP5]], [[SH_PROM]]
2194 // CHECK-NEXT: store volatile <16 x i8> [[SHL2]], ptr @sc, align 8
2195 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
2196 // CHECK-NEXT: [[SHL3:%.*]] = shl <16 x i8> [[TMP6]], splat (i8 5)
2197 // CHECK-NEXT: store volatile <16 x i8> [[SHL3]], ptr @sc, align 8
2198 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
2199 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
2200 // CHECK-NEXT: [[SHL4:%.*]] = shl <16 x i8> [[TMP8]], [[TMP7]]
2201 // CHECK-NEXT: store volatile <16 x i8> [[SHL4]], ptr @uc, align 8
2202 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
2203 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
2204 // CHECK-NEXT: [[SHL5:%.*]] = shl <16 x i8> [[TMP10]], [[TMP9]]
2205 // CHECK-NEXT: store volatile <16 x i8> [[SHL5]], ptr @uc, align 8
2206 // CHECK-NEXT: [[TMP11:%.*]] = load volatile i32, ptr @cnt, align 4
2207 // CHECK-NEXT: [[SPLAT_SPLATINSERT6:%.*]] = insertelement <16 x i32> poison, i32 [[TMP11]], i64 0
2208 // CHECK-NEXT: [[SPLAT_SPLAT7:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT6]], <16 x i32> poison, <16 x i32> zeroinitializer
2209 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
2210 // CHECK-NEXT: [[SH_PROM8:%.*]] = trunc <16 x i32> [[SPLAT_SPLAT7]] to <16 x i8>
2211 // CHECK-NEXT: [[SHL9:%.*]] = shl <16 x i8> [[TMP12]], [[SH_PROM8]]
2212 // CHECK-NEXT: store volatile <16 x i8> [[SHL9]], ptr @uc, align 8
2213 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
2214 // CHECK-NEXT: [[SHL10:%.*]] = shl <16 x i8> [[TMP13]], splat (i8 5)
2215 // CHECK-NEXT: store volatile <16 x i8> [[SHL10]], ptr @uc, align 8
2216 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
2217 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
2218 // CHECK-NEXT: [[SHL11:%.*]] = shl <8 x i16> [[TMP15]], [[TMP14]]
2219 // CHECK-NEXT: store volatile <8 x i16> [[SHL11]], ptr @ss, align 8
2220 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
2221 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
2222 // CHECK-NEXT: [[SHL12:%.*]] = shl <8 x i16> [[TMP17]], [[TMP16]]
2223 // CHECK-NEXT: store volatile <8 x i16> [[SHL12]], ptr @ss, align 8
2224 // CHECK-NEXT: [[TMP18:%.*]] = load volatile i32, ptr @cnt, align 4
2225 // CHECK-NEXT: [[SPLAT_SPLATINSERT13:%.*]] = insertelement <8 x i32> poison, i32 [[TMP18]], i64 0
2226 // CHECK-NEXT: [[SPLAT_SPLAT14:%.*]] = shufflevector <8 x i32> [[SPLAT_SPLATINSERT13]], <8 x i32> poison, <8 x i32> zeroinitializer
2227 // CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
2228 // CHECK-NEXT: [[SH_PROM15:%.*]] = trunc <8 x i32> [[SPLAT_SPLAT14]] to <8 x i16>
2229 // CHECK-NEXT: [[SHL16:%.*]] = shl <8 x i16> [[TMP19]], [[SH_PROM15]]
2230 // CHECK-NEXT: store volatile <8 x i16> [[SHL16]], ptr @ss, align 8
2231 // CHECK-NEXT: [[TMP20:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
2232 // CHECK-NEXT: [[SHL17:%.*]] = shl <8 x i16> [[TMP20]], splat (i16 5)
2233 // CHECK-NEXT: store volatile <8 x i16> [[SHL17]], ptr @ss, align 8
2234 // CHECK-NEXT: [[TMP21:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
2235 // CHECK-NEXT: [[TMP22:%.*]] = load volatile <8 x i16>, ptr @us, align 8
2236 // CHECK-NEXT: [[SHL18:%.*]] = shl <8 x i16> [[TMP22]], [[TMP21]]
2237 // CHECK-NEXT: store volatile <8 x i16> [[SHL18]], ptr @us, align 8
2238 // CHECK-NEXT: [[TMP23:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
2239 // CHECK-NEXT: [[TMP24:%.*]] = load volatile <8 x i16>, ptr @us, align 8
2240 // CHECK-NEXT: [[SHL19:%.*]] = shl <8 x i16> [[TMP24]], [[TMP23]]
2241 // CHECK-NEXT: store volatile <8 x i16> [[SHL19]], ptr @us, align 8
2242 // CHECK-NEXT: [[TMP25:%.*]] = load volatile i32, ptr @cnt, align 4
2243 // CHECK-NEXT: [[SPLAT_SPLATINSERT20:%.*]] = insertelement <8 x i32> poison, i32 [[TMP25]], i64 0
2244 // CHECK-NEXT: [[SPLAT_SPLAT21:%.*]] = shufflevector <8 x i32> [[SPLAT_SPLATINSERT20]], <8 x i32> poison, <8 x i32> zeroinitializer
2245 // CHECK-NEXT: [[TMP26:%.*]] = load volatile <8 x i16>, ptr @us, align 8
2246 // CHECK-NEXT: [[SH_PROM22:%.*]] = trunc <8 x i32> [[SPLAT_SPLAT21]] to <8 x i16>
2247 // CHECK-NEXT: [[SHL23:%.*]] = shl <8 x i16> [[TMP26]], [[SH_PROM22]]
2248 // CHECK-NEXT: store volatile <8 x i16> [[SHL23]], ptr @us, align 8
2249 // CHECK-NEXT: [[TMP27:%.*]] = load volatile <8 x i16>, ptr @us, align 8
2250 // CHECK-NEXT: [[SHL24:%.*]] = shl <8 x i16> [[TMP27]], splat (i16 5)
2251 // CHECK-NEXT: store volatile <8 x i16> [[SHL24]], ptr @us, align 8
2252 // CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
2253 // CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @si, align 8
2254 // CHECK-NEXT: [[SHL25:%.*]] = shl <4 x i32> [[TMP29]], [[TMP28]]
2255 // CHECK-NEXT: store volatile <4 x i32> [[SHL25]], ptr @si, align 8
2256 // CHECK-NEXT: [[TMP30:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
2257 // CHECK-NEXT: [[TMP31:%.*]] = load volatile <4 x i32>, ptr @si, align 8
2258 // CHECK-NEXT: [[SHL26:%.*]] = shl <4 x i32> [[TMP31]], [[TMP30]]
2259 // CHECK-NEXT: store volatile <4 x i32> [[SHL26]], ptr @si, align 8
2260 // CHECK-NEXT: [[TMP32:%.*]] = load volatile i32, ptr @cnt, align 4
2261 // CHECK-NEXT: [[SPLAT_SPLATINSERT27:%.*]] = insertelement <4 x i32> poison, i32 [[TMP32]], i64 0
2262 // CHECK-NEXT: [[SPLAT_SPLAT28:%.*]] = shufflevector <4 x i32> [[SPLAT_SPLATINSERT27]], <4 x i32> poison, <4 x i32> zeroinitializer
2263 // CHECK-NEXT: [[TMP33:%.*]] = load volatile <4 x i32>, ptr @si, align 8
2264 // CHECK-NEXT: [[SHL29:%.*]] = shl <4 x i32> [[TMP33]], [[SPLAT_SPLAT28]]
2265 // CHECK-NEXT: store volatile <4 x i32> [[SHL29]], ptr @si, align 8
2266 // CHECK-NEXT: [[TMP34:%.*]] = load volatile <4 x i32>, ptr @si, align 8
2267 // CHECK-NEXT: [[SHL30:%.*]] = shl <4 x i32> [[TMP34]], splat (i32 5)
2268 // CHECK-NEXT: store volatile <4 x i32> [[SHL30]], ptr @si, align 8
2269 // CHECK-NEXT: [[TMP35:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
2270 // CHECK-NEXT: [[TMP36:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
2271 // CHECK-NEXT: [[SHL31:%.*]] = shl <4 x i32> [[TMP36]], [[TMP35]]
2272 // CHECK-NEXT: store volatile <4 x i32> [[SHL31]], ptr @ui, align 8
2273 // CHECK-NEXT: [[TMP37:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
2274 // CHECK-NEXT: [[TMP38:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
2275 // CHECK-NEXT: [[SHL32:%.*]] = shl <4 x i32> [[TMP38]], [[TMP37]]
2276 // CHECK-NEXT: store volatile <4 x i32> [[SHL32]], ptr @ui, align 8
2277 // CHECK-NEXT: [[TMP39:%.*]] = load volatile i32, ptr @cnt, align 4
2278 // CHECK-NEXT: [[SPLAT_SPLATINSERT33:%.*]] = insertelement <4 x i32> poison, i32 [[TMP39]], i64 0
2279 // CHECK-NEXT: [[SPLAT_SPLAT34:%.*]] = shufflevector <4 x i32> [[SPLAT_SPLATINSERT33]], <4 x i32> poison, <4 x i32> zeroinitializer
2280 // CHECK-NEXT: [[TMP40:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
2281 // CHECK-NEXT: [[SHL35:%.*]] = shl <4 x i32> [[TMP40]], [[SPLAT_SPLAT34]]
2282 // CHECK-NEXT: store volatile <4 x i32> [[SHL35]], ptr @ui, align 8
2283 // CHECK-NEXT: [[TMP41:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
2284 // CHECK-NEXT: [[SHL36:%.*]] = shl <4 x i32> [[TMP41]], splat (i32 5)
2285 // CHECK-NEXT: store volatile <4 x i32> [[SHL36]], ptr @ui, align 8
2286 // CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
2287 // CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2288 // CHECK-NEXT: [[SHL37:%.*]] = shl <2 x i64> [[TMP43]], [[TMP42]]
2289 // CHECK-NEXT: store volatile <2 x i64> [[SHL37]], ptr @sl, align 8
2290 // CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
2291 // CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2292 // CHECK-NEXT: [[SHL38:%.*]] = shl <2 x i64> [[TMP45]], [[TMP44]]
2293 // CHECK-NEXT: store volatile <2 x i64> [[SHL38]], ptr @sl, align 8
2294 // CHECK-NEXT: [[TMP46:%.*]] = load volatile i32, ptr @cnt, align 4
2295 // CHECK-NEXT: [[SPLAT_SPLATINSERT39:%.*]] = insertelement <2 x i32> poison, i32 [[TMP46]], i64 0
2296 // CHECK-NEXT: [[SPLAT_SPLAT40:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT39]], <2 x i32> poison, <2 x i32> zeroinitializer
2297 // CHECK-NEXT: [[TMP47:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2298 // CHECK-NEXT: [[SH_PROM41:%.*]] = zext <2 x i32> [[SPLAT_SPLAT40]] to <2 x i64>
2299 // CHECK-NEXT: [[SHL42:%.*]] = shl <2 x i64> [[TMP47]], [[SH_PROM41]]
2300 // CHECK-NEXT: store volatile <2 x i64> [[SHL42]], ptr @sl, align 8
2301 // CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2302 // CHECK-NEXT: [[SHL43:%.*]] = shl <2 x i64> [[TMP48]], splat (i64 5)
2303 // CHECK-NEXT: store volatile <2 x i64> [[SHL43]], ptr @sl, align 8
2304 // CHECK-NEXT: [[TMP49:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
2305 // CHECK-NEXT: [[TMP50:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
2306 // CHECK-NEXT: [[SHL44:%.*]] = shl <2 x i64> [[TMP50]], [[TMP49]]
2307 // CHECK-NEXT: store volatile <2 x i64> [[SHL44]], ptr @ul, align 8
2308 // CHECK-NEXT: [[TMP51:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
2309 // CHECK-NEXT: [[TMP52:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
2310 // CHECK-NEXT: [[SHL45:%.*]] = shl <2 x i64> [[TMP52]], [[TMP51]]
2311 // CHECK-NEXT: store volatile <2 x i64> [[SHL45]], ptr @ul, align 8
2312 // CHECK-NEXT: [[TMP53:%.*]] = load volatile i32, ptr @cnt, align 4
2313 // CHECK-NEXT: [[SPLAT_SPLATINSERT46:%.*]] = insertelement <2 x i32> poison, i32 [[TMP53]], i64 0
2314 // CHECK-NEXT: [[SPLAT_SPLAT47:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT46]], <2 x i32> poison, <2 x i32> zeroinitializer
2315 // CHECK-NEXT: [[TMP54:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
2316 // CHECK-NEXT: [[SH_PROM48:%.*]] = zext <2 x i32> [[SPLAT_SPLAT47]] to <2 x i64>
2317 // CHECK-NEXT: [[SHL49:%.*]] = shl <2 x i64> [[TMP54]], [[SH_PROM48]]
2318 // CHECK-NEXT: store volatile <2 x i64> [[SHL49]], ptr @ul, align 8
2319 // CHECK-NEXT: [[TMP55:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
2320 // CHECK-NEXT: [[SHL50:%.*]] = shl <2 x i64> [[TMP55]], splat (i64 5)
2321 // CHECK-NEXT: store volatile <2 x i64> [[SHL50]], ptr @ul, align 8
2322 // CHECK-NEXT: ret void
2323 //
2324 void test_sl_assign(void) {
2325
2326 sc <<= sc2;
2327 sc <<= uc2;
2328 sc <<= cnt;
2329 sc <<= 5;
2330 uc <<= sc2;
2331 uc <<= uc2;
2332 uc <<= cnt;
2333 uc <<= 5;
2334
2335 ss <<= ss2;
2336 ss <<= us2;
2337 ss <<= cnt;
2338 ss <<= 5;
2339 us <<= ss2;
2340 us <<= us2;
2341 us <<= cnt;
2342 us <<= 5;
2343
2344 si <<= si2;
2345 si <<= ui2;
2346 si <<= cnt;
2347 si <<= 5;
2348 ui <<= si2;
2349 ui <<= ui2;
2350 ui <<= cnt;
2351 ui <<= 5;
2352
2353 sl <<= sl2;
2354 sl <<= ul2;
2355 sl <<= cnt;
2356 sl <<= 5;
2357 ul <<= sl2;
2358 ul <<= ul2;
2359 ul <<= cnt;
2360 ul <<= 5;
2361 }
2362
2363 // CHECK-LABEL: define dso_local void @test_sr(
2364 // CHECK-SAME: ) #[[ATTR0]] {
2365 // CHECK-NEXT: [[ENTRY:.*:]]
2366 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
2367 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
2368 // CHECK-NEXT: [[SHR:%.*]] = ashr <16 x i8> [[TMP0]], [[TMP1]]
2369 // CHECK-NEXT: store volatile <16 x i8> [[SHR]], ptr @sc, align 8
2370 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
2371 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
2372 // CHECK-NEXT: [[SHR1:%.*]] = ashr <16 x i8> [[TMP2]], [[TMP3]]
2373 // CHECK-NEXT: store volatile <16 x i8> [[SHR1]], ptr @sc, align 8
2374 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
2375 // CHECK-NEXT: [[TMP5:%.*]] = load volatile i32, ptr @cnt, align 4
2376 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[TMP5]], i64 0
2377 // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
2378 // CHECK-NEXT: [[SH_PROM:%.*]] = trunc <16 x i32> [[SPLAT_SPLAT]] to <16 x i8>
2379 // CHECK-NEXT: [[SHR2:%.*]] = ashr <16 x i8> [[TMP4]], [[SH_PROM]]
2380 // CHECK-NEXT: store volatile <16 x i8> [[SHR2]], ptr @sc, align 8
2381 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
2382 // CHECK-NEXT: [[SHR3:%.*]] = ashr <16 x i8> [[TMP6]], splat (i8 5)
2383 // CHECK-NEXT: store volatile <16 x i8> [[SHR3]], ptr @sc, align 8
2384 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
2385 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
2386 // CHECK-NEXT: [[SHR4:%.*]] = lshr <16 x i8> [[TMP7]], [[TMP8]]
2387 // CHECK-NEXT: store volatile <16 x i8> [[SHR4]], ptr @uc, align 8
2388 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
2389 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
2390 // CHECK-NEXT: [[SHR5:%.*]] = lshr <16 x i8> [[TMP9]], [[TMP10]]
2391 // CHECK-NEXT: store volatile <16 x i8> [[SHR5]], ptr @uc, align 8
2392 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
2393 // CHECK-NEXT: [[TMP12:%.*]] = load volatile i32, ptr @cnt, align 4
2394 // CHECK-NEXT: [[SPLAT_SPLATINSERT6:%.*]] = insertelement <16 x i32> poison, i32 [[TMP12]], i64 0
2395 // CHECK-NEXT: [[SPLAT_SPLAT7:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT6]], <16 x i32> poison, <16 x i32> zeroinitializer
2396 // CHECK-NEXT: [[SH_PROM8:%.*]] = trunc <16 x i32> [[SPLAT_SPLAT7]] to <16 x i8>
2397 // CHECK-NEXT: [[SHR9:%.*]] = lshr <16 x i8> [[TMP11]], [[SH_PROM8]]
2398 // CHECK-NEXT: store volatile <16 x i8> [[SHR9]], ptr @uc, align 8
2399 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
2400 // CHECK-NEXT: [[SHR10:%.*]] = lshr <16 x i8> [[TMP13]], splat (i8 5)
2401 // CHECK-NEXT: store volatile <16 x i8> [[SHR10]], ptr @uc, align 8
2402 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
2403 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
2404 // CHECK-NEXT: [[SHR11:%.*]] = ashr <8 x i16> [[TMP14]], [[TMP15]]
2405 // CHECK-NEXT: store volatile <8 x i16> [[SHR11]], ptr @ss, align 8
2406 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
2407 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
2408 // CHECK-NEXT: [[SHR12:%.*]] = ashr <8 x i16> [[TMP16]], [[TMP17]]
2409 // CHECK-NEXT: store volatile <8 x i16> [[SHR12]], ptr @ss, align 8
2410 // CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
2411 // CHECK-NEXT: [[TMP19:%.*]] = load volatile i32, ptr @cnt, align 4
2412 // CHECK-NEXT: [[SPLAT_SPLATINSERT13:%.*]] = insertelement <8 x i32> poison, i32 [[TMP19]], i64 0
2413 // CHECK-NEXT: [[SPLAT_SPLAT14:%.*]] = shufflevector <8 x i32> [[SPLAT_SPLATINSERT13]], <8 x i32> poison, <8 x i32> zeroinitializer
2414 // CHECK-NEXT: [[SH_PROM15:%.*]] = trunc <8 x i32> [[SPLAT_SPLAT14]] to <8 x i16>
2415 // CHECK-NEXT: [[SHR16:%.*]] = ashr <8 x i16> [[TMP18]], [[SH_PROM15]]
2416 // CHECK-NEXT: store volatile <8 x i16> [[SHR16]], ptr @ss, align 8
2417 // CHECK-NEXT: [[TMP20:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
2418 // CHECK-NEXT: [[SHR17:%.*]] = ashr <8 x i16> [[TMP20]], splat (i16 5)
2419 // CHECK-NEXT: store volatile <8 x i16> [[SHR17]], ptr @ss, align 8
2420 // CHECK-NEXT: [[TMP21:%.*]] = load volatile <8 x i16>, ptr @us, align 8
2421 // CHECK-NEXT: [[TMP22:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
2422 // CHECK-NEXT: [[SHR18:%.*]] = lshr <8 x i16> [[TMP21]], [[TMP22]]
2423 // CHECK-NEXT: store volatile <8 x i16> [[SHR18]], ptr @us, align 8
2424 // CHECK-NEXT: [[TMP23:%.*]] = load volatile <8 x i16>, ptr @us, align 8
2425 // CHECK-NEXT: [[TMP24:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
2426 // CHECK-NEXT: [[SHR19:%.*]] = lshr <8 x i16> [[TMP23]], [[TMP24]]
2427 // CHECK-NEXT: store volatile <8 x i16> [[SHR19]], ptr @us, align 8
2428 // CHECK-NEXT: [[TMP25:%.*]] = load volatile <8 x i16>, ptr @us, align 8
2429 // CHECK-NEXT: [[TMP26:%.*]] = load volatile i32, ptr @cnt, align 4
2430 // CHECK-NEXT: [[SPLAT_SPLATINSERT20:%.*]] = insertelement <8 x i32> poison, i32 [[TMP26]], i64 0
2431 // CHECK-NEXT: [[SPLAT_SPLAT21:%.*]] = shufflevector <8 x i32> [[SPLAT_SPLATINSERT20]], <8 x i32> poison, <8 x i32> zeroinitializer
2432 // CHECK-NEXT: [[SH_PROM22:%.*]] = trunc <8 x i32> [[SPLAT_SPLAT21]] to <8 x i16>
2433 // CHECK-NEXT: [[SHR23:%.*]] = lshr <8 x i16> [[TMP25]], [[SH_PROM22]]
2434 // CHECK-NEXT: store volatile <8 x i16> [[SHR23]], ptr @us, align 8
2435 // CHECK-NEXT: [[TMP27:%.*]] = load volatile <8 x i16>, ptr @us, align 8
2436 // CHECK-NEXT: [[SHR24:%.*]] = lshr <8 x i16> [[TMP27]], splat (i16 5)
2437 // CHECK-NEXT: store volatile <8 x i16> [[SHR24]], ptr @us, align 8
2438 // CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @si, align 8
2439 // CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
2440 // CHECK-NEXT: [[SHR25:%.*]] = ashr <4 x i32> [[TMP28]], [[TMP29]]
2441 // CHECK-NEXT: store volatile <4 x i32> [[SHR25]], ptr @si, align 8
2442 // CHECK-NEXT: [[TMP30:%.*]] = load volatile <4 x i32>, ptr @si, align 8
2443 // CHECK-NEXT: [[TMP31:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
2444 // CHECK-NEXT: [[SHR26:%.*]] = ashr <4 x i32> [[TMP30]], [[TMP31]]
2445 // CHECK-NEXT: store volatile <4 x i32> [[SHR26]], ptr @si, align 8
2446 // CHECK-NEXT: [[TMP32:%.*]] = load volatile <4 x i32>, ptr @si, align 8
2447 // CHECK-NEXT: [[TMP33:%.*]] = load volatile i32, ptr @cnt, align 4
2448 // CHECK-NEXT: [[SPLAT_SPLATINSERT27:%.*]] = insertelement <4 x i32> poison, i32 [[TMP33]], i64 0
2449 // CHECK-NEXT: [[SPLAT_SPLAT28:%.*]] = shufflevector <4 x i32> [[SPLAT_SPLATINSERT27]], <4 x i32> poison, <4 x i32> zeroinitializer
2450 // CHECK-NEXT: [[SHR29:%.*]] = ashr <4 x i32> [[TMP32]], [[SPLAT_SPLAT28]]
2451 // CHECK-NEXT: store volatile <4 x i32> [[SHR29]], ptr @si, align 8
2452 // CHECK-NEXT: [[TMP34:%.*]] = load volatile <4 x i32>, ptr @si, align 8
2453 // CHECK-NEXT: [[SHR30:%.*]] = ashr <4 x i32> [[TMP34]], splat (i32 5)
2454 // CHECK-NEXT: store volatile <4 x i32> [[SHR30]], ptr @si, align 8
2455 // CHECK-NEXT: [[TMP35:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
2456 // CHECK-NEXT: [[TMP36:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
2457 // CHECK-NEXT: [[SHR31:%.*]] = lshr <4 x i32> [[TMP35]], [[TMP36]]
2458 // CHECK-NEXT: store volatile <4 x i32> [[SHR31]], ptr @ui, align 8
2459 // CHECK-NEXT: [[TMP37:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
2460 // CHECK-NEXT: [[TMP38:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
2461 // CHECK-NEXT: [[SHR32:%.*]] = lshr <4 x i32> [[TMP37]], [[TMP38]]
2462 // CHECK-NEXT: store volatile <4 x i32> [[SHR32]], ptr @ui, align 8
2463 // CHECK-NEXT: [[TMP39:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
2464 // CHECK-NEXT: [[TMP40:%.*]] = load volatile i32, ptr @cnt, align 4
2465 // CHECK-NEXT: [[SPLAT_SPLATINSERT33:%.*]] = insertelement <4 x i32> poison, i32 [[TMP40]], i64 0
2466 // CHECK-NEXT: [[SPLAT_SPLAT34:%.*]] = shufflevector <4 x i32> [[SPLAT_SPLATINSERT33]], <4 x i32> poison, <4 x i32> zeroinitializer
2467 // CHECK-NEXT: [[SHR35:%.*]] = lshr <4 x i32> [[TMP39]], [[SPLAT_SPLAT34]]
2468 // CHECK-NEXT: store volatile <4 x i32> [[SHR35]], ptr @ui, align 8
2469 // CHECK-NEXT: [[TMP41:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
2470 // CHECK-NEXT: [[SHR36:%.*]] = lshr <4 x i32> [[TMP41]], splat (i32 5)
2471 // CHECK-NEXT: store volatile <4 x i32> [[SHR36]], ptr @ui, align 8
2472 // CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2473 // CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
2474 // CHECK-NEXT: [[SHR37:%.*]] = ashr <2 x i64> [[TMP42]], [[TMP43]]
2475 // CHECK-NEXT: store volatile <2 x i64> [[SHR37]], ptr @sl, align 8
2476 // CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2477 // CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
2478 // CHECK-NEXT: [[SHR38:%.*]] = ashr <2 x i64> [[TMP44]], [[TMP45]]
2479 // CHECK-NEXT: store volatile <2 x i64> [[SHR38]], ptr @sl, align 8
2480 // CHECK-NEXT: [[TMP46:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2481 // CHECK-NEXT: [[TMP47:%.*]] = load volatile i32, ptr @cnt, align 4
2482 // CHECK-NEXT: [[SPLAT_SPLATINSERT39:%.*]] = insertelement <2 x i32> poison, i32 [[TMP47]], i64 0
2483 // CHECK-NEXT: [[SPLAT_SPLAT40:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT39]], <2 x i32> poison, <2 x i32> zeroinitializer
2484 // CHECK-NEXT: [[SH_PROM41:%.*]] = zext <2 x i32> [[SPLAT_SPLAT40]] to <2 x i64>
2485 // CHECK-NEXT: [[SHR42:%.*]] = ashr <2 x i64> [[TMP46]], [[SH_PROM41]]
2486 // CHECK-NEXT: store volatile <2 x i64> [[SHR42]], ptr @sl, align 8
2487 // CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2488 // CHECK-NEXT: [[SHR43:%.*]] = ashr <2 x i64> [[TMP48]], splat (i64 5)
2489 // CHECK-NEXT: store volatile <2 x i64> [[SHR43]], ptr @sl, align 8
2490 // CHECK-NEXT: [[TMP49:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
2491 // CHECK-NEXT: [[TMP50:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
2492 // CHECK-NEXT: [[SHR44:%.*]] = lshr <2 x i64> [[TMP49]], [[TMP50]]
2493 // CHECK-NEXT: store volatile <2 x i64> [[SHR44]], ptr @ul, align 8
2494 // CHECK-NEXT: [[TMP51:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
2495 // CHECK-NEXT: [[TMP52:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
2496 // CHECK-NEXT: [[SHR45:%.*]] = lshr <2 x i64> [[TMP51]], [[TMP52]]
2497 // CHECK-NEXT: store volatile <2 x i64> [[SHR45]], ptr @ul, align 8
2498 // CHECK-NEXT: [[TMP53:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
2499 // CHECK-NEXT: [[TMP54:%.*]] = load volatile i32, ptr @cnt, align 4
2500 // CHECK-NEXT: [[SPLAT_SPLATINSERT46:%.*]] = insertelement <2 x i32> poison, i32 [[TMP54]], i64 0
2501 // CHECK-NEXT: [[SPLAT_SPLAT47:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT46]], <2 x i32> poison, <2 x i32> zeroinitializer
2502 // CHECK-NEXT: [[SH_PROM48:%.*]] = zext <2 x i32> [[SPLAT_SPLAT47]] to <2 x i64>
2503 // CHECK-NEXT: [[SHR49:%.*]] = lshr <2 x i64> [[TMP53]], [[SH_PROM48]]
2504 // CHECK-NEXT: store volatile <2 x i64> [[SHR49]], ptr @ul, align 8
2505 // CHECK-NEXT: [[TMP55:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
2506 // CHECK-NEXT: [[SHR50:%.*]] = lshr <2 x i64> [[TMP55]], splat (i64 5)
2507 // CHECK-NEXT: store volatile <2 x i64> [[SHR50]], ptr @ul, align 8
2508 // CHECK-NEXT: ret void
2509 //
2510 void test_sr(void) {
2511
2512 sc = sc >> sc2;
2513 sc = sc >> uc2;
2514 sc = sc >> cnt;
2515 sc = sc >> 5;
2516 uc = uc >> sc2;
2517 uc = uc >> uc2;
2518 uc = uc >> cnt;
2519 uc = uc >> 5;
2520
2521 ss = ss >> ss2;
2522 ss = ss >> us2;
2523 ss = ss >> cnt;
2524 ss = ss >> 5;
2525 us = us >> ss2;
2526 us = us >> us2;
2527 us = us >> cnt;
2528 us = us >> 5;
2529
2530 si = si >> si2;
2531 si = si >> ui2;
2532 si = si >> cnt;
2533 si = si >> 5;
2534 ui = ui >> si2;
2535 ui = ui >> ui2;
2536 ui = ui >> cnt;
2537 ui = ui >> 5;
2538
2539 sl = sl >> sl2;
2540 sl = sl >> ul2;
2541 sl = sl >> cnt;
2542 sl = sl >> 5;
2543 ul = ul >> sl2;
2544 ul = ul >> ul2;
2545 ul = ul >> cnt;
2546 ul = ul >> 5;
2547 }
2548
2549 // CHECK-LABEL: define dso_local void @test_sr_assign(
2550 // CHECK-SAME: ) #[[ATTR0]] {
2551 // CHECK-NEXT: [[ENTRY:.*:]]
2552 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
2553 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
2554 // CHECK-NEXT: [[SHR:%.*]] = ashr <16 x i8> [[TMP1]], [[TMP0]]
2555 // CHECK-NEXT: store volatile <16 x i8> [[SHR]], ptr @sc, align 8
2556 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
2557 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
2558 // CHECK-NEXT: [[SHR1:%.*]] = ashr <16 x i8> [[TMP3]], [[TMP2]]
2559 // CHECK-NEXT: store volatile <16 x i8> [[SHR1]], ptr @sc, align 8
2560 // CHECK-NEXT: [[TMP4:%.*]] = load volatile i32, ptr @cnt, align 4
2561 // CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[TMP4]], i64 0
2562 // CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT]], <16 x i32> poison, <16 x i32> zeroinitializer
2563 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
2564 // CHECK-NEXT: [[SH_PROM:%.*]] = trunc <16 x i32> [[SPLAT_SPLAT]] to <16 x i8>
2565 // CHECK-NEXT: [[SHR2:%.*]] = ashr <16 x i8> [[TMP5]], [[SH_PROM]]
2566 // CHECK-NEXT: store volatile <16 x i8> [[SHR2]], ptr @sc, align 8
2567 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
2568 // CHECK-NEXT: [[SHR3:%.*]] = ashr <16 x i8> [[TMP6]], splat (i8 5)
2569 // CHECK-NEXT: store volatile <16 x i8> [[SHR3]], ptr @sc, align 8
2570 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
2571 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
2572 // CHECK-NEXT: [[SHR4:%.*]] = lshr <16 x i8> [[TMP8]], [[TMP7]]
2573 // CHECK-NEXT: store volatile <16 x i8> [[SHR4]], ptr @uc, align 8
2574 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
2575 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
2576 // CHECK-NEXT: [[SHR5:%.*]] = lshr <16 x i8> [[TMP10]], [[TMP9]]
2577 // CHECK-NEXT: store volatile <16 x i8> [[SHR5]], ptr @uc, align 8
2578 // CHECK-NEXT: [[TMP11:%.*]] = load volatile i32, ptr @cnt, align 4
2579 // CHECK-NEXT: [[SPLAT_SPLATINSERT6:%.*]] = insertelement <16 x i32> poison, i32 [[TMP11]], i64 0
2580 // CHECK-NEXT: [[SPLAT_SPLAT7:%.*]] = shufflevector <16 x i32> [[SPLAT_SPLATINSERT6]], <16 x i32> poison, <16 x i32> zeroinitializer
2581 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
2582 // CHECK-NEXT: [[SH_PROM8:%.*]] = trunc <16 x i32> [[SPLAT_SPLAT7]] to <16 x i8>
2583 // CHECK-NEXT: [[SHR9:%.*]] = lshr <16 x i8> [[TMP12]], [[SH_PROM8]]
2584 // CHECK-NEXT: store volatile <16 x i8> [[SHR9]], ptr @uc, align 8
2585 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
2586 // CHECK-NEXT: [[SHR10:%.*]] = lshr <16 x i8> [[TMP13]], splat (i8 5)
2587 // CHECK-NEXT: store volatile <16 x i8> [[SHR10]], ptr @uc, align 8
2588 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
2589 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
2590 // CHECK-NEXT: [[SHR11:%.*]] = ashr <8 x i16> [[TMP15]], [[TMP14]]
2591 // CHECK-NEXT: store volatile <8 x i16> [[SHR11]], ptr @ss, align 8
2592 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
2593 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
2594 // CHECK-NEXT: [[SHR12:%.*]] = ashr <8 x i16> [[TMP17]], [[TMP16]]
2595 // CHECK-NEXT: store volatile <8 x i16> [[SHR12]], ptr @ss, align 8
2596 // CHECK-NEXT: [[TMP18:%.*]] = load volatile i32, ptr @cnt, align 4
2597 // CHECK-NEXT: [[SPLAT_SPLATINSERT13:%.*]] = insertelement <8 x i32> poison, i32 [[TMP18]], i64 0
2598 // CHECK-NEXT: [[SPLAT_SPLAT14:%.*]] = shufflevector <8 x i32> [[SPLAT_SPLATINSERT13]], <8 x i32> poison, <8 x i32> zeroinitializer
2599 // CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
2600 // CHECK-NEXT: [[SH_PROM15:%.*]] = trunc <8 x i32> [[SPLAT_SPLAT14]] to <8 x i16>
2601 // CHECK-NEXT: [[SHR16:%.*]] = ashr <8 x i16> [[TMP19]], [[SH_PROM15]]
2602 // CHECK-NEXT: store volatile <8 x i16> [[SHR16]], ptr @ss, align 8
2603 // CHECK-NEXT: [[TMP20:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
2604 // CHECK-NEXT: [[SHR17:%.*]] = ashr <8 x i16> [[TMP20]], splat (i16 5)
2605 // CHECK-NEXT: store volatile <8 x i16> [[SHR17]], ptr @ss, align 8
2606 // CHECK-NEXT: [[TMP21:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
2607 // CHECK-NEXT: [[TMP22:%.*]] = load volatile <8 x i16>, ptr @us, align 8
2608 // CHECK-NEXT: [[SHR18:%.*]] = lshr <8 x i16> [[TMP22]], [[TMP21]]
2609 // CHECK-NEXT: store volatile <8 x i16> [[SHR18]], ptr @us, align 8
2610 // CHECK-NEXT: [[TMP23:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
2611 // CHECK-NEXT: [[TMP24:%.*]] = load volatile <8 x i16>, ptr @us, align 8
2612 // CHECK-NEXT: [[SHR19:%.*]] = lshr <8 x i16> [[TMP24]], [[TMP23]]
2613 // CHECK-NEXT: store volatile <8 x i16> [[SHR19]], ptr @us, align 8
2614 // CHECK-NEXT: [[TMP25:%.*]] = load volatile i32, ptr @cnt, align 4
2615 // CHECK-NEXT: [[SPLAT_SPLATINSERT20:%.*]] = insertelement <8 x i32> poison, i32 [[TMP25]], i64 0
2616 // CHECK-NEXT: [[SPLAT_SPLAT21:%.*]] = shufflevector <8 x i32> [[SPLAT_SPLATINSERT20]], <8 x i32> poison, <8 x i32> zeroinitializer
2617 // CHECK-NEXT: [[TMP26:%.*]] = load volatile <8 x i16>, ptr @us, align 8
2618 // CHECK-NEXT: [[SH_PROM22:%.*]] = trunc <8 x i32> [[SPLAT_SPLAT21]] to <8 x i16>
2619 // CHECK-NEXT: [[SHR23:%.*]] = lshr <8 x i16> [[TMP26]], [[SH_PROM22]]
2620 // CHECK-NEXT: store volatile <8 x i16> [[SHR23]], ptr @us, align 8
2621 // CHECK-NEXT: [[TMP27:%.*]] = load volatile <8 x i16>, ptr @us, align 8
2622 // CHECK-NEXT: [[SHR24:%.*]] = lshr <8 x i16> [[TMP27]], splat (i16 5)
2623 // CHECK-NEXT: store volatile <8 x i16> [[SHR24]], ptr @us, align 8
2624 // CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
2625 // CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @si, align 8
2626 // CHECK-NEXT: [[SHR25:%.*]] = ashr <4 x i32> [[TMP29]], [[TMP28]]
2627 // CHECK-NEXT: store volatile <4 x i32> [[SHR25]], ptr @si, align 8
2628 // CHECK-NEXT: [[TMP30:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
2629 // CHECK-NEXT: [[TMP31:%.*]] = load volatile <4 x i32>, ptr @si, align 8
2630 // CHECK-NEXT: [[SHR26:%.*]] = ashr <4 x i32> [[TMP31]], [[TMP30]]
2631 // CHECK-NEXT: store volatile <4 x i32> [[SHR26]], ptr @si, align 8
2632 // CHECK-NEXT: [[TMP32:%.*]] = load volatile i32, ptr @cnt, align 4
2633 // CHECK-NEXT: [[SPLAT_SPLATINSERT27:%.*]] = insertelement <4 x i32> poison, i32 [[TMP32]], i64 0
2634 // CHECK-NEXT: [[SPLAT_SPLAT28:%.*]] = shufflevector <4 x i32> [[SPLAT_SPLATINSERT27]], <4 x i32> poison, <4 x i32> zeroinitializer
2635 // CHECK-NEXT: [[TMP33:%.*]] = load volatile <4 x i32>, ptr @si, align 8
2636 // CHECK-NEXT: [[SHR29:%.*]] = ashr <4 x i32> [[TMP33]], [[SPLAT_SPLAT28]]
2637 // CHECK-NEXT: store volatile <4 x i32> [[SHR29]], ptr @si, align 8
2638 // CHECK-NEXT: [[TMP34:%.*]] = load volatile <4 x i32>, ptr @si, align 8
2639 // CHECK-NEXT: [[SHR30:%.*]] = ashr <4 x i32> [[TMP34]], splat (i32 5)
2640 // CHECK-NEXT: store volatile <4 x i32> [[SHR30]], ptr @si, align 8
2641 // CHECK-NEXT: [[TMP35:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
2642 // CHECK-NEXT: [[TMP36:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
2643 // CHECK-NEXT: [[SHR31:%.*]] = lshr <4 x i32> [[TMP36]], [[TMP35]]
2644 // CHECK-NEXT: store volatile <4 x i32> [[SHR31]], ptr @ui, align 8
2645 // CHECK-NEXT: [[TMP37:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
2646 // CHECK-NEXT: [[TMP38:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
2647 // CHECK-NEXT: [[SHR32:%.*]] = lshr <4 x i32> [[TMP38]], [[TMP37]]
2648 // CHECK-NEXT: store volatile <4 x i32> [[SHR32]], ptr @ui, align 8
2649 // CHECK-NEXT: [[TMP39:%.*]] = load volatile i32, ptr @cnt, align 4
2650 // CHECK-NEXT: [[SPLAT_SPLATINSERT33:%.*]] = insertelement <4 x i32> poison, i32 [[TMP39]], i64 0
2651 // CHECK-NEXT: [[SPLAT_SPLAT34:%.*]] = shufflevector <4 x i32> [[SPLAT_SPLATINSERT33]], <4 x i32> poison, <4 x i32> zeroinitializer
2652 // CHECK-NEXT: [[TMP40:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
2653 // CHECK-NEXT: [[SHR35:%.*]] = lshr <4 x i32> [[TMP40]], [[SPLAT_SPLAT34]]
2654 // CHECK-NEXT: store volatile <4 x i32> [[SHR35]], ptr @ui, align 8
2655 // CHECK-NEXT: [[TMP41:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
2656 // CHECK-NEXT: [[SHR36:%.*]] = lshr <4 x i32> [[TMP41]], splat (i32 5)
2657 // CHECK-NEXT: store volatile <4 x i32> [[SHR36]], ptr @ui, align 8
2658 // CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
2659 // CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2660 // CHECK-NEXT: [[SHR37:%.*]] = ashr <2 x i64> [[TMP43]], [[TMP42]]
2661 // CHECK-NEXT: store volatile <2 x i64> [[SHR37]], ptr @sl, align 8
2662 // CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
2663 // CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2664 // CHECK-NEXT: [[SHR38:%.*]] = ashr <2 x i64> [[TMP45]], [[TMP44]]
2665 // CHECK-NEXT: store volatile <2 x i64> [[SHR38]], ptr @sl, align 8
2666 // CHECK-NEXT: [[TMP46:%.*]] = load volatile i32, ptr @cnt, align 4
2667 // CHECK-NEXT: [[SPLAT_SPLATINSERT39:%.*]] = insertelement <2 x i32> poison, i32 [[TMP46]], i64 0
2668 // CHECK-NEXT: [[SPLAT_SPLAT40:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT39]], <2 x i32> poison, <2 x i32> zeroinitializer
2669 // CHECK-NEXT: [[TMP47:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2670 // CHECK-NEXT: [[SH_PROM41:%.*]] = zext <2 x i32> [[SPLAT_SPLAT40]] to <2 x i64>
2671 // CHECK-NEXT: [[SHR42:%.*]] = ashr <2 x i64> [[TMP47]], [[SH_PROM41]]
2672 // CHECK-NEXT: store volatile <2 x i64> [[SHR42]], ptr @sl, align 8
2673 // CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2674 // CHECK-NEXT: [[SHR43:%.*]] = ashr <2 x i64> [[TMP48]], splat (i64 5)
2675 // CHECK-NEXT: store volatile <2 x i64> [[SHR43]], ptr @sl, align 8
2676 // CHECK-NEXT: [[TMP49:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
2677 // CHECK-NEXT: [[TMP50:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
2678 // CHECK-NEXT: [[SHR44:%.*]] = lshr <2 x i64> [[TMP50]], [[TMP49]]
2679 // CHECK-NEXT: store volatile <2 x i64> [[SHR44]], ptr @ul, align 8
2680 // CHECK-NEXT: [[TMP51:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
2681 // CHECK-NEXT: [[TMP52:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
2682 // CHECK-NEXT: [[SHR45:%.*]] = lshr <2 x i64> [[TMP52]], [[TMP51]]
2683 // CHECK-NEXT: store volatile <2 x i64> [[SHR45]], ptr @ul, align 8
2684 // CHECK-NEXT: [[TMP53:%.*]] = load volatile i32, ptr @cnt, align 4
2685 // CHECK-NEXT: [[SPLAT_SPLATINSERT46:%.*]] = insertelement <2 x i32> poison, i32 [[TMP53]], i64 0
2686 // CHECK-NEXT: [[SPLAT_SPLAT47:%.*]] = shufflevector <2 x i32> [[SPLAT_SPLATINSERT46]], <2 x i32> poison, <2 x i32> zeroinitializer
2687 // CHECK-NEXT: [[TMP54:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
2688 // CHECK-NEXT: [[SH_PROM48:%.*]] = zext <2 x i32> [[SPLAT_SPLAT47]] to <2 x i64>
2689 // CHECK-NEXT: [[SHR49:%.*]] = lshr <2 x i64> [[TMP54]], [[SH_PROM48]]
2690 // CHECK-NEXT: store volatile <2 x i64> [[SHR49]], ptr @ul, align 8
2691 // CHECK-NEXT: [[TMP55:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
2692 // CHECK-NEXT: [[SHR50:%.*]] = lshr <2 x i64> [[TMP55]], splat (i64 5)
2693 // CHECK-NEXT: store volatile <2 x i64> [[SHR50]], ptr @ul, align 8
2694 // CHECK-NEXT: ret void
2695 //
2696 void test_sr_assign(void) {
2697
2698 sc >>= sc2;
2699 sc >>= uc2;
2700 sc >>= cnt;
2701 sc >>= 5;
2702 uc >>= sc2;
2703 uc >>= uc2;
2704 uc >>= cnt;
2705 uc >>= 5;
2706
2707 ss >>= ss2;
2708 ss >>= us2;
2709 ss >>= cnt;
2710 ss >>= 5;
2711 us >>= ss2;
2712 us >>= us2;
2713 us >>= cnt;
2714 us >>= 5;
2715
2716 si >>= si2;
2717 si >>= ui2;
2718 si >>= cnt;
2719 si >>= 5;
2720 ui >>= si2;
2721 ui >>= ui2;
2722 ui >>= cnt;
2723 ui >>= 5;
2724
2725 sl >>= sl2;
2726 sl >>= ul2;
2727 sl >>= cnt;
2728 sl >>= 5;
2729 ul >>= sl2;
2730 ul >>= ul2;
2731 ul >>= cnt;
2732 ul >>= 5;
2733 }
2734
2735
2736 // CHECK-LABEL: define dso_local void @test_cmpeq(
2737 // CHECK-SAME: ) #[[ATTR0]] {
2738 // CHECK-NEXT: [[ENTRY:.*:]]
2739 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
2740 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
2741 // CHECK-NEXT: [[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
2742 // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
2743 // CHECK-NEXT: store volatile <16 x i8> [[SEXT]], ptr @bc, align 8
2744 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
2745 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
2746 // CHECK-NEXT: [[CMP1:%.*]] = icmp eq <16 x i8> [[TMP2]], [[TMP3]]
2747 // CHECK-NEXT: [[SEXT2:%.*]] = sext <16 x i1> [[CMP1]] to <16 x i8>
2748 // CHECK-NEXT: store volatile <16 x i8> [[SEXT2]], ptr @bc, align 8
2749 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
2750 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
2751 // CHECK-NEXT: [[CMP3:%.*]] = icmp eq <16 x i8> [[TMP4]], [[TMP5]]
2752 // CHECK-NEXT: [[SEXT4:%.*]] = sext <16 x i1> [[CMP3]] to <16 x i8>
2753 // CHECK-NEXT: store volatile <16 x i8> [[SEXT4]], ptr @bc, align 8
2754 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
2755 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
2756 // CHECK-NEXT: [[CMP5:%.*]] = icmp eq <16 x i8> [[TMP6]], [[TMP7]]
2757 // CHECK-NEXT: [[SEXT6:%.*]] = sext <16 x i1> [[CMP5]] to <16 x i8>
2758 // CHECK-NEXT: store volatile <16 x i8> [[SEXT6]], ptr @bc, align 8
2759 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
2760 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
2761 // CHECK-NEXT: [[CMP7:%.*]] = icmp eq <16 x i8> [[TMP8]], [[TMP9]]
2762 // CHECK-NEXT: [[SEXT8:%.*]] = sext <16 x i1> [[CMP7]] to <16 x i8>
2763 // CHECK-NEXT: store volatile <16 x i8> [[SEXT8]], ptr @bc, align 8
2764 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
2765 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
2766 // CHECK-NEXT: [[CMP9:%.*]] = icmp eq <16 x i8> [[TMP10]], [[TMP11]]
2767 // CHECK-NEXT: [[SEXT10:%.*]] = sext <16 x i1> [[CMP9]] to <16 x i8>
2768 // CHECK-NEXT: store volatile <16 x i8> [[SEXT10]], ptr @bc, align 8
2769 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
2770 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
2771 // CHECK-NEXT: [[CMP11:%.*]] = icmp eq <16 x i8> [[TMP12]], [[TMP13]]
2772 // CHECK-NEXT: [[SEXT12:%.*]] = sext <16 x i1> [[CMP11]] to <16 x i8>
2773 // CHECK-NEXT: store volatile <16 x i8> [[SEXT12]], ptr @bc, align 8
2774 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
2775 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
2776 // CHECK-NEXT: [[CMP13:%.*]] = icmp eq <8 x i16> [[TMP14]], [[TMP15]]
2777 // CHECK-NEXT: [[SEXT14:%.*]] = sext <8 x i1> [[CMP13]] to <8 x i16>
2778 // CHECK-NEXT: store volatile <8 x i16> [[SEXT14]], ptr @bs, align 8
2779 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
2780 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
2781 // CHECK-NEXT: [[CMP15:%.*]] = icmp eq <8 x i16> [[TMP16]], [[TMP17]]
2782 // CHECK-NEXT: [[SEXT16:%.*]] = sext <8 x i1> [[CMP15]] to <8 x i16>
2783 // CHECK-NEXT: store volatile <8 x i16> [[SEXT16]], ptr @bs, align 8
2784 // CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
2785 // CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
2786 // CHECK-NEXT: [[CMP17:%.*]] = icmp eq <8 x i16> [[TMP18]], [[TMP19]]
2787 // CHECK-NEXT: [[SEXT18:%.*]] = sext <8 x i1> [[CMP17]] to <8 x i16>
2788 // CHECK-NEXT: store volatile <8 x i16> [[SEXT18]], ptr @bs, align 8
2789 // CHECK-NEXT: [[TMP20:%.*]] = load volatile <8 x i16>, ptr @us, align 8
2790 // CHECK-NEXT: [[TMP21:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
2791 // CHECK-NEXT: [[CMP19:%.*]] = icmp eq <8 x i16> [[TMP20]], [[TMP21]]
2792 // CHECK-NEXT: [[SEXT20:%.*]] = sext <8 x i1> [[CMP19]] to <8 x i16>
2793 // CHECK-NEXT: store volatile <8 x i16> [[SEXT20]], ptr @bs, align 8
2794 // CHECK-NEXT: [[TMP22:%.*]] = load volatile <8 x i16>, ptr @us, align 8
2795 // CHECK-NEXT: [[TMP23:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
2796 // CHECK-NEXT: [[CMP21:%.*]] = icmp eq <8 x i16> [[TMP22]], [[TMP23]]
2797 // CHECK-NEXT: [[SEXT22:%.*]] = sext <8 x i1> [[CMP21]] to <8 x i16>
2798 // CHECK-NEXT: store volatile <8 x i16> [[SEXT22]], ptr @bs, align 8
2799 // CHECK-NEXT: [[TMP24:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
2800 // CHECK-NEXT: [[TMP25:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
2801 // CHECK-NEXT: [[CMP23:%.*]] = icmp eq <8 x i16> [[TMP24]], [[TMP25]]
2802 // CHECK-NEXT: [[SEXT24:%.*]] = sext <8 x i1> [[CMP23]] to <8 x i16>
2803 // CHECK-NEXT: store volatile <8 x i16> [[SEXT24]], ptr @bs, align 8
2804 // CHECK-NEXT: [[TMP26:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
2805 // CHECK-NEXT: [[TMP27:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
2806 // CHECK-NEXT: [[CMP25:%.*]] = icmp eq <8 x i16> [[TMP26]], [[TMP27]]
2807 // CHECK-NEXT: [[SEXT26:%.*]] = sext <8 x i1> [[CMP25]] to <8 x i16>
2808 // CHECK-NEXT: store volatile <8 x i16> [[SEXT26]], ptr @bs, align 8
2809 // CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @si, align 8
2810 // CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
2811 // CHECK-NEXT: [[CMP27:%.*]] = icmp eq <4 x i32> [[TMP28]], [[TMP29]]
2812 // CHECK-NEXT: [[SEXT28:%.*]] = sext <4 x i1> [[CMP27]] to <4 x i32>
2813 // CHECK-NEXT: store volatile <4 x i32> [[SEXT28]], ptr @bi, align 8
2814 // CHECK-NEXT: [[TMP30:%.*]] = load volatile <4 x i32>, ptr @si, align 8
2815 // CHECK-NEXT: [[TMP31:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
2816 // CHECK-NEXT: [[CMP29:%.*]] = icmp eq <4 x i32> [[TMP30]], [[TMP31]]
2817 // CHECK-NEXT: [[SEXT30:%.*]] = sext <4 x i1> [[CMP29]] to <4 x i32>
2818 // CHECK-NEXT: store volatile <4 x i32> [[SEXT30]], ptr @bi, align 8
2819 // CHECK-NEXT: [[TMP32:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
2820 // CHECK-NEXT: [[TMP33:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
2821 // CHECK-NEXT: [[CMP31:%.*]] = icmp eq <4 x i32> [[TMP32]], [[TMP33]]
2822 // CHECK-NEXT: [[SEXT32:%.*]] = sext <4 x i1> [[CMP31]] to <4 x i32>
2823 // CHECK-NEXT: store volatile <4 x i32> [[SEXT32]], ptr @bi, align 8
2824 // CHECK-NEXT: [[TMP34:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
2825 // CHECK-NEXT: [[TMP35:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
2826 // CHECK-NEXT: [[CMP33:%.*]] = icmp eq <4 x i32> [[TMP34]], [[TMP35]]
2827 // CHECK-NEXT: [[SEXT34:%.*]] = sext <4 x i1> [[CMP33]] to <4 x i32>
2828 // CHECK-NEXT: store volatile <4 x i32> [[SEXT34]], ptr @bi, align 8
2829 // CHECK-NEXT: [[TMP36:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
2830 // CHECK-NEXT: [[TMP37:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
2831 // CHECK-NEXT: [[CMP35:%.*]] = icmp eq <4 x i32> [[TMP36]], [[TMP37]]
2832 // CHECK-NEXT: [[SEXT36:%.*]] = sext <4 x i1> [[CMP35]] to <4 x i32>
2833 // CHECK-NEXT: store volatile <4 x i32> [[SEXT36]], ptr @bi, align 8
2834 // CHECK-NEXT: [[TMP38:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
2835 // CHECK-NEXT: [[TMP39:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
2836 // CHECK-NEXT: [[CMP37:%.*]] = icmp eq <4 x i32> [[TMP38]], [[TMP39]]
2837 // CHECK-NEXT: [[SEXT38:%.*]] = sext <4 x i1> [[CMP37]] to <4 x i32>
2838 // CHECK-NEXT: store volatile <4 x i32> [[SEXT38]], ptr @bi, align 8
2839 // CHECK-NEXT: [[TMP40:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
2840 // CHECK-NEXT: [[TMP41:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
2841 // CHECK-NEXT: [[CMP39:%.*]] = icmp eq <4 x i32> [[TMP40]], [[TMP41]]
2842 // CHECK-NEXT: [[SEXT40:%.*]] = sext <4 x i1> [[CMP39]] to <4 x i32>
2843 // CHECK-NEXT: store volatile <4 x i32> [[SEXT40]], ptr @bi, align 8
2844 // CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2845 // CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
2846 // CHECK-NEXT: [[CMP41:%.*]] = icmp eq <2 x i64> [[TMP42]], [[TMP43]]
2847 // CHECK-NEXT: [[SEXT42:%.*]] = sext <2 x i1> [[CMP41]] to <2 x i64>
2848 // CHECK-NEXT: store volatile <2 x i64> [[SEXT42]], ptr @bl, align 8
2849 // CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2850 // CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
2851 // CHECK-NEXT: [[CMP43:%.*]] = icmp eq <2 x i64> [[TMP44]], [[TMP45]]
2852 // CHECK-NEXT: [[SEXT44:%.*]] = sext <2 x i1> [[CMP43]] to <2 x i64>
2853 // CHECK-NEXT: store volatile <2 x i64> [[SEXT44]], ptr @bl, align 8
2854 // CHECK-NEXT: [[TMP46:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
2855 // CHECK-NEXT: [[TMP47:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
2856 // CHECK-NEXT: [[CMP45:%.*]] = icmp eq <2 x i64> [[TMP46]], [[TMP47]]
2857 // CHECK-NEXT: [[SEXT46:%.*]] = sext <2 x i1> [[CMP45]] to <2 x i64>
2858 // CHECK-NEXT: store volatile <2 x i64> [[SEXT46]], ptr @bl, align 8
2859 // CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
2860 // CHECK-NEXT: [[TMP49:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
2861 // CHECK-NEXT: [[CMP47:%.*]] = icmp eq <2 x i64> [[TMP48]], [[TMP49]]
2862 // CHECK-NEXT: [[SEXT48:%.*]] = sext <2 x i1> [[CMP47]] to <2 x i64>
2863 // CHECK-NEXT: store volatile <2 x i64> [[SEXT48]], ptr @bl, align 8
2864 // CHECK-NEXT: [[TMP50:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
2865 // CHECK-NEXT: [[TMP51:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
2866 // CHECK-NEXT: [[CMP49:%.*]] = icmp eq <2 x i64> [[TMP50]], [[TMP51]]
2867 // CHECK-NEXT: [[SEXT50:%.*]] = sext <2 x i1> [[CMP49]] to <2 x i64>
2868 // CHECK-NEXT: store volatile <2 x i64> [[SEXT50]], ptr @bl, align 8
2869 // CHECK-NEXT: [[TMP52:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
2870 // CHECK-NEXT: [[TMP53:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
2871 // CHECK-NEXT: [[CMP51:%.*]] = icmp eq <2 x i64> [[TMP52]], [[TMP53]]
2872 // CHECK-NEXT: [[SEXT52:%.*]] = sext <2 x i1> [[CMP51]] to <2 x i64>
2873 // CHECK-NEXT: store volatile <2 x i64> [[SEXT52]], ptr @bl, align 8
2874 // CHECK-NEXT: [[TMP54:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
2875 // CHECK-NEXT: [[TMP55:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
2876 // CHECK-NEXT: [[CMP53:%.*]] = icmp eq <2 x i64> [[TMP54]], [[TMP55]]
2877 // CHECK-NEXT: [[SEXT54:%.*]] = sext <2 x i1> [[CMP53]] to <2 x i64>
2878 // CHECK-NEXT: store volatile <2 x i64> [[SEXT54]], ptr @bl, align 8
2879 // CHECK-NEXT: [[TMP56:%.*]] = load volatile <2 x double>, ptr @fd, align 8
2880 // CHECK-NEXT: [[TMP57:%.*]] = load volatile <2 x double>, ptr @fd2, align 8
2881 // CHECK-NEXT: [[CMP55:%.*]] = fcmp oeq <2 x double> [[TMP56]], [[TMP57]]
2882 // CHECK-NEXT: [[SEXT56:%.*]] = sext <2 x i1> [[CMP55]] to <2 x i64>
2883 // CHECK-NEXT: store volatile <2 x i64> [[SEXT56]], ptr @bl, align 8
2884 // CHECK-NEXT: ret void
2885 //
2886 void test_cmpeq(void) {
2887
2888 bc = sc == sc2;
2889 bc = sc == bc2;
2890 bc = bc == sc2;
2891 bc = uc == uc2;
2892 bc = uc == bc2;
2893 bc = bc == uc2;
2894 bc = bc == bc2;
2895
2896 bs = ss == ss2;
2897 bs = ss == bs2;
2898 bs = bs == ss2;
2899 bs = us == us2;
2900 bs = us == bs2;
2901 bs = bs == us2;
2902 bs = bs == bs2;
2903
2904 bi = si == si2;
2905 bi = si == bi2;
2906 bi = bi == si2;
2907 bi = ui == ui2;
2908 bi = ui == bi2;
2909 bi = bi == ui2;
2910 bi = bi == bi2;
2911
2912 bl = sl == sl2;
2913 bl = sl == bl2;
2914 bl = bl == sl2;
2915 bl = ul == ul2;
2916 bl = ul == bl2;
2917 bl = bl == ul2;
2918 bl = bl == bl2;
2919
2920 bl = fd == fd2;
2921 }
2922
2923 // CHECK-LABEL: define dso_local void @test_cmpne(
2924 // CHECK-SAME: ) #[[ATTR0]] {
2925 // CHECK-NEXT: [[ENTRY:.*:]]
2926 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
2927 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
2928 // CHECK-NEXT: [[CMP:%.*]] = icmp ne <16 x i8> [[TMP0]], [[TMP1]]
2929 // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
2930 // CHECK-NEXT: store volatile <16 x i8> [[SEXT]], ptr @bc, align 8
2931 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
2932 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
2933 // CHECK-NEXT: [[CMP1:%.*]] = icmp ne <16 x i8> [[TMP2]], [[TMP3]]
2934 // CHECK-NEXT: [[SEXT2:%.*]] = sext <16 x i1> [[CMP1]] to <16 x i8>
2935 // CHECK-NEXT: store volatile <16 x i8> [[SEXT2]], ptr @bc, align 8
2936 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
2937 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
2938 // CHECK-NEXT: [[CMP3:%.*]] = icmp ne <16 x i8> [[TMP4]], [[TMP5]]
2939 // CHECK-NEXT: [[SEXT4:%.*]] = sext <16 x i1> [[CMP3]] to <16 x i8>
2940 // CHECK-NEXT: store volatile <16 x i8> [[SEXT4]], ptr @bc, align 8
2941 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
2942 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
2943 // CHECK-NEXT: [[CMP5:%.*]] = icmp ne <16 x i8> [[TMP6]], [[TMP7]]
2944 // CHECK-NEXT: [[SEXT6:%.*]] = sext <16 x i1> [[CMP5]] to <16 x i8>
2945 // CHECK-NEXT: store volatile <16 x i8> [[SEXT6]], ptr @bc, align 8
2946 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
2947 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
2948 // CHECK-NEXT: [[CMP7:%.*]] = icmp ne <16 x i8> [[TMP8]], [[TMP9]]
2949 // CHECK-NEXT: [[SEXT8:%.*]] = sext <16 x i1> [[CMP7]] to <16 x i8>
2950 // CHECK-NEXT: store volatile <16 x i8> [[SEXT8]], ptr @bc, align 8
2951 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
2952 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
2953 // CHECK-NEXT: [[CMP9:%.*]] = icmp ne <16 x i8> [[TMP10]], [[TMP11]]
2954 // CHECK-NEXT: [[SEXT10:%.*]] = sext <16 x i1> [[CMP9]] to <16 x i8>
2955 // CHECK-NEXT: store volatile <16 x i8> [[SEXT10]], ptr @bc, align 8
2956 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
2957 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
2958 // CHECK-NEXT: [[CMP11:%.*]] = icmp ne <16 x i8> [[TMP12]], [[TMP13]]
2959 // CHECK-NEXT: [[SEXT12:%.*]] = sext <16 x i1> [[CMP11]] to <16 x i8>
2960 // CHECK-NEXT: store volatile <16 x i8> [[SEXT12]], ptr @bc, align 8
2961 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
2962 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
2963 // CHECK-NEXT: [[CMP13:%.*]] = icmp ne <8 x i16> [[TMP14]], [[TMP15]]
2964 // CHECK-NEXT: [[SEXT14:%.*]] = sext <8 x i1> [[CMP13]] to <8 x i16>
2965 // CHECK-NEXT: store volatile <8 x i16> [[SEXT14]], ptr @bs, align 8
2966 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
2967 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
2968 // CHECK-NEXT: [[CMP15:%.*]] = icmp ne <8 x i16> [[TMP16]], [[TMP17]]
2969 // CHECK-NEXT: [[SEXT16:%.*]] = sext <8 x i1> [[CMP15]] to <8 x i16>
2970 // CHECK-NEXT: store volatile <8 x i16> [[SEXT16]], ptr @bs, align 8
2971 // CHECK-NEXT: [[TMP18:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
2972 // CHECK-NEXT: [[TMP19:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
2973 // CHECK-NEXT: [[CMP17:%.*]] = icmp ne <8 x i16> [[TMP18]], [[TMP19]]
2974 // CHECK-NEXT: [[SEXT18:%.*]] = sext <8 x i1> [[CMP17]] to <8 x i16>
2975 // CHECK-NEXT: store volatile <8 x i16> [[SEXT18]], ptr @bs, align 8
2976 // CHECK-NEXT: [[TMP20:%.*]] = load volatile <8 x i16>, ptr @us, align 8
2977 // CHECK-NEXT: [[TMP21:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
2978 // CHECK-NEXT: [[CMP19:%.*]] = icmp ne <8 x i16> [[TMP20]], [[TMP21]]
2979 // CHECK-NEXT: [[SEXT20:%.*]] = sext <8 x i1> [[CMP19]] to <8 x i16>
2980 // CHECK-NEXT: store volatile <8 x i16> [[SEXT20]], ptr @bs, align 8
2981 // CHECK-NEXT: [[TMP22:%.*]] = load volatile <8 x i16>, ptr @us, align 8
2982 // CHECK-NEXT: [[TMP23:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
2983 // CHECK-NEXT: [[CMP21:%.*]] = icmp ne <8 x i16> [[TMP22]], [[TMP23]]
2984 // CHECK-NEXT: [[SEXT22:%.*]] = sext <8 x i1> [[CMP21]] to <8 x i16>
2985 // CHECK-NEXT: store volatile <8 x i16> [[SEXT22]], ptr @bs, align 8
2986 // CHECK-NEXT: [[TMP24:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
2987 // CHECK-NEXT: [[TMP25:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
2988 // CHECK-NEXT: [[CMP23:%.*]] = icmp ne <8 x i16> [[TMP24]], [[TMP25]]
2989 // CHECK-NEXT: [[SEXT24:%.*]] = sext <8 x i1> [[CMP23]] to <8 x i16>
2990 // CHECK-NEXT: store volatile <8 x i16> [[SEXT24]], ptr @bs, align 8
2991 // CHECK-NEXT: [[TMP26:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
2992 // CHECK-NEXT: [[TMP27:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
2993 // CHECK-NEXT: [[CMP25:%.*]] = icmp ne <8 x i16> [[TMP26]], [[TMP27]]
2994 // CHECK-NEXT: [[SEXT26:%.*]] = sext <8 x i1> [[CMP25]] to <8 x i16>
2995 // CHECK-NEXT: store volatile <8 x i16> [[SEXT26]], ptr @bs, align 8
2996 // CHECK-NEXT: [[TMP28:%.*]] = load volatile <4 x i32>, ptr @si, align 8
2997 // CHECK-NEXT: [[TMP29:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
2998 // CHECK-NEXT: [[CMP27:%.*]] = icmp ne <4 x i32> [[TMP28]], [[TMP29]]
2999 // CHECK-NEXT: [[SEXT28:%.*]] = sext <4 x i1> [[CMP27]] to <4 x i32>
3000 // CHECK-NEXT: store volatile <4 x i32> [[SEXT28]], ptr @bi, align 8
3001 // CHECK-NEXT: [[TMP30:%.*]] = load volatile <4 x i32>, ptr @si, align 8
3002 // CHECK-NEXT: [[TMP31:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
3003 // CHECK-NEXT: [[CMP29:%.*]] = icmp ne <4 x i32> [[TMP30]], [[TMP31]]
3004 // CHECK-NEXT: [[SEXT30:%.*]] = sext <4 x i1> [[CMP29]] to <4 x i32>
3005 // CHECK-NEXT: store volatile <4 x i32> [[SEXT30]], ptr @bi, align 8
3006 // CHECK-NEXT: [[TMP32:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
3007 // CHECK-NEXT: [[TMP33:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
3008 // CHECK-NEXT: [[CMP31:%.*]] = icmp ne <4 x i32> [[TMP32]], [[TMP33]]
3009 // CHECK-NEXT: [[SEXT32:%.*]] = sext <4 x i1> [[CMP31]] to <4 x i32>
3010 // CHECK-NEXT: store volatile <4 x i32> [[SEXT32]], ptr @bi, align 8
3011 // CHECK-NEXT: [[TMP34:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
3012 // CHECK-NEXT: [[TMP35:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
3013 // CHECK-NEXT: [[CMP33:%.*]] = icmp ne <4 x i32> [[TMP34]], [[TMP35]]
3014 // CHECK-NEXT: [[SEXT34:%.*]] = sext <4 x i1> [[CMP33]] to <4 x i32>
3015 // CHECK-NEXT: store volatile <4 x i32> [[SEXT34]], ptr @bi, align 8
3016 // CHECK-NEXT: [[TMP36:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
3017 // CHECK-NEXT: [[TMP37:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
3018 // CHECK-NEXT: [[CMP35:%.*]] = icmp ne <4 x i32> [[TMP36]], [[TMP37]]
3019 // CHECK-NEXT: [[SEXT36:%.*]] = sext <4 x i1> [[CMP35]] to <4 x i32>
3020 // CHECK-NEXT: store volatile <4 x i32> [[SEXT36]], ptr @bi, align 8
3021 // CHECK-NEXT: [[TMP38:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
3022 // CHECK-NEXT: [[TMP39:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
3023 // CHECK-NEXT: [[CMP37:%.*]] = icmp ne <4 x i32> [[TMP38]], [[TMP39]]
3024 // CHECK-NEXT: [[SEXT38:%.*]] = sext <4 x i1> [[CMP37]] to <4 x i32>
3025 // CHECK-NEXT: store volatile <4 x i32> [[SEXT38]], ptr @bi, align 8
3026 // CHECK-NEXT: [[TMP40:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
3027 // CHECK-NEXT: [[TMP41:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
3028 // CHECK-NEXT: [[CMP39:%.*]] = icmp ne <4 x i32> [[TMP40]], [[TMP41]]
3029 // CHECK-NEXT: [[SEXT40:%.*]] = sext <4 x i1> [[CMP39]] to <4 x i32>
3030 // CHECK-NEXT: store volatile <4 x i32> [[SEXT40]], ptr @bi, align 8
3031 // CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
3032 // CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
3033 // CHECK-NEXT: [[CMP41:%.*]] = icmp ne <2 x i64> [[TMP42]], [[TMP43]]
3034 // CHECK-NEXT: [[SEXT42:%.*]] = sext <2 x i1> [[CMP41]] to <2 x i64>
3035 // CHECK-NEXT: store volatile <2 x i64> [[SEXT42]], ptr @bl, align 8
3036 // CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
3037 // CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
3038 // CHECK-NEXT: [[CMP43:%.*]] = icmp ne <2 x i64> [[TMP44]], [[TMP45]]
3039 // CHECK-NEXT: [[SEXT44:%.*]] = sext <2 x i1> [[CMP43]] to <2 x i64>
3040 // CHECK-NEXT: store volatile <2 x i64> [[SEXT44]], ptr @bl, align 8
3041 // CHECK-NEXT: [[TMP46:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
3042 // CHECK-NEXT: [[TMP47:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
3043 // CHECK-NEXT: [[CMP45:%.*]] = icmp ne <2 x i64> [[TMP46]], [[TMP47]]
3044 // CHECK-NEXT: [[SEXT46:%.*]] = sext <2 x i1> [[CMP45]] to <2 x i64>
3045 // CHECK-NEXT: store volatile <2 x i64> [[SEXT46]], ptr @bl, align 8
3046 // CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
3047 // CHECK-NEXT: [[TMP49:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
3048 // CHECK-NEXT: [[CMP47:%.*]] = icmp ne <2 x i64> [[TMP48]], [[TMP49]]
3049 // CHECK-NEXT: [[SEXT48:%.*]] = sext <2 x i1> [[CMP47]] to <2 x i64>
3050 // CHECK-NEXT: store volatile <2 x i64> [[SEXT48]], ptr @bl, align 8
3051 // CHECK-NEXT: [[TMP50:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
3052 // CHECK-NEXT: [[TMP51:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
3053 // CHECK-NEXT: [[CMP49:%.*]] = icmp ne <2 x i64> [[TMP50]], [[TMP51]]
3054 // CHECK-NEXT: [[SEXT50:%.*]] = sext <2 x i1> [[CMP49]] to <2 x i64>
3055 // CHECK-NEXT: store volatile <2 x i64> [[SEXT50]], ptr @bl, align 8
3056 // CHECK-NEXT: [[TMP52:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
3057 // CHECK-NEXT: [[TMP53:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
3058 // CHECK-NEXT: [[CMP51:%.*]] = icmp ne <2 x i64> [[TMP52]], [[TMP53]]
3059 // CHECK-NEXT: [[SEXT52:%.*]] = sext <2 x i1> [[CMP51]] to <2 x i64>
3060 // CHECK-NEXT: store volatile <2 x i64> [[SEXT52]], ptr @bl, align 8
3061 // CHECK-NEXT: [[TMP54:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
3062 // CHECK-NEXT: [[TMP55:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
3063 // CHECK-NEXT: [[CMP53:%.*]] = icmp ne <2 x i64> [[TMP54]], [[TMP55]]
3064 // CHECK-NEXT: [[SEXT54:%.*]] = sext <2 x i1> [[CMP53]] to <2 x i64>
3065 // CHECK-NEXT: store volatile <2 x i64> [[SEXT54]], ptr @bl, align 8
3066 // CHECK-NEXT: [[TMP56:%.*]] = load volatile <2 x double>, ptr @fd, align 8
3067 // CHECK-NEXT: [[TMP57:%.*]] = load volatile <2 x double>, ptr @fd2, align 8
3068 // CHECK-NEXT: [[CMP55:%.*]] = fcmp une <2 x double> [[TMP56]], [[TMP57]]
3069 // CHECK-NEXT: [[SEXT56:%.*]] = sext <2 x i1> [[CMP55]] to <2 x i64>
3070 // CHECK-NEXT: store volatile <2 x i64> [[SEXT56]], ptr @bl, align 8
3071 // CHECK-NEXT: ret void
3072 //
3073 void test_cmpne(void) {
3074
3075 bc = sc != sc2;
3076 bc = sc != bc2;
3077 bc = bc != sc2;
3078 bc = uc != uc2;
3079 bc = uc != bc2;
3080 bc = bc != uc2;
3081 bc = bc != bc2;
3082
3083 bs = ss != ss2;
3084 bs = ss != bs2;
3085 bs = bs != ss2;
3086 bs = us != us2;
3087 bs = us != bs2;
3088 bs = bs != us2;
3089 bs = bs != bs2;
3090
3091 bi = si != si2;
3092 bi = si != bi2;
3093 bi = bi != si2;
3094 bi = ui != ui2;
3095 bi = ui != bi2;
3096 bi = bi != ui2;
3097 bi = bi != bi2;
3098
3099 bl = sl != sl2;
3100 bl = sl != bl2;
3101 bl = bl != sl2;
3102 bl = ul != ul2;
3103 bl = ul != bl2;
3104 bl = bl != ul2;
3105 bl = bl != bl2;
3106
3107 bl = fd != fd2;
3108 }
3109
3110 // CHECK-LABEL: define dso_local void @test_cmpge(
3111 // CHECK-SAME: ) #[[ATTR0]] {
3112 // CHECK-NEXT: [[ENTRY:.*:]]
3113 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
3114 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
3115 // CHECK-NEXT: [[CMP:%.*]] = icmp sge <16 x i8> [[TMP0]], [[TMP1]]
3116 // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
3117 // CHECK-NEXT: store volatile <16 x i8> [[SEXT]], ptr @bc, align 8
3118 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
3119 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
3120 // CHECK-NEXT: [[CMP1:%.*]] = icmp uge <16 x i8> [[TMP2]], [[TMP3]]
3121 // CHECK-NEXT: [[SEXT2:%.*]] = sext <16 x i1> [[CMP1]] to <16 x i8>
3122 // CHECK-NEXT: store volatile <16 x i8> [[SEXT2]], ptr @bc, align 8
3123 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
3124 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
3125 // CHECK-NEXT: [[CMP3:%.*]] = icmp uge <16 x i8> [[TMP4]], [[TMP5]]
3126 // CHECK-NEXT: [[SEXT4:%.*]] = sext <16 x i1> [[CMP3]] to <16 x i8>
3127 // CHECK-NEXT: store volatile <16 x i8> [[SEXT4]], ptr @bc, align 8
3128 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
3129 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
3130 // CHECK-NEXT: [[CMP5:%.*]] = icmp sge <8 x i16> [[TMP6]], [[TMP7]]
3131 // CHECK-NEXT: [[SEXT6:%.*]] = sext <8 x i1> [[CMP5]] to <8 x i16>
3132 // CHECK-NEXT: store volatile <8 x i16> [[SEXT6]], ptr @bs, align 8
3133 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <8 x i16>, ptr @us, align 8
3134 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
3135 // CHECK-NEXT: [[CMP7:%.*]] = icmp uge <8 x i16> [[TMP8]], [[TMP9]]
3136 // CHECK-NEXT: [[SEXT8:%.*]] = sext <8 x i1> [[CMP7]] to <8 x i16>
3137 // CHECK-NEXT: store volatile <8 x i16> [[SEXT8]], ptr @bs, align 8
3138 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
3139 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
3140 // CHECK-NEXT: [[CMP9:%.*]] = icmp uge <8 x i16> [[TMP10]], [[TMP11]]
3141 // CHECK-NEXT: [[SEXT10:%.*]] = sext <8 x i1> [[CMP9]] to <8 x i16>
3142 // CHECK-NEXT: store volatile <8 x i16> [[SEXT10]], ptr @bs, align 8
3143 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <4 x i32>, ptr @si, align 8
3144 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
3145 // CHECK-NEXT: [[CMP11:%.*]] = icmp sge <4 x i32> [[TMP12]], [[TMP13]]
3146 // CHECK-NEXT: [[SEXT12:%.*]] = sext <4 x i1> [[CMP11]] to <4 x i32>
3147 // CHECK-NEXT: store volatile <4 x i32> [[SEXT12]], ptr @bi, align 8
3148 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
3149 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
3150 // CHECK-NEXT: [[CMP13:%.*]] = icmp uge <4 x i32> [[TMP14]], [[TMP15]]
3151 // CHECK-NEXT: [[SEXT14:%.*]] = sext <4 x i1> [[CMP13]] to <4 x i32>
3152 // CHECK-NEXT: store volatile <4 x i32> [[SEXT14]], ptr @bi, align 8
3153 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
3154 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
3155 // CHECK-NEXT: [[CMP15:%.*]] = icmp uge <4 x i32> [[TMP16]], [[TMP17]]
3156 // CHECK-NEXT: [[SEXT16:%.*]] = sext <4 x i1> [[CMP15]] to <4 x i32>
3157 // CHECK-NEXT: store volatile <4 x i32> [[SEXT16]], ptr @bi, align 8
3158 // CHECK-NEXT: [[TMP18:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
3159 // CHECK-NEXT: [[TMP19:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
3160 // CHECK-NEXT: [[CMP17:%.*]] = icmp sge <2 x i64> [[TMP18]], [[TMP19]]
3161 // CHECK-NEXT: [[SEXT18:%.*]] = sext <2 x i1> [[CMP17]] to <2 x i64>
3162 // CHECK-NEXT: store volatile <2 x i64> [[SEXT18]], ptr @bl, align 8
3163 // CHECK-NEXT: [[TMP20:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
3164 // CHECK-NEXT: [[TMP21:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
3165 // CHECK-NEXT: [[CMP19:%.*]] = icmp uge <2 x i64> [[TMP20]], [[TMP21]]
3166 // CHECK-NEXT: [[SEXT20:%.*]] = sext <2 x i1> [[CMP19]] to <2 x i64>
3167 // CHECK-NEXT: store volatile <2 x i64> [[SEXT20]], ptr @bl, align 8
3168 // CHECK-NEXT: [[TMP22:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
3169 // CHECK-NEXT: [[TMP23:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
3170 // CHECK-NEXT: [[CMP21:%.*]] = icmp uge <2 x i64> [[TMP22]], [[TMP23]]
3171 // CHECK-NEXT: [[SEXT22:%.*]] = sext <2 x i1> [[CMP21]] to <2 x i64>
3172 // CHECK-NEXT: store volatile <2 x i64> [[SEXT22]], ptr @bl, align 8
3173 // CHECK-NEXT: [[TMP24:%.*]] = load volatile <2 x double>, ptr @fd, align 8
3174 // CHECK-NEXT: [[TMP25:%.*]] = load volatile <2 x double>, ptr @fd2, align 8
3175 // CHECK-NEXT: [[CMP23:%.*]] = fcmp oge <2 x double> [[TMP24]], [[TMP25]]
3176 // CHECK-NEXT: [[SEXT24:%.*]] = sext <2 x i1> [[CMP23]] to <2 x i64>
3177 // CHECK-NEXT: store volatile <2 x i64> [[SEXT24]], ptr @bl, align 8
3178 // CHECK-NEXT: ret void
3179 //
3180 void test_cmpge(void) {
3181
3182 bc = sc >= sc2;
3183 bc = uc >= uc2;
3184 bc = bc >= bc2;
3185
3186 bs = ss >= ss2;
3187 bs = us >= us2;
3188 bs = bs >= bs2;
3189
3190 bi = si >= si2;
3191 bi = ui >= ui2;
3192 bi = bi >= bi2;
3193
3194 bl = sl >= sl2;
3195 bl = ul >= ul2;
3196 bl = bl >= bl2;
3197
3198 bl = fd >= fd2;
3199 }
3200
3201 // CHECK-LABEL: define dso_local void @test_cmpgt(
3202 // CHECK-SAME: ) #[[ATTR0]] {
3203 // CHECK-NEXT: [[ENTRY:.*:]]
3204 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
3205 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
3206 // CHECK-NEXT: [[CMP:%.*]] = icmp sgt <16 x i8> [[TMP0]], [[TMP1]]
3207 // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
3208 // CHECK-NEXT: store volatile <16 x i8> [[SEXT]], ptr @bc, align 8
3209 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
3210 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
3211 // CHECK-NEXT: [[CMP1:%.*]] = icmp ugt <16 x i8> [[TMP2]], [[TMP3]]
3212 // CHECK-NEXT: [[SEXT2:%.*]] = sext <16 x i1> [[CMP1]] to <16 x i8>
3213 // CHECK-NEXT: store volatile <16 x i8> [[SEXT2]], ptr @bc, align 8
3214 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
3215 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
3216 // CHECK-NEXT: [[CMP3:%.*]] = icmp ugt <16 x i8> [[TMP4]], [[TMP5]]
3217 // CHECK-NEXT: [[SEXT4:%.*]] = sext <16 x i1> [[CMP3]] to <16 x i8>
3218 // CHECK-NEXT: store volatile <16 x i8> [[SEXT4]], ptr @bc, align 8
3219 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
3220 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
3221 // CHECK-NEXT: [[CMP5:%.*]] = icmp sgt <8 x i16> [[TMP6]], [[TMP7]]
3222 // CHECK-NEXT: [[SEXT6:%.*]] = sext <8 x i1> [[CMP5]] to <8 x i16>
3223 // CHECK-NEXT: store volatile <8 x i16> [[SEXT6]], ptr @bs, align 8
3224 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <8 x i16>, ptr @us, align 8
3225 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
3226 // CHECK-NEXT: [[CMP7:%.*]] = icmp ugt <8 x i16> [[TMP8]], [[TMP9]]
3227 // CHECK-NEXT: [[SEXT8:%.*]] = sext <8 x i1> [[CMP7]] to <8 x i16>
3228 // CHECK-NEXT: store volatile <8 x i16> [[SEXT8]], ptr @bs, align 8
3229 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
3230 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
3231 // CHECK-NEXT: [[CMP9:%.*]] = icmp ugt <8 x i16> [[TMP10]], [[TMP11]]
3232 // CHECK-NEXT: [[SEXT10:%.*]] = sext <8 x i1> [[CMP9]] to <8 x i16>
3233 // CHECK-NEXT: store volatile <8 x i16> [[SEXT10]], ptr @bs, align 8
3234 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <4 x i32>, ptr @si, align 8
3235 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
3236 // CHECK-NEXT: [[CMP11:%.*]] = icmp sgt <4 x i32> [[TMP12]], [[TMP13]]
3237 // CHECK-NEXT: [[SEXT12:%.*]] = sext <4 x i1> [[CMP11]] to <4 x i32>
3238 // CHECK-NEXT: store volatile <4 x i32> [[SEXT12]], ptr @bi, align 8
3239 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
3240 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
3241 // CHECK-NEXT: [[CMP13:%.*]] = icmp ugt <4 x i32> [[TMP14]], [[TMP15]]
3242 // CHECK-NEXT: [[SEXT14:%.*]] = sext <4 x i1> [[CMP13]] to <4 x i32>
3243 // CHECK-NEXT: store volatile <4 x i32> [[SEXT14]], ptr @bi, align 8
3244 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
3245 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
3246 // CHECK-NEXT: [[CMP15:%.*]] = icmp ugt <4 x i32> [[TMP16]], [[TMP17]]
3247 // CHECK-NEXT: [[SEXT16:%.*]] = sext <4 x i1> [[CMP15]] to <4 x i32>
3248 // CHECK-NEXT: store volatile <4 x i32> [[SEXT16]], ptr @bi, align 8
3249 // CHECK-NEXT: [[TMP18:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
3250 // CHECK-NEXT: [[TMP19:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
3251 // CHECK-NEXT: [[CMP17:%.*]] = icmp sgt <2 x i64> [[TMP18]], [[TMP19]]
3252 // CHECK-NEXT: [[SEXT18:%.*]] = sext <2 x i1> [[CMP17]] to <2 x i64>
3253 // CHECK-NEXT: store volatile <2 x i64> [[SEXT18]], ptr @bl, align 8
3254 // CHECK-NEXT: [[TMP20:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
3255 // CHECK-NEXT: [[TMP21:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
3256 // CHECK-NEXT: [[CMP19:%.*]] = icmp ugt <2 x i64> [[TMP20]], [[TMP21]]
3257 // CHECK-NEXT: [[SEXT20:%.*]] = sext <2 x i1> [[CMP19]] to <2 x i64>
3258 // CHECK-NEXT: store volatile <2 x i64> [[SEXT20]], ptr @bl, align 8
3259 // CHECK-NEXT: [[TMP22:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
3260 // CHECK-NEXT: [[TMP23:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
3261 // CHECK-NEXT: [[CMP21:%.*]] = icmp ugt <2 x i64> [[TMP22]], [[TMP23]]
3262 // CHECK-NEXT: [[SEXT22:%.*]] = sext <2 x i1> [[CMP21]] to <2 x i64>
3263 // CHECK-NEXT: store volatile <2 x i64> [[SEXT22]], ptr @bl, align 8
3264 // CHECK-NEXT: [[TMP24:%.*]] = load volatile <2 x double>, ptr @fd, align 8
3265 // CHECK-NEXT: [[TMP25:%.*]] = load volatile <2 x double>, ptr @fd2, align 8
3266 // CHECK-NEXT: [[CMP23:%.*]] = fcmp ogt <2 x double> [[TMP24]], [[TMP25]]
3267 // CHECK-NEXT: [[SEXT24:%.*]] = sext <2 x i1> [[CMP23]] to <2 x i64>
3268 // CHECK-NEXT: store volatile <2 x i64> [[SEXT24]], ptr @bl, align 8
3269 // CHECK-NEXT: ret void
3270 //
3271 void test_cmpgt(void) {
3272
3273 bc = sc > sc2;
3274 bc = uc > uc2;
3275 bc = bc > bc2;
3276
3277 bs = ss > ss2;
3278 bs = us > us2;
3279 bs = bs > bs2;
3280
3281 bi = si > si2;
3282 bi = ui > ui2;
3283 bi = bi > bi2;
3284
3285 bl = sl > sl2;
3286 bl = ul > ul2;
3287 bl = bl > bl2;
3288
3289 bl = fd > fd2;
3290 }
3291
3292 // CHECK-LABEL: define dso_local void @test_cmple(
3293 // CHECK-SAME: ) #[[ATTR0]] {
3294 // CHECK-NEXT: [[ENTRY:.*:]]
3295 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
3296 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
3297 // CHECK-NEXT: [[CMP:%.*]] = icmp sle <16 x i8> [[TMP0]], [[TMP1]]
3298 // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
3299 // CHECK-NEXT: store volatile <16 x i8> [[SEXT]], ptr @bc, align 8
3300 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
3301 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
3302 // CHECK-NEXT: [[CMP1:%.*]] = icmp ule <16 x i8> [[TMP2]], [[TMP3]]
3303 // CHECK-NEXT: [[SEXT2:%.*]] = sext <16 x i1> [[CMP1]] to <16 x i8>
3304 // CHECK-NEXT: store volatile <16 x i8> [[SEXT2]], ptr @bc, align 8
3305 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
3306 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
3307 // CHECK-NEXT: [[CMP3:%.*]] = icmp ule <16 x i8> [[TMP4]], [[TMP5]]
3308 // CHECK-NEXT: [[SEXT4:%.*]] = sext <16 x i1> [[CMP3]] to <16 x i8>
3309 // CHECK-NEXT: store volatile <16 x i8> [[SEXT4]], ptr @bc, align 8
3310 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
3311 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
3312 // CHECK-NEXT: [[CMP5:%.*]] = icmp sle <8 x i16> [[TMP6]], [[TMP7]]
3313 // CHECK-NEXT: [[SEXT6:%.*]] = sext <8 x i1> [[CMP5]] to <8 x i16>
3314 // CHECK-NEXT: store volatile <8 x i16> [[SEXT6]], ptr @bs, align 8
3315 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <8 x i16>, ptr @us, align 8
3316 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
3317 // CHECK-NEXT: [[CMP7:%.*]] = icmp ule <8 x i16> [[TMP8]], [[TMP9]]
3318 // CHECK-NEXT: [[SEXT8:%.*]] = sext <8 x i1> [[CMP7]] to <8 x i16>
3319 // CHECK-NEXT: store volatile <8 x i16> [[SEXT8]], ptr @bs, align 8
3320 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
3321 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
3322 // CHECK-NEXT: [[CMP9:%.*]] = icmp ule <8 x i16> [[TMP10]], [[TMP11]]
3323 // CHECK-NEXT: [[SEXT10:%.*]] = sext <8 x i1> [[CMP9]] to <8 x i16>
3324 // CHECK-NEXT: store volatile <8 x i16> [[SEXT10]], ptr @bs, align 8
3325 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <4 x i32>, ptr @si, align 8
3326 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
3327 // CHECK-NEXT: [[CMP11:%.*]] = icmp sle <4 x i32> [[TMP12]], [[TMP13]]
3328 // CHECK-NEXT: [[SEXT12:%.*]] = sext <4 x i1> [[CMP11]] to <4 x i32>
3329 // CHECK-NEXT: store volatile <4 x i32> [[SEXT12]], ptr @bi, align 8
3330 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
3331 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
3332 // CHECK-NEXT: [[CMP13:%.*]] = icmp ule <4 x i32> [[TMP14]], [[TMP15]]
3333 // CHECK-NEXT: [[SEXT14:%.*]] = sext <4 x i1> [[CMP13]] to <4 x i32>
3334 // CHECK-NEXT: store volatile <4 x i32> [[SEXT14]], ptr @bi, align 8
3335 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
3336 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
3337 // CHECK-NEXT: [[CMP15:%.*]] = icmp ule <4 x i32> [[TMP16]], [[TMP17]]
3338 // CHECK-NEXT: [[SEXT16:%.*]] = sext <4 x i1> [[CMP15]] to <4 x i32>
3339 // CHECK-NEXT: store volatile <4 x i32> [[SEXT16]], ptr @bi, align 8
3340 // CHECK-NEXT: [[TMP18:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
3341 // CHECK-NEXT: [[TMP19:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
3342 // CHECK-NEXT: [[CMP17:%.*]] = icmp sle <2 x i64> [[TMP18]], [[TMP19]]
3343 // CHECK-NEXT: [[SEXT18:%.*]] = sext <2 x i1> [[CMP17]] to <2 x i64>
3344 // CHECK-NEXT: store volatile <2 x i64> [[SEXT18]], ptr @bl, align 8
3345 // CHECK-NEXT: [[TMP20:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
3346 // CHECK-NEXT: [[TMP21:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
3347 // CHECK-NEXT: [[CMP19:%.*]] = icmp ule <2 x i64> [[TMP20]], [[TMP21]]
3348 // CHECK-NEXT: [[SEXT20:%.*]] = sext <2 x i1> [[CMP19]] to <2 x i64>
3349 // CHECK-NEXT: store volatile <2 x i64> [[SEXT20]], ptr @bl, align 8
3350 // CHECK-NEXT: [[TMP22:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
3351 // CHECK-NEXT: [[TMP23:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
3352 // CHECK-NEXT: [[CMP21:%.*]] = icmp ule <2 x i64> [[TMP22]], [[TMP23]]
3353 // CHECK-NEXT: [[SEXT22:%.*]] = sext <2 x i1> [[CMP21]] to <2 x i64>
3354 // CHECK-NEXT: store volatile <2 x i64> [[SEXT22]], ptr @bl, align 8
3355 // CHECK-NEXT: [[TMP24:%.*]] = load volatile <2 x double>, ptr @fd, align 8
3356 // CHECK-NEXT: [[TMP25:%.*]] = load volatile <2 x double>, ptr @fd2, align 8
3357 // CHECK-NEXT: [[CMP23:%.*]] = fcmp ole <2 x double> [[TMP24]], [[TMP25]]
3358 // CHECK-NEXT: [[SEXT24:%.*]] = sext <2 x i1> [[CMP23]] to <2 x i64>
3359 // CHECK-NEXT: store volatile <2 x i64> [[SEXT24]], ptr @bl, align 8
3360 // CHECK-NEXT: ret void
3361 //
3362 void test_cmple(void) {
3363
3364 bc = sc <= sc2;
3365 bc = uc <= uc2;
3366 bc = bc <= bc2;
3367
3368 bs = ss <= ss2;
3369 bs = us <= us2;
3370 bs = bs <= bs2;
3371
3372 bi = si <= si2;
3373 bi = ui <= ui2;
3374 bi = bi <= bi2;
3375
3376 bl = sl <= sl2;
3377 bl = ul <= ul2;
3378 bl = bl <= bl2;
3379
3380 bl = fd <= fd2;
3381 }
3382
3383 // CHECK-LABEL: define dso_local void @test_cmplt(
3384 // CHECK-SAME: ) #[[ATTR0]] {
3385 // CHECK-NEXT: [[ENTRY:.*:]]
3386 // CHECK-NEXT: [[TMP0:%.*]] = load volatile <16 x i8>, ptr @sc, align 8
3387 // CHECK-NEXT: [[TMP1:%.*]] = load volatile <16 x i8>, ptr @sc2, align 8
3388 // CHECK-NEXT: [[CMP:%.*]] = icmp slt <16 x i8> [[TMP0]], [[TMP1]]
3389 // CHECK-NEXT: [[SEXT:%.*]] = sext <16 x i1> [[CMP]] to <16 x i8>
3390 // CHECK-NEXT: store volatile <16 x i8> [[SEXT]], ptr @bc, align 8
3391 // CHECK-NEXT: [[TMP2:%.*]] = load volatile <16 x i8>, ptr @uc, align 8
3392 // CHECK-NEXT: [[TMP3:%.*]] = load volatile <16 x i8>, ptr @uc2, align 8
3393 // CHECK-NEXT: [[CMP1:%.*]] = icmp ult <16 x i8> [[TMP2]], [[TMP3]]
3394 // CHECK-NEXT: [[SEXT2:%.*]] = sext <16 x i1> [[CMP1]] to <16 x i8>
3395 // CHECK-NEXT: store volatile <16 x i8> [[SEXT2]], ptr @bc, align 8
3396 // CHECK-NEXT: [[TMP4:%.*]] = load volatile <16 x i8>, ptr @bc, align 8
3397 // CHECK-NEXT: [[TMP5:%.*]] = load volatile <16 x i8>, ptr @bc2, align 8
3398 // CHECK-NEXT: [[CMP3:%.*]] = icmp ult <16 x i8> [[TMP4]], [[TMP5]]
3399 // CHECK-NEXT: [[SEXT4:%.*]] = sext <16 x i1> [[CMP3]] to <16 x i8>
3400 // CHECK-NEXT: store volatile <16 x i8> [[SEXT4]], ptr @bc, align 8
3401 // CHECK-NEXT: [[TMP6:%.*]] = load volatile <8 x i16>, ptr @ss, align 8
3402 // CHECK-NEXT: [[TMP7:%.*]] = load volatile <8 x i16>, ptr @ss2, align 8
3403 // CHECK-NEXT: [[CMP5:%.*]] = icmp slt <8 x i16> [[TMP6]], [[TMP7]]
3404 // CHECK-NEXT: [[SEXT6:%.*]] = sext <8 x i1> [[CMP5]] to <8 x i16>
3405 // CHECK-NEXT: store volatile <8 x i16> [[SEXT6]], ptr @bs, align 8
3406 // CHECK-NEXT: [[TMP8:%.*]] = load volatile <8 x i16>, ptr @us, align 8
3407 // CHECK-NEXT: [[TMP9:%.*]] = load volatile <8 x i16>, ptr @us2, align 8
3408 // CHECK-NEXT: [[CMP7:%.*]] = icmp ult <8 x i16> [[TMP8]], [[TMP9]]
3409 // CHECK-NEXT: [[SEXT8:%.*]] = sext <8 x i1> [[CMP7]] to <8 x i16>
3410 // CHECK-NEXT: store volatile <8 x i16> [[SEXT8]], ptr @bs, align 8
3411 // CHECK-NEXT: [[TMP10:%.*]] = load volatile <8 x i16>, ptr @bs, align 8
3412 // CHECK-NEXT: [[TMP11:%.*]] = load volatile <8 x i16>, ptr @bs2, align 8
3413 // CHECK-NEXT: [[CMP9:%.*]] = icmp ult <8 x i16> [[TMP10]], [[TMP11]]
3414 // CHECK-NEXT: [[SEXT10:%.*]] = sext <8 x i1> [[CMP9]] to <8 x i16>
3415 // CHECK-NEXT: store volatile <8 x i16> [[SEXT10]], ptr @bs, align 8
3416 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <4 x i32>, ptr @si, align 8
3417 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <4 x i32>, ptr @si2, align 8
3418 // CHECK-NEXT: [[CMP11:%.*]] = icmp slt <4 x i32> [[TMP12]], [[TMP13]]
3419 // CHECK-NEXT: [[SEXT12:%.*]] = sext <4 x i1> [[CMP11]] to <4 x i32>
3420 // CHECK-NEXT: store volatile <4 x i32> [[SEXT12]], ptr @bi, align 8
3421 // CHECK-NEXT: [[TMP14:%.*]] = load volatile <4 x i32>, ptr @ui, align 8
3422 // CHECK-NEXT: [[TMP15:%.*]] = load volatile <4 x i32>, ptr @ui2, align 8
3423 // CHECK-NEXT: [[CMP13:%.*]] = icmp ult <4 x i32> [[TMP14]], [[TMP15]]
3424 // CHECK-NEXT: [[SEXT14:%.*]] = sext <4 x i1> [[CMP13]] to <4 x i32>
3425 // CHECK-NEXT: store volatile <4 x i32> [[SEXT14]], ptr @bi, align 8
3426 // CHECK-NEXT: [[TMP16:%.*]] = load volatile <4 x i32>, ptr @bi, align 8
3427 // CHECK-NEXT: [[TMP17:%.*]] = load volatile <4 x i32>, ptr @bi2, align 8
3428 // CHECK-NEXT: [[CMP15:%.*]] = icmp ult <4 x i32> [[TMP16]], [[TMP17]]
3429 // CHECK-NEXT: [[SEXT16:%.*]] = sext <4 x i1> [[CMP15]] to <4 x i32>
3430 // CHECK-NEXT: store volatile <4 x i32> [[SEXT16]], ptr @bi, align 8
3431 // CHECK-NEXT: [[TMP18:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
3432 // CHECK-NEXT: [[TMP19:%.*]] = load volatile <2 x i64>, ptr @sl2, align 8
3433 // CHECK-NEXT: [[CMP17:%.*]] = icmp slt <2 x i64> [[TMP18]], [[TMP19]]
3434 // CHECK-NEXT: [[SEXT18:%.*]] = sext <2 x i1> [[CMP17]] to <2 x i64>
3435 // CHECK-NEXT: store volatile <2 x i64> [[SEXT18]], ptr @bl, align 8
3436 // CHECK-NEXT: [[TMP20:%.*]] = load volatile <2 x i64>, ptr @ul, align 8
3437 // CHECK-NEXT: [[TMP21:%.*]] = load volatile <2 x i64>, ptr @ul2, align 8
3438 // CHECK-NEXT: [[CMP19:%.*]] = icmp ult <2 x i64> [[TMP20]], [[TMP21]]
3439 // CHECK-NEXT: [[SEXT20:%.*]] = sext <2 x i1> [[CMP19]] to <2 x i64>
3440 // CHECK-NEXT: store volatile <2 x i64> [[SEXT20]], ptr @bl, align 8
3441 // CHECK-NEXT: [[TMP22:%.*]] = load volatile <2 x i64>, ptr @bl, align 8
3442 // CHECK-NEXT: [[TMP23:%.*]] = load volatile <2 x i64>, ptr @bl2, align 8
3443 // CHECK-NEXT: [[CMP21:%.*]] = icmp ult <2 x i64> [[TMP22]], [[TMP23]]
3444 // CHECK-NEXT: [[SEXT22:%.*]] = sext <2 x i1> [[CMP21]] to <2 x i64>
3445 // CHECK-NEXT: store volatile <2 x i64> [[SEXT22]], ptr @bl, align 8
3446 // CHECK-NEXT: [[TMP24:%.*]] = load volatile <2 x double>, ptr @fd, align 8
3447 // CHECK-NEXT: [[TMP25:%.*]] = load volatile <2 x double>, ptr @fd2, align 8
3448 // CHECK-NEXT: [[CMP23:%.*]] = fcmp olt <2 x double> [[TMP24]], [[TMP25]]
3449 // CHECK-NEXT: [[SEXT24:%.*]] = sext <2 x i1> [[CMP23]] to <2 x i64>
3450 // CHECK-NEXT: store volatile <2 x i64> [[SEXT24]], ptr @bl, align 8
3451 // CHECK-NEXT: ret void
3452 //
3453 void test_cmplt(void) {
3454
3455 bc = sc < sc2;
3456 bc = uc < uc2;
3457 bc = bc < bc2;
3458
3459 bs = ss < ss2;
3460 bs = us < us2;
3461 bs = bs < bs2;
3462
3463 bi = si < si2;
3464 bi = ui < ui2;
3465 bi = bi < bi2;
3466
3467 bl = sl < sl2;
3468 bl = ul < ul2;
3469 bl = bl < bl2;
3470
3471 bl = fd < fd2;
3472 }
3473
LLVM monorepo