1 ; RUN: llc < %s -debug-entry-values -mtriple=arm64-apple-darwin | FileCheck %s
3 ; Stackmap Header: no constants - 6 callsites
4 ; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps
5 ; CHECK-NEXT: __LLVM_StackMaps:
17 ; Functions and stack size
18 ; CHECK-NEXT: .quad _test
19 ; CHECK-NEXT: .quad 16
21 ; CHECK-NEXT: .quad _property_access1
22 ; CHECK-NEXT: .quad 16
24 ; CHECK-NEXT: .quad _property_access2
25 ; CHECK-NEXT: .quad 32
27 ; CHECK-NEXT: .quad _property_access3
28 ; CHECK-NEXT: .quad 32
30 ; CHECK-NEXT: .quad _anyreg_test1
31 ; CHECK-NEXT: .quad 16
33 ; CHECK-NEXT: .quad _anyreg_test2
34 ; CHECK-NEXT: .quad 16
36 ; CHECK-NEXT: .quad _patchpoint_spilldef
37 ; CHECK-NEXT: .quad 112
39 ; CHECK-NEXT: .quad _patchpoint_spillargs
40 ; CHECK-NEXT: .quad 128
45 ; CHECK-LABEL: .long L{{.*}}-_test
46 ; CHECK-NEXT: .short 0
48 ; CHECK-NEXT: .short 3
52 ; CHECK-NEXT: .short 4
53 ; CHECK-NEXT: .short {{[0-9]+}}
54 ; CHECK-NEXT: .short 0
59 ; CHECK-NEXT: .short 4
60 ; CHECK-NEXT: .short {{[0-9]+}}
61 ; CHECK-NEXT: .short 0
66 ; CHECK-NEXT: .short 8
67 ; CHECK-NEXT: .short 0
68 ; CHECK-NEXT: .short 0
70 define i64 @test() nounwind ssp uwtable {
72 call anyregcc void (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 16, ptr null, i32 2, i32 1, i32 2, i64 3)
76 ; property access 1 - %obj is an anyreg call argument and should therefore be in a register
77 ; CHECK-LABEL: .long L{{.*}}-_property_access1
78 ; CHECK-NEXT: .short 0
80 ; CHECK-NEXT: .short 2
81 ; Loc 0: Register <-- this is the return register
84 ; CHECK-NEXT: .short 8
85 ; CHECK-NEXT: .short {{[0-9]+}}
86 ; CHECK-NEXT: .short 0
91 ; CHECK-NEXT: .short 8
92 ; CHECK-NEXT: .short {{[0-9]+}}
93 ; CHECK-NEXT: .short 0
95 define i64 @property_access1(ptr %obj) nounwind ssp uwtable {
97 %f = inttoptr i64 281474417671919 to ptr
98 %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 20, ptr %f, i32 1, ptr %obj)
102 ; property access 2 - %obj is an anyreg call argument and should therefore be in a register
103 ; CHECK-LABEL: .long L{{.*}}-_property_access2
104 ; CHECK-NEXT: .short 0
106 ; CHECK-NEXT: .short 2
107 ; Loc 0: Register <-- this is the return register
108 ; CHECK-NEXT: .byte 1
109 ; CHECK-NEXT: .byte 0
110 ; CHECK-NEXT: .short 8
111 ; CHECK-NEXT: .short {{[0-9]+}}
112 ; CHECK-NEXT: .short 0
113 ; CHECK-NEXT: .long 0
115 ; CHECK-NEXT: .byte 1
116 ; CHECK-NEXT: .byte 0
117 ; CHECK-NEXT: .short 8
118 ; CHECK-NEXT: .short {{[0-9]+}}
119 ; CHECK-NEXT: .short 0
120 ; CHECK-NEXT: .long 0
121 define i64 @property_access2() nounwind ssp uwtable {
123 %obj = alloca i64, align 8
124 %f = inttoptr i64 281474417671919 to ptr
125 %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 20, ptr %f, i32 1, ptr %obj)
129 ; property access 3 - %obj is a frame index
130 ; CHECK-LABEL: .long L{{.*}}-_property_access3
131 ; CHECK-NEXT: .short 0
133 ; CHECK-NEXT: .short 2
134 ; Loc 0: Register <-- this is the return register
135 ; CHECK-NEXT: .byte 1
136 ; CHECK-NEXT: .byte 0
137 ; CHECK-NEXT: .short 8
138 ; CHECK-NEXT: .short {{[0-9]+}}
139 ; CHECK-NEXT: .short 0
140 ; CHECK-NEXT: .long 0
141 ; Loc 1: Direct FP - 8
142 ; CHECK-NEXT: .byte 2
143 ; CHECK-NEXT: .byte 0
144 ; CHECK-NEXT: .short 8
145 ; CHECK-NEXT: .short 29
146 ; CHECK-NEXT: .short 0
147 ; CHECK-NEXT: .long -8
148 define i64 @property_access3() nounwind ssp uwtable {
150 %obj = alloca i64, align 8
151 %f = inttoptr i64 281474417671919 to ptr
152 %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 20, ptr %f, i32 0, ptr %obj)
157 ; CHECK-LABEL: .long L{{.*}}-_anyreg_test1
158 ; CHECK-NEXT: .short 0
160 ; CHECK-NEXT: .short 14
161 ; Loc 0: Register <-- this is the return register
162 ; CHECK-NEXT: .byte 1
163 ; CHECK-NEXT: .byte 0
164 ; CHECK-NEXT: .short 8
165 ; CHECK-NEXT: .short {{[0-9]+}}
166 ; CHECK-NEXT: .short 0
167 ; CHECK-NEXT: .long 0
169 ; CHECK-NEXT: .byte 1
170 ; CHECK-NEXT: .byte 0
171 ; CHECK-NEXT: .short 8
172 ; CHECK-NEXT: .short {{[0-9]+}}
173 ; CHECK-NEXT: .short 0
174 ; CHECK-NEXT: .long 0
176 ; CHECK-NEXT: .byte 1
177 ; CHECK-NEXT: .byte 0
178 ; CHECK-NEXT: .short 8
179 ; CHECK-NEXT: .short {{[0-9]+}}
180 ; CHECK-NEXT: .short 0
181 ; CHECK-NEXT: .long 0
183 ; CHECK-NEXT: .byte 1
184 ; CHECK-NEXT: .byte 0
185 ; CHECK-NEXT: .short 8
186 ; CHECK-NEXT: .short {{[0-9]+}}
187 ; CHECK-NEXT: .short 0
188 ; CHECK-NEXT: .long 0
190 ; CHECK-NEXT: .byte 1
191 ; CHECK-NEXT: .byte 0
192 ; CHECK-NEXT: .short 8
193 ; CHECK-NEXT: .short {{[0-9]+}}
194 ; CHECK-NEXT: .short 0
195 ; CHECK-NEXT: .long 0
197 ; CHECK-NEXT: .byte 1
198 ; CHECK-NEXT: .byte 0
199 ; CHECK-NEXT: .short 8
200 ; CHECK-NEXT: .short {{[0-9]+}}
201 ; CHECK-NEXT: .short 0
202 ; CHECK-NEXT: .long 0
204 ; CHECK-NEXT: .byte 1
205 ; CHECK-NEXT: .byte 0
206 ; CHECK-NEXT: .short 8
207 ; CHECK-NEXT: .short {{[0-9]+}}
208 ; CHECK-NEXT: .short 0
209 ; CHECK-NEXT: .long 0
211 ; CHECK-NEXT: .byte 1
212 ; CHECK-NEXT: .byte 0
213 ; CHECK-NEXT: .short 8
214 ; CHECK-NEXT: .short {{[0-9]+}}
215 ; CHECK-NEXT: .short 0
216 ; CHECK-NEXT: .long 0
218 ; CHECK-NEXT: .byte 1
219 ; CHECK-NEXT: .byte 0
220 ; CHECK-NEXT: .short 8
221 ; CHECK-NEXT: .short {{[0-9]+}}
222 ; CHECK-NEXT: .short 0
223 ; CHECK-NEXT: .long 0
225 ; CHECK-NEXT: .byte 1
226 ; CHECK-NEXT: .byte 0
227 ; CHECK-NEXT: .short 8
228 ; CHECK-NEXT: .short {{[0-9]+}}
229 ; CHECK-NEXT: .short 0
230 ; CHECK-NEXT: .long 0
232 ; CHECK-NEXT: .byte 1
233 ; CHECK-NEXT: .byte 0
234 ; CHECK-NEXT: .short 8
235 ; CHECK-NEXT: .short {{[0-9]+}}
236 ; CHECK-NEXT: .short 0
237 ; CHECK-NEXT: .long 0
239 ; CHECK-NEXT: .byte 1
240 ; CHECK-NEXT: .byte 0
241 ; CHECK-NEXT: .short 8
242 ; CHECK-NEXT: .short {{[0-9]+}}
243 ; CHECK-NEXT: .short 0
244 ; CHECK-NEXT: .long 0
246 ; CHECK-NEXT: .byte 1
247 ; CHECK-NEXT: .byte 0
248 ; CHECK-NEXT: .short 8
249 ; CHECK-NEXT: .short {{[0-9]+}}
250 ; CHECK-NEXT: .short 0
251 ; CHECK-NEXT: .long 0
253 ; CHECK-NEXT: .byte 1
254 ; CHECK-NEXT: .byte 0
255 ; CHECK-NEXT: .short 8
256 ; CHECK-NEXT: .short {{[0-9]+}}
257 ; CHECK-NEXT: .short 0
258 ; CHECK-NEXT: .long 0
259 define i64 @anyreg_test1(ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13) nounwind ssp uwtable {
261 %f = inttoptr i64 281474417671919 to ptr
262 %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 20, ptr %f, i32 13, ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13)
267 ; CHECK-LABEL: .long L{{.*}}-_anyreg_test2
268 ; CHECK-NEXT: .short 0
270 ; CHECK-NEXT: .short 14
271 ; Loc 0: Register <-- this is the return register
272 ; CHECK-NEXT: .byte 1
273 ; CHECK-NEXT: .byte 0
274 ; CHECK-NEXT: .short 8
275 ; CHECK-NEXT: .short {{[0-9]+}}
276 ; CHECK-NEXT: .short 0
277 ; CHECK-NEXT: .long 0
279 ; CHECK-NEXT: .byte 1
280 ; CHECK-NEXT: .byte 0
281 ; CHECK-NEXT: .short 8
282 ; CHECK-NEXT: .short {{[0-9]+}}
283 ; CHECK-NEXT: .short 0
284 ; CHECK-NEXT: .long 0
286 ; CHECK-NEXT: .byte 1
287 ; CHECK-NEXT: .byte 0
288 ; CHECK-NEXT: .short 8
289 ; CHECK-NEXT: .short {{[0-9]+}}
290 ; CHECK-NEXT: .short 0
291 ; CHECK-NEXT: .long 0
293 ; CHECK-NEXT: .byte 1
294 ; CHECK-NEXT: .byte 0
295 ; CHECK-NEXT: .short 8
296 ; CHECK-NEXT: .short {{[0-9]+}}
297 ; CHECK-NEXT: .short 0
298 ; CHECK-NEXT: .long 0
300 ; CHECK-NEXT: .byte 1
301 ; CHECK-NEXT: .byte 0
302 ; CHECK-NEXT: .short 8
303 ; CHECK-NEXT: .short {{[0-9]+}}
304 ; CHECK-NEXT: .short 0
305 ; CHECK-NEXT: .long 0
307 ; CHECK-NEXT: .byte 1
308 ; CHECK-NEXT: .byte 0
309 ; CHECK-NEXT: .short 8
310 ; CHECK-NEXT: .short {{[0-9]+}}
311 ; CHECK-NEXT: .short 0
312 ; CHECK-NEXT: .long 0
314 ; CHECK-NEXT: .byte 1
315 ; CHECK-NEXT: .byte 0
316 ; CHECK-NEXT: .short 8
317 ; CHECK-NEXT: .short {{[0-9]+}}
318 ; CHECK-NEXT: .short 0
319 ; CHECK-NEXT: .long 0
321 ; CHECK-NEXT: .byte 1
322 ; CHECK-NEXT: .byte 0
323 ; CHECK-NEXT: .short 8
324 ; CHECK-NEXT: .short {{[0-9]+}}
325 ; CHECK-NEXT: .short 0
326 ; CHECK-NEXT: .long 0
328 ; CHECK-NEXT: .byte 1
329 ; CHECK-NEXT: .byte 0
330 ; CHECK-NEXT: .short 8
331 ; CHECK-NEXT: .short {{[0-9]+}}
332 ; CHECK-NEXT: .short 0
333 ; CHECK-NEXT: .long 0
335 ; CHECK-NEXT: .byte 1
336 ; CHECK-NEXT: .byte 0
337 ; CHECK-NEXT: .short 8
338 ; CHECK-NEXT: .short {{[0-9]+}}
339 ; CHECK-NEXT: .short 0
340 ; CHECK-NEXT: .long 0
342 ; CHECK-NEXT: .byte 1
343 ; CHECK-NEXT: .byte 0
344 ; CHECK-NEXT: .short 8
345 ; CHECK-NEXT: .short {{[0-9]+}}
346 ; CHECK-NEXT: .short 0
347 ; CHECK-NEXT: .long 0
349 ; CHECK-NEXT: .byte 1
350 ; CHECK-NEXT: .byte 0
351 ; CHECK-NEXT: .short 8
352 ; CHECK-NEXT: .short {{[0-9]+}}
353 ; CHECK-NEXT: .short 0
354 ; CHECK-NEXT: .long 0
356 ; CHECK-NEXT: .byte 1
357 ; CHECK-NEXT: .byte 0
358 ; CHECK-NEXT: .short 8
359 ; CHECK-NEXT: .short {{[0-9]+}}
360 ; CHECK-NEXT: .short 0
361 ; CHECK-NEXT: .long 0
363 ; CHECK-NEXT: .byte 1
364 ; CHECK-NEXT: .byte 0
365 ; CHECK-NEXT: .short 8
366 ; CHECK-NEXT: .short {{[0-9]+}}
367 ; CHECK-NEXT: .short 0
368 ; CHECK-NEXT: .long 0
369 define i64 @anyreg_test2(ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13) nounwind ssp uwtable {
371 %f = inttoptr i64 281474417671919 to ptr
372 %ret = call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, ptr %f, i32 8, ptr %a1, ptr %a2, ptr %a3, ptr %a4, ptr %a5, ptr %a6, ptr %a7, ptr %a8, ptr %a9, ptr %a10, ptr %a11, ptr %a12, ptr %a13)
376 ; Test spilling the return value of an anyregcc call.
378 ; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
380 ; CHECK-LABEL: .long L{{.*}}-_patchpoint_spilldef
381 ; CHECK-NEXT: .short 0
382 ; CHECK-NEXT: .short 3
383 ; Loc 0: Register (some register that will be spilled to the stack)
384 ; CHECK-NEXT: .byte 1
385 ; CHECK-NEXT: .byte 0
386 ; CHECK-NEXT: .short 8
387 ; CHECK-NEXT: .short {{[0-9]+}}
388 ; CHECK-NEXT: .short 0
389 ; CHECK-NEXT: .long 0
391 ; CHECK-NEXT: .byte 1
392 ; CHECK-NEXT: .byte 0
393 ; CHECK-NEXT: .short 8
394 ; CHECK-NEXT: .short {{[0-9]+}}
395 ; CHECK-NEXT: .short 0
396 ; CHECK-NEXT: .long 0
398 ; CHECK-NEXT: .byte 1
399 ; CHECK-NEXT: .byte 0
400 ; CHECK-NEXT: .short 8
401 ; CHECK-NEXT: .short {{[0-9]+}}
402 ; CHECK-NEXT: .short 0
403 ; CHECK-NEXT: .long 0
404 define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
406 %result = tail call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 16, ptr inttoptr (i64 0 to ptr), i32 2, i64 %p1, i64 %p2)
407 tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
411 ; Test spilling the arguments of an anyregcc call.
413 ; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
415 ; CHECK-LABEL: .long L{{.*}}-_patchpoint_spillargs
416 ; CHECK-NEXT: .short 0
417 ; CHECK-NEXT: .short 5
418 ; Loc 0: Return a register
419 ; CHECK-NEXT: .byte 1
420 ; CHECK-NEXT: .byte 0
421 ; CHECK-NEXT: .short 8
422 ; CHECK-NEXT: .short {{[0-9]+}}
423 ; CHECK-NEXT: .short 0
424 ; CHECK-NEXT: .long 0
425 ; Loc 1: Arg0 in a Register
426 ; CHECK-NEXT: .byte 1
427 ; CHECK-NEXT: .byte 0
428 ; CHECK-NEXT: .short 8
429 ; CHECK-NEXT: .short {{[0-9]+}}
430 ; CHECK-NEXT: .short 0
431 ; CHECK-NEXT: .long 0
432 ; Loc 2: Arg1 in a Register
433 ; CHECK-NEXT: .byte 1
434 ; CHECK-NEXT: .byte 0
435 ; CHECK-NEXT: .short 8
436 ; CHECK-NEXT: .short {{[0-9]+}}
437 ; CHECK-NEXT: .short 0
438 ; CHECK-NEXT: .long 0
439 ; Loc 3: Arg2 spilled to FP -96
440 ; CHECK-NEXT: .byte 3
441 ; CHECK-NEXT: .byte 0
442 ; CHECK-NEXT: .short 8
443 ; CHECK-NEXT: .short 29
444 ; CHECK-NEXT: .short 0
445 ; CHECK-NEXT: .long -96
446 ; Loc 4: Arg3 spilled to FP - 88
447 ; CHECK-NEXT: .byte 3
448 ; CHECK-NEXT: .byte 0
449 ; CHECK-NEXT: .short 8
450 ; CHECK-NEXT: .short 29
451 ; CHECK-NEXT: .short 0
452 ; CHECK-NEXT: .long -88
453 define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
455 tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind
456 %result = tail call anyregcc i64 (i64, i32, ptr, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 16, ptr inttoptr (i64 0 to ptr), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
460 declare void @llvm.experimental.patchpoint.void(i64, i32, ptr, i32, ...)
461 declare i64 @llvm.experimental.patchpoint.i64(i64, i32, ptr, i32, ...)