1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
8 define <vscale x 16 x i8> @sdiv_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
9 ; CHECK-LABEL: sdiv_i8:
11 ; CHECK-NEXT: sunpkhi z2.h, z1.b
12 ; CHECK-NEXT: sunpkhi z3.h, z0.b
13 ; CHECK-NEXT: ptrue p0.s
14 ; CHECK-NEXT: sunpklo z1.h, z1.b
15 ; CHECK-NEXT: sunpklo z0.h, z0.b
16 ; CHECK-NEXT: sunpkhi z4.s, z2.h
17 ; CHECK-NEXT: sunpkhi z5.s, z3.h
18 ; CHECK-NEXT: sunpklo z2.s, z2.h
19 ; CHECK-NEXT: sunpklo z3.s, z3.h
20 ; CHECK-NEXT: sdivr z4.s, p0/m, z4.s, z5.s
21 ; CHECK-NEXT: sunpkhi z5.s, z0.h
22 ; CHECK-NEXT: sunpklo z0.s, z0.h
23 ; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s
24 ; CHECK-NEXT: sunpkhi z3.s, z1.h
25 ; CHECK-NEXT: sunpklo z1.s, z1.h
26 ; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z5.s
27 ; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s
28 ; CHECK-NEXT: uzp1 z1.h, z2.h, z4.h
29 ; CHECK-NEXT: uzp1 z0.h, z0.h, z3.h
30 ; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b
32 %div = sdiv <vscale x 16 x i8> %a, %b
33 ret <vscale x 16 x i8> %div
36 define <vscale x 8 x i16> @sdiv_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
37 ; CHECK-LABEL: sdiv_i16:
39 ; CHECK-NEXT: ptrue p0.s
40 ; CHECK-NEXT: sunpkhi z2.s, z1.h
41 ; CHECK-NEXT: sunpkhi z3.s, z0.h
42 ; CHECK-NEXT: sunpklo z1.s, z1.h
43 ; CHECK-NEXT: sunpklo z0.s, z0.h
44 ; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s
45 ; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s
46 ; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h
48 %div = sdiv <vscale x 8 x i16> %a, %b
49 ret <vscale x 8 x i16> %div
52 define <vscale x 4 x i32> @sdiv_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
53 ; CHECK-LABEL: sdiv_i32:
55 ; CHECK-NEXT: ptrue p0.s
56 ; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s
58 %div = sdiv <vscale x 4 x i32> %a, %b
59 ret <vscale x 4 x i32> %div
62 define <vscale x 2 x i64> @sdiv_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
63 ; CHECK-LABEL: sdiv_i64:
65 ; CHECK-NEXT: ptrue p0.d
66 ; CHECK-NEXT: sdiv z0.d, p0/m, z0.d, z1.d
68 %div = sdiv <vscale x 2 x i64> %a, %b
69 ret <vscale x 2 x i64> %div
72 define <vscale x 8 x i32> @sdiv_split_i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) {
73 ; CHECK-LABEL: sdiv_split_i32:
75 ; CHECK-NEXT: ptrue p0.s
76 ; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z2.s
77 ; CHECK-NEXT: sdiv z1.s, p0/m, z1.s, z3.s
79 %div = sdiv <vscale x 8 x i32> %a, %b
80 ret <vscale x 8 x i32> %div
83 define <vscale x 2 x i32> @sdiv_widen_i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
84 ; CHECK-LABEL: sdiv_widen_i32:
86 ; CHECK-NEXT: ptrue p0.d
87 ; CHECK-NEXT: sxtw z1.d, p0/m, z1.d
88 ; CHECK-NEXT: sxtw z0.d, p0/m, z0.d
89 ; CHECK-NEXT: sdiv z0.d, p0/m, z0.d, z1.d
91 %div = sdiv <vscale x 2 x i32> %a, %b
92 ret <vscale x 2 x i32> %div
95 define <vscale x 4 x i64> @sdiv_split_i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) {
96 ; CHECK-LABEL: sdiv_split_i64:
98 ; CHECK-NEXT: ptrue p0.d
99 ; CHECK-NEXT: sdiv z0.d, p0/m, z0.d, z2.d
100 ; CHECK-NEXT: sdiv z1.d, p0/m, z1.d, z3.d
102 %div = sdiv <vscale x 4 x i64> %a, %b
103 ret <vscale x 4 x i64> %div
110 define <vscale x 16 x i8> @srem_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
111 ; CHECK-LABEL: srem_i8:
113 ; CHECK-NEXT: sunpkhi z2.h, z1.b
114 ; CHECK-NEXT: sunpkhi z3.h, z0.b
115 ; CHECK-NEXT: ptrue p0.s
116 ; CHECK-NEXT: sunpkhi z4.s, z2.h
117 ; CHECK-NEXT: sunpkhi z5.s, z3.h
118 ; CHECK-NEXT: sunpklo z2.s, z2.h
119 ; CHECK-NEXT: sunpklo z3.s, z3.h
120 ; CHECK-NEXT: sdivr z4.s, p0/m, z4.s, z5.s
121 ; CHECK-NEXT: sunpklo z5.h, z0.b
122 ; CHECK-NEXT: sunpkhi z7.s, z5.h
123 ; CHECK-NEXT: sunpklo z5.s, z5.h
124 ; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s
125 ; CHECK-NEXT: sunpklo z3.h, z1.b
126 ; CHECK-NEXT: sunpkhi z6.s, z3.h
127 ; CHECK-NEXT: sunpklo z3.s, z3.h
128 ; CHECK-NEXT: sdivr z6.s, p0/m, z6.s, z7.s
129 ; CHECK-NEXT: uzp1 z2.h, z2.h, z4.h
130 ; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z5.s
131 ; CHECK-NEXT: ptrue p0.b
132 ; CHECK-NEXT: uzp1 z3.h, z3.h, z6.h
133 ; CHECK-NEXT: uzp1 z2.b, z3.b, z2.b
134 ; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b
136 %div = srem <vscale x 16 x i8> %a, %b
137 ret <vscale x 16 x i8> %div
140 define <vscale x 8 x i16> @srem_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
141 ; CHECK-LABEL: srem_i16:
143 ; CHECK-NEXT: ptrue p0.s
144 ; CHECK-NEXT: sunpkhi z2.s, z1.h
145 ; CHECK-NEXT: sunpkhi z3.s, z0.h
146 ; CHECK-NEXT: sunpklo z4.s, z0.h
147 ; CHECK-NEXT: sdivr z2.s, p0/m, z2.s, z3.s
148 ; CHECK-NEXT: sunpklo z3.s, z1.h
149 ; CHECK-NEXT: sdivr z3.s, p0/m, z3.s, z4.s
150 ; CHECK-NEXT: ptrue p0.h
151 ; CHECK-NEXT: uzp1 z2.h, z3.h, z2.h
152 ; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h
154 %div = srem <vscale x 8 x i16> %a, %b
155 ret <vscale x 8 x i16> %div
158 define <vscale x 4 x i32> @srem_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
159 ; CHECK-LABEL: srem_i32:
161 ; CHECK-NEXT: ptrue p0.s
162 ; CHECK-NEXT: movprfx z2, z0
163 ; CHECK-NEXT: sdiv z2.s, p0/m, z2.s, z1.s
164 ; CHECK-NEXT: mls z0.s, p0/m, z2.s, z1.s
166 %div = srem <vscale x 4 x i32> %a, %b
167 ret <vscale x 4 x i32> %div
170 define <vscale x 2 x i64> @srem_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
171 ; CHECK-LABEL: srem_i64:
173 ; CHECK-NEXT: ptrue p0.d
174 ; CHECK-NEXT: movprfx z2, z0
175 ; CHECK-NEXT: sdiv z2.d, p0/m, z2.d, z1.d
176 ; CHECK-NEXT: mls z0.d, p0/m, z2.d, z1.d
178 %div = srem <vscale x 2 x i64> %a, %b
179 ret <vscale x 2 x i64> %div
186 define <vscale x 16 x i8> @udiv_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
187 ; CHECK-LABEL: udiv_i8:
189 ; CHECK-NEXT: uunpkhi z2.h, z1.b
190 ; CHECK-NEXT: uunpkhi z3.h, z0.b
191 ; CHECK-NEXT: ptrue p0.s
192 ; CHECK-NEXT: uunpklo z1.h, z1.b
193 ; CHECK-NEXT: uunpklo z0.h, z0.b
194 ; CHECK-NEXT: uunpkhi z4.s, z2.h
195 ; CHECK-NEXT: uunpkhi z5.s, z3.h
196 ; CHECK-NEXT: uunpklo z2.s, z2.h
197 ; CHECK-NEXT: uunpklo z3.s, z3.h
198 ; CHECK-NEXT: udivr z4.s, p0/m, z4.s, z5.s
199 ; CHECK-NEXT: uunpkhi z5.s, z0.h
200 ; CHECK-NEXT: uunpklo z0.s, z0.h
201 ; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s
202 ; CHECK-NEXT: uunpkhi z3.s, z1.h
203 ; CHECK-NEXT: uunpklo z1.s, z1.h
204 ; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z5.s
205 ; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s
206 ; CHECK-NEXT: uzp1 z1.h, z2.h, z4.h
207 ; CHECK-NEXT: uzp1 z0.h, z0.h, z3.h
208 ; CHECK-NEXT: uzp1 z0.b, z0.b, z1.b
210 %div = udiv <vscale x 16 x i8> %a, %b
211 ret <vscale x 16 x i8> %div
214 define <vscale x 8 x i16> @udiv_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
215 ; CHECK-LABEL: udiv_i16:
217 ; CHECK-NEXT: ptrue p0.s
218 ; CHECK-NEXT: uunpkhi z2.s, z1.h
219 ; CHECK-NEXT: uunpkhi z3.s, z0.h
220 ; CHECK-NEXT: uunpklo z1.s, z1.h
221 ; CHECK-NEXT: uunpklo z0.s, z0.h
222 ; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s
223 ; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s
224 ; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h
226 %div = udiv <vscale x 8 x i16> %a, %b
227 ret <vscale x 8 x i16> %div
230 define <vscale x 4 x i32> @udiv_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
231 ; CHECK-LABEL: udiv_i32:
233 ; CHECK-NEXT: ptrue p0.s
234 ; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s
236 %div = udiv <vscale x 4 x i32> %a, %b
237 ret <vscale x 4 x i32> %div
240 define <vscale x 2 x i64> @udiv_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
241 ; CHECK-LABEL: udiv_i64:
243 ; CHECK-NEXT: ptrue p0.d
244 ; CHECK-NEXT: udiv z0.d, p0/m, z0.d, z1.d
246 %div = udiv <vscale x 2 x i64> %a, %b
247 ret <vscale x 2 x i64> %div
250 define <vscale x 8 x i32> @udiv_split_i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) {
251 ; CHECK-LABEL: udiv_split_i32:
253 ; CHECK-NEXT: ptrue p0.s
254 ; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z2.s
255 ; CHECK-NEXT: udiv z1.s, p0/m, z1.s, z3.s
257 %div = udiv <vscale x 8 x i32> %a, %b
258 ret <vscale x 8 x i32> %div
261 define <vscale x 2 x i32> @udiv_widen_i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
262 ; CHECK-LABEL: udiv_widen_i32:
264 ; CHECK-NEXT: ptrue p0.d
265 ; CHECK-NEXT: and z1.d, z1.d, #0xffffffff
266 ; CHECK-NEXT: and z0.d, z0.d, #0xffffffff
267 ; CHECK-NEXT: udiv z0.d, p0/m, z0.d, z1.d
269 %div = udiv <vscale x 2 x i32> %a, %b
270 ret <vscale x 2 x i32> %div
273 define <vscale x 4 x i64> @udiv_split_i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) {
274 ; CHECK-LABEL: udiv_split_i64:
276 ; CHECK-NEXT: ptrue p0.d
277 ; CHECK-NEXT: udiv z0.d, p0/m, z0.d, z2.d
278 ; CHECK-NEXT: udiv z1.d, p0/m, z1.d, z3.d
280 %div = udiv <vscale x 4 x i64> %a, %b
281 ret <vscale x 4 x i64> %div
289 define <vscale x 16 x i8> @urem_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
290 ; CHECK-LABEL: urem_i8:
292 ; CHECK-NEXT: uunpkhi z2.h, z1.b
293 ; CHECK-NEXT: uunpkhi z3.h, z0.b
294 ; CHECK-NEXT: ptrue p0.s
295 ; CHECK-NEXT: uunpkhi z4.s, z2.h
296 ; CHECK-NEXT: uunpkhi z5.s, z3.h
297 ; CHECK-NEXT: uunpklo z2.s, z2.h
298 ; CHECK-NEXT: uunpklo z3.s, z3.h
299 ; CHECK-NEXT: udivr z4.s, p0/m, z4.s, z5.s
300 ; CHECK-NEXT: uunpklo z5.h, z0.b
301 ; CHECK-NEXT: uunpkhi z7.s, z5.h
302 ; CHECK-NEXT: uunpklo z5.s, z5.h
303 ; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s
304 ; CHECK-NEXT: uunpklo z3.h, z1.b
305 ; CHECK-NEXT: uunpkhi z6.s, z3.h
306 ; CHECK-NEXT: uunpklo z3.s, z3.h
307 ; CHECK-NEXT: udivr z6.s, p0/m, z6.s, z7.s
308 ; CHECK-NEXT: uzp1 z2.h, z2.h, z4.h
309 ; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z5.s
310 ; CHECK-NEXT: ptrue p0.b
311 ; CHECK-NEXT: uzp1 z3.h, z3.h, z6.h
312 ; CHECK-NEXT: uzp1 z2.b, z3.b, z2.b
313 ; CHECK-NEXT: mls z0.b, p0/m, z2.b, z1.b
315 %div = urem <vscale x 16 x i8> %a, %b
316 ret <vscale x 16 x i8> %div
319 define <vscale x 8 x i16> @urem_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
320 ; CHECK-LABEL: urem_i16:
322 ; CHECK-NEXT: ptrue p0.s
323 ; CHECK-NEXT: uunpkhi z2.s, z1.h
324 ; CHECK-NEXT: uunpkhi z3.s, z0.h
325 ; CHECK-NEXT: uunpklo z4.s, z0.h
326 ; CHECK-NEXT: udivr z2.s, p0/m, z2.s, z3.s
327 ; CHECK-NEXT: uunpklo z3.s, z1.h
328 ; CHECK-NEXT: udivr z3.s, p0/m, z3.s, z4.s
329 ; CHECK-NEXT: ptrue p0.h
330 ; CHECK-NEXT: uzp1 z2.h, z3.h, z2.h
331 ; CHECK-NEXT: mls z0.h, p0/m, z2.h, z1.h
333 %div = urem <vscale x 8 x i16> %a, %b
334 ret <vscale x 8 x i16> %div
337 define <vscale x 4 x i32> @urem_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
338 ; CHECK-LABEL: urem_i32:
340 ; CHECK-NEXT: ptrue p0.s
341 ; CHECK-NEXT: movprfx z2, z0
342 ; CHECK-NEXT: udiv z2.s, p0/m, z2.s, z1.s
343 ; CHECK-NEXT: mls z0.s, p0/m, z2.s, z1.s
345 %div = urem <vscale x 4 x i32> %a, %b
346 ret <vscale x 4 x i32> %div
349 define <vscale x 2 x i64> @urem_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
350 ; CHECK-LABEL: urem_i64:
352 ; CHECK-NEXT: ptrue p0.d
353 ; CHECK-NEXT: movprfx z2, z0
354 ; CHECK-NEXT: udiv z2.d, p0/m, z2.d, z1.d
355 ; CHECK-NEXT: mls z0.d, p0/m, z2.d, z1.d
357 %div = urem <vscale x 2 x i64> %a, %b
358 ret <vscale x 2 x i64> %div
365 define <vscale x 16 x i8> @smin_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
366 ; CHECK-LABEL: smin_i8:
368 ; CHECK-NEXT: ptrue p0.b
369 ; CHECK-NEXT: smin z0.b, p0/m, z0.b, z1.b
371 %cmp = icmp slt <vscale x 16 x i8> %a, %b
372 %min = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b
373 ret <vscale x 16 x i8> %min
376 define <vscale x 8 x i16> @smin_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
377 ; CHECK-LABEL: smin_i16:
379 ; CHECK-NEXT: ptrue p0.h
380 ; CHECK-NEXT: smin z0.h, p0/m, z0.h, z1.h
382 %cmp = icmp slt <vscale x 8 x i16> %a, %b
383 %min = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b
384 ret <vscale x 8 x i16> %min
387 define <vscale x 4 x i32> @smin_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
388 ; CHECK-LABEL: smin_i32:
390 ; CHECK-NEXT: ptrue p0.s
391 ; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s
393 %cmp = icmp slt <vscale x 4 x i32> %a, %b
394 %min = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b
395 ret <vscale x 4 x i32> %min
398 define <vscale x 2 x i64> @smin_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
399 ; CHECK-LABEL: smin_i64:
401 ; CHECK-NEXT: ptrue p0.d
402 ; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d
404 %cmp = icmp slt <vscale x 2 x i64> %a, %b
405 %min = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b
406 ret <vscale x 2 x i64> %min
409 define <vscale x 32 x i8> @smin_split_i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) {
410 ; CHECK-LABEL: smin_split_i8:
412 ; CHECK-NEXT: ptrue p0.b
413 ; CHECK-NEXT: smin z0.b, p0/m, z0.b, z2.b
414 ; CHECK-NEXT: smin z1.b, p0/m, z1.b, z3.b
416 %cmp = icmp slt <vscale x 32 x i8> %a, %b
417 %min = select <vscale x 32 x i1> %cmp, <vscale x 32 x i8> %a, <vscale x 32 x i8> %b
418 ret <vscale x 32 x i8> %min
421 define <vscale x 32 x i16> @smin_split_i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) {
422 ; CHECK-LABEL: smin_split_i16:
424 ; CHECK-NEXT: ptrue p0.h
425 ; CHECK-NEXT: smin z0.h, p0/m, z0.h, z4.h
426 ; CHECK-NEXT: smin z1.h, p0/m, z1.h, z5.h
427 ; CHECK-NEXT: smin z2.h, p0/m, z2.h, z6.h
428 ; CHECK-NEXT: smin z3.h, p0/m, z3.h, z7.h
430 %cmp = icmp slt <vscale x 32 x i16> %a, %b
431 %min = select <vscale x 32 x i1> %cmp, <vscale x 32 x i16> %a, <vscale x 32 x i16> %b
432 ret <vscale x 32 x i16> %min
435 define <vscale x 8 x i32> @smin_split_i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) {
436 ; CHECK-LABEL: smin_split_i32:
438 ; CHECK-NEXT: ptrue p0.s
439 ; CHECK-NEXT: smin z0.s, p0/m, z0.s, z2.s
440 ; CHECK-NEXT: smin z1.s, p0/m, z1.s, z3.s
442 %cmp = icmp slt <vscale x 8 x i32> %a, %b
443 %min = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %a, <vscale x 8 x i32> %b
444 ret <vscale x 8 x i32> %min
447 define <vscale x 4 x i64> @smin_split_i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) {
448 ; CHECK-LABEL: smin_split_i64:
450 ; CHECK-NEXT: ptrue p0.d
451 ; CHECK-NEXT: smin z0.d, p0/m, z0.d, z2.d
452 ; CHECK-NEXT: smin z1.d, p0/m, z1.d, z3.d
454 %cmp = icmp slt <vscale x 4 x i64> %a, %b
455 %min = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b
456 ret <vscale x 4 x i64> %min
459 define <vscale x 8 x i8> @smin_promote_i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
460 ; CHECK-LABEL: smin_promote_i8:
462 ; CHECK-NEXT: ptrue p0.h
463 ; CHECK-NEXT: sxtb z1.h, p0/m, z1.h
464 ; CHECK-NEXT: sxtb z0.h, p0/m, z0.h
465 ; CHECK-NEXT: smin z0.h, p0/m, z0.h, z1.h
467 %cmp = icmp slt <vscale x 8 x i8> %a, %b
468 %min = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b
469 ret <vscale x 8 x i8> %min
472 define <vscale x 4 x i16> @smin_promote_i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {
473 ; CHECK-LABEL: smin_promote_i16:
475 ; CHECK-NEXT: ptrue p0.s
476 ; CHECK-NEXT: sxth z1.s, p0/m, z1.s
477 ; CHECK-NEXT: sxth z0.s, p0/m, z0.s
478 ; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s
480 %cmp = icmp slt <vscale x 4 x i16> %a, %b
481 %min = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b
482 ret <vscale x 4 x i16> %min
485 define <vscale x 2 x i32> @smin_promote_i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
486 ; CHECK-LABEL: smin_promote_i32:
488 ; CHECK-NEXT: ptrue p0.d
489 ; CHECK-NEXT: sxtw z1.d, p0/m, z1.d
490 ; CHECK-NEXT: sxtw z0.d, p0/m, z0.d
491 ; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d
493 %cmp = icmp slt <vscale x 2 x i32> %a, %b
494 %min = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %a, <vscale x 2 x i32> %b
495 ret <vscale x 2 x i32> %min
502 define <vscale x 16 x i8> @umin_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
503 ; CHECK-LABEL: umin_i8:
505 ; CHECK-NEXT: ptrue p0.b
506 ; CHECK-NEXT: umin z0.b, p0/m, z0.b, z1.b
508 %cmp = icmp ult <vscale x 16 x i8> %a, %b
509 %min = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b
510 ret <vscale x 16 x i8> %min
513 define <vscale x 8 x i16> @umin_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
514 ; CHECK-LABEL: umin_i16:
516 ; CHECK-NEXT: ptrue p0.h
517 ; CHECK-NEXT: umin z0.h, p0/m, z0.h, z1.h
519 %cmp = icmp ult <vscale x 8 x i16> %a, %b
520 %min = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b
521 ret <vscale x 8 x i16> %min
524 define <vscale x 4 x i32> @umin_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
525 ; CHECK-LABEL: umin_i32:
527 ; CHECK-NEXT: ptrue p0.s
528 ; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s
530 %cmp = icmp ult <vscale x 4 x i32> %a, %b
531 %min = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b
532 ret <vscale x 4 x i32> %min
535 define <vscale x 2 x i64> @umin_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
536 ; CHECK-LABEL: umin_i64:
538 ; CHECK-NEXT: ptrue p0.d
539 ; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d
541 %cmp = icmp ult <vscale x 2 x i64> %a, %b
542 %min = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b
543 ret <vscale x 2 x i64> %min
546 define <vscale x 4 x i64> @umin_split_i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) {
547 ; CHECK-LABEL: umin_split_i64:
549 ; CHECK-NEXT: ptrue p0.d
550 ; CHECK-NEXT: umin z0.d, p0/m, z0.d, z2.d
551 ; CHECK-NEXT: umin z1.d, p0/m, z1.d, z3.d
553 %cmp = icmp ult <vscale x 4 x i64> %a, %b
554 %min = select <vscale x 4 x i1> %cmp, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b
555 ret <vscale x 4 x i64> %min
558 define <vscale x 8 x i8> @umin_promote_i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
559 ; CHECK-LABEL: umin_promote_i8:
561 ; CHECK-NEXT: ptrue p0.h
562 ; CHECK-NEXT: and z1.h, z1.h, #0xff
563 ; CHECK-NEXT: and z0.h, z0.h, #0xff
564 ; CHECK-NEXT: umin z0.h, p0/m, z0.h, z1.h
566 %cmp = icmp ult <vscale x 8 x i8> %a, %b
567 %min = select <vscale x 8 x i1> %cmp, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b
568 ret <vscale x 8 x i8> %min
575 define <vscale x 16 x i8> @smax_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
576 ; CHECK-LABEL: smax_i8:
578 ; CHECK-NEXT: ptrue p0.b
579 ; CHECK-NEXT: smax z0.b, p0/m, z0.b, z1.b
581 %cmp = icmp sgt <vscale x 16 x i8> %a, %b
582 %max = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b
583 ret <vscale x 16 x i8> %max
586 define <vscale x 8 x i16> @smax_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
587 ; CHECK-LABEL: smax_i16:
589 ; CHECK-NEXT: ptrue p0.h
590 ; CHECK-NEXT: smax z0.h, p0/m, z0.h, z1.h
592 %cmp = icmp sgt <vscale x 8 x i16> %a, %b
593 %max = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b
594 ret <vscale x 8 x i16> %max
597 define <vscale x 4 x i32> @smax_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
598 ; CHECK-LABEL: smax_i32:
600 ; CHECK-NEXT: ptrue p0.s
601 ; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s
603 %cmp = icmp sgt <vscale x 4 x i32> %a, %b
604 %max = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b
605 ret <vscale x 4 x i32> %max
608 define <vscale x 2 x i64> @smax_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
609 ; CHECK-LABEL: smax_i64:
611 ; CHECK-NEXT: ptrue p0.d
612 ; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d
614 %cmp = icmp sgt <vscale x 2 x i64> %a, %b
615 %max = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b
616 ret <vscale x 2 x i64> %max
619 define <vscale x 8 x i32> @smax_split_i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) {
620 ; CHECK-LABEL: smax_split_i32:
622 ; CHECK-NEXT: ptrue p0.s
623 ; CHECK-NEXT: smax z0.s, p0/m, z0.s, z2.s
624 ; CHECK-NEXT: smax z1.s, p0/m, z1.s, z3.s
626 %cmp = icmp sgt <vscale x 8 x i32> %a, %b
627 %max = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %a, <vscale x 8 x i32> %b
628 ret <vscale x 8 x i32> %max
631 define <vscale x 4 x i16> @smax_promote_i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {
632 ; CHECK-LABEL: smax_promote_i16:
634 ; CHECK-NEXT: ptrue p0.s
635 ; CHECK-NEXT: sxth z1.s, p0/m, z1.s
636 ; CHECK-NEXT: sxth z0.s, p0/m, z0.s
637 ; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s
639 %cmp = icmp sgt <vscale x 4 x i16> %a, %b
640 %max = select <vscale x 4 x i1> %cmp, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b
641 ret <vscale x 4 x i16> %max
648 define <vscale x 16 x i8> @umax_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
649 ; CHECK-LABEL: umax_i8:
651 ; CHECK-NEXT: ptrue p0.b
652 ; CHECK-NEXT: umax z0.b, p0/m, z0.b, z1.b
654 %cmp = icmp ugt <vscale x 16 x i8> %a, %b
655 %max = select <vscale x 16 x i1> %cmp, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b
656 ret <vscale x 16 x i8> %max
659 define <vscale x 8 x i16> @umax_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
660 ; CHECK-LABEL: umax_i16:
662 ; CHECK-NEXT: ptrue p0.h
663 ; CHECK-NEXT: umax z0.h, p0/m, z0.h, z1.h
665 %cmp = icmp ugt <vscale x 8 x i16> %a, %b
666 %max = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b
667 ret <vscale x 8 x i16> %max
670 define <vscale x 4 x i32> @umax_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
671 ; CHECK-LABEL: umax_i32:
673 ; CHECK-NEXT: ptrue p0.s
674 ; CHECK-NEXT: umax z0.s, p0/m, z0.s, z1.s
676 %cmp = icmp ugt <vscale x 4 x i32> %a, %b
677 %max = select <vscale x 4 x i1> %cmp, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b
678 ret <vscale x 4 x i32> %max
681 define <vscale x 2 x i64> @umax_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
682 ; CHECK-LABEL: umax_i64:
684 ; CHECK-NEXT: ptrue p0.d
685 ; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d
687 %cmp = icmp ugt <vscale x 2 x i64> %a, %b
688 %max = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b
689 ret <vscale x 2 x i64> %max
692 define <vscale x 16 x i16> @umax_split_i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) {
693 ; CHECK-LABEL: umax_split_i16:
695 ; CHECK-NEXT: ptrue p0.h
696 ; CHECK-NEXT: umax z0.h, p0/m, z0.h, z2.h
697 ; CHECK-NEXT: umax z1.h, p0/m, z1.h, z3.h
699 %cmp = icmp ugt <vscale x 16 x i16> %a, %b
700 %max = select <vscale x 16 x i1> %cmp, <vscale x 16 x i16> %a, <vscale x 16 x i16> %b
701 ret <vscale x 16 x i16> %max
704 define <vscale x 2 x i32> @umax_promote_i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
705 ; CHECK-LABEL: umax_promote_i32:
707 ; CHECK-NEXT: ptrue p0.d
708 ; CHECK-NEXT: and z1.d, z1.d, #0xffffffff
709 ; CHECK-NEXT: and z0.d, z0.d, #0xffffffff
710 ; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d
712 %cmp = icmp ugt <vscale x 2 x i32> %a, %b
713 %max = select <vscale x 2 x i1> %cmp, <vscale x 2 x i32> %a, <vscale x 2 x i32> %b
714 ret <vscale x 2 x i32> %max
721 define <vscale x 16 x i8> @asr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b){
722 ; CHECK-LABEL: asr_i8:
724 ; CHECK-NEXT: ptrue p0.b
725 ; CHECK-NEXT: asr z0.b, p0/m, z0.b, z1.b
727 %shr = ashr <vscale x 16 x i8> %a, %b
728 ret <vscale x 16 x i8> %shr
731 define <vscale x 8 x i16> @asr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b){
732 ; CHECK-LABEL: asr_i16:
734 ; CHECK-NEXT: ptrue p0.h
735 ; CHECK-NEXT: asr z0.h, p0/m, z0.h, z1.h
737 %shr = ashr <vscale x 8 x i16> %a, %b
738 ret <vscale x 8 x i16> %shr
741 define <vscale x 4 x i32> @asr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b){
742 ; CHECK-LABEL: asr_i32:
744 ; CHECK-NEXT: ptrue p0.s
745 ; CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.s
747 %shr = ashr <vscale x 4 x i32> %a, %b
748 ret <vscale x 4 x i32> %shr
751 define <vscale x 2 x i64> @asr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b){
752 ; CHECK-LABEL: asr_i64:
754 ; CHECK-NEXT: ptrue p0.d
755 ; CHECK-NEXT: asr z0.d, p0/m, z0.d, z1.d
757 %shr = ashr <vscale x 2 x i64> %a, %b
758 ret <vscale x 2 x i64> %shr
761 define <vscale x 16 x i16> @asr_split_i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b){
762 ; CHECK-LABEL: asr_split_i16:
764 ; CHECK-NEXT: ptrue p0.h
765 ; CHECK-NEXT: asr z0.h, p0/m, z0.h, z2.h
766 ; CHECK-NEXT: asr z1.h, p0/m, z1.h, z3.h
768 %shr = ashr <vscale x 16 x i16> %a, %b
769 ret <vscale x 16 x i16> %shr
772 define <vscale x 2 x i32> @asr_promote_i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b){
773 ; CHECK-LABEL: asr_promote_i32:
775 ; CHECK-NEXT: ptrue p0.d
776 ; CHECK-NEXT: and z1.d, z1.d, #0xffffffff
777 ; CHECK-NEXT: sxtw z0.d, p0/m, z0.d
778 ; CHECK-NEXT: asr z0.d, p0/m, z0.d, z1.d
780 %shr = ashr <vscale x 2 x i32> %a, %b
781 ret <vscale x 2 x i32> %shr
788 define <vscale x 16 x i8> @asrr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b){
789 ; CHECK-LABEL: asrr_i8:
791 ; CHECK-NEXT: ptrue p0.b
792 ; CHECK-NEXT: asrr z0.b, p0/m, z0.b, z1.b
794 %shr = ashr <vscale x 16 x i8> %b, %a
795 ret <vscale x 16 x i8> %shr
798 define <vscale x 8 x i16> @asrr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b){
799 ; CHECK-LABEL: asrr_i16:
801 ; CHECK-NEXT: ptrue p0.h
802 ; CHECK-NEXT: asrr z0.h, p0/m, z0.h, z1.h
804 %shr = ashr <vscale x 8 x i16> %b, %a
805 ret <vscale x 8 x i16> %shr
808 define <vscale x 4 x i32> @asrr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b){
809 ; CHECK-LABEL: asrr_i32:
811 ; CHECK-NEXT: ptrue p0.s
812 ; CHECK-NEXT: asrr z0.s, p0/m, z0.s, z1.s
814 %shr = ashr <vscale x 4 x i32> %b, %a
815 ret <vscale x 4 x i32> %shr
818 define <vscale x 2 x i64> @asrr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b){
819 ; CHECK-LABEL: asrr_i64:
821 ; CHECK-NEXT: ptrue p0.d
822 ; CHECK-NEXT: asrr z0.d, p0/m, z0.d, z1.d
824 %shr = ashr <vscale x 2 x i64> %b, %a
825 ret <vscale x 2 x i64> %shr
832 define <vscale x 16 x i8> @lsl_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b){
833 ; CHECK-LABEL: lsl_i8:
835 ; CHECK-NEXT: ptrue p0.b
836 ; CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.b
838 %shl = shl <vscale x 16 x i8> %a, %b
839 ret <vscale x 16 x i8> %shl
842 define <vscale x 8 x i16> @lsl_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b){
843 ; CHECK-LABEL: lsl_i16:
845 ; CHECK-NEXT: ptrue p0.h
846 ; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h
848 %shl = shl <vscale x 8 x i16> %a, %b
849 ret <vscale x 8 x i16> %shl
852 define <vscale x 4 x i32> @lsl_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b){
853 ; CHECK-LABEL: lsl_i32:
855 ; CHECK-NEXT: ptrue p0.s
856 ; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s
858 %shl = shl <vscale x 4 x i32> %a, %b
859 ret <vscale x 4 x i32> %shl
862 define <vscale x 2 x i64> @lsl_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b){
863 ; CHECK-LABEL: lsl_i64:
865 ; CHECK-NEXT: ptrue p0.d
866 ; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d
868 %shl = shl <vscale x 2 x i64> %a, %b
869 ret <vscale x 2 x i64> %shl
872 define <vscale x 4 x i64> @lsl_split_i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b){
873 ; CHECK-LABEL: lsl_split_i64:
875 ; CHECK-NEXT: ptrue p0.d
876 ; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z2.d
877 ; CHECK-NEXT: lsl z1.d, p0/m, z1.d, z3.d
879 %shl = shl <vscale x 4 x i64> %a, %b
880 ret <vscale x 4 x i64> %shl
883 define <vscale x 4 x i16> @lsl_promote_i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b){
884 ; CHECK-LABEL: lsl_promote_i16:
886 ; CHECK-NEXT: ptrue p0.s
887 ; CHECK-NEXT: and z1.s, z1.s, #0xffff
888 ; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s
890 %shl = shl <vscale x 4 x i16> %a, %b
891 ret <vscale x 4 x i16> %shl
898 define <vscale x 16 x i8> @lslr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b){
899 ; CHECK-LABEL: lslr_i8:
901 ; CHECK-NEXT: ptrue p0.b
902 ; CHECK-NEXT: lslr z0.b, p0/m, z0.b, z1.b
904 %shl = shl <vscale x 16 x i8> %b, %a
905 ret <vscale x 16 x i8> %shl
908 define <vscale x 8 x i16> @lslr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b){
909 ; CHECK-LABEL: lslr_i16:
911 ; CHECK-NEXT: ptrue p0.h
912 ; CHECK-NEXT: lslr z0.h, p0/m, z0.h, z1.h
914 %shl = shl <vscale x 8 x i16> %b, %a
915 ret <vscale x 8 x i16> %shl
918 define <vscale x 4 x i32> @lslr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b){
919 ; CHECK-LABEL: lslr_i32:
921 ; CHECK-NEXT: ptrue p0.s
922 ; CHECK-NEXT: lslr z0.s, p0/m, z0.s, z1.s
924 %shl = shl <vscale x 4 x i32> %b, %a
925 ret <vscale x 4 x i32> %shl
928 define <vscale x 2 x i64> @lslr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b){
929 ; CHECK-LABEL: lslr_i64:
931 ; CHECK-NEXT: ptrue p0.d
932 ; CHECK-NEXT: lslr z0.d, p0/m, z0.d, z1.d
934 %shl = shl <vscale x 2 x i64> %b, %a
935 ret <vscale x 2 x i64> %shl
942 define <vscale x 16 x i8> @lsr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b){
943 ; CHECK-LABEL: lsr_i8:
945 ; CHECK-NEXT: ptrue p0.b
946 ; CHECK-NEXT: lsr z0.b, p0/m, z0.b, z1.b
948 %shr = lshr <vscale x 16 x i8> %a, %b
949 ret <vscale x 16 x i8> %shr
952 define <vscale x 8 x i16> @lsr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b){
953 ; CHECK-LABEL: lsr_i16:
955 ; CHECK-NEXT: ptrue p0.h
956 ; CHECK-NEXT: lsr z0.h, p0/m, z0.h, z1.h
958 %shr = lshr <vscale x 8 x i16> %a, %b
959 ret <vscale x 8 x i16> %shr
962 define <vscale x 4 x i32> @lsr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b){
963 ; CHECK-LABEL: lsr_i32:
965 ; CHECK-NEXT: ptrue p0.s
966 ; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z1.s
968 %shr = lshr <vscale x 4 x i32> %a, %b
969 ret <vscale x 4 x i32> %shr
972 define <vscale x 2 x i64> @lsr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b){
973 ; CHECK-LABEL: lsr_i64:
975 ; CHECK-NEXT: ptrue p0.d
976 ; CHECK-NEXT: lsr z0.d, p0/m, z0.d, z1.d
978 %shr = lshr <vscale x 2 x i64> %a, %b
979 ret <vscale x 2 x i64> %shr
982 define <vscale x 8 x i8> @lsr_promote_i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b){
983 ; CHECK-LABEL: lsr_promote_i8:
985 ; CHECK-NEXT: ptrue p0.h
986 ; CHECK-NEXT: and z1.h, z1.h, #0xff
987 ; CHECK-NEXT: and z0.h, z0.h, #0xff
988 ; CHECK-NEXT: lsr z0.h, p0/m, z0.h, z1.h
990 %shr = lshr <vscale x 8 x i8> %a, %b
991 ret <vscale x 8 x i8> %shr
994 define <vscale x 8 x i32> @lsr_split_i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b){
995 ; CHECK-LABEL: lsr_split_i32:
997 ; CHECK-NEXT: ptrue p0.s
998 ; CHECK-NEXT: lsr z0.s, p0/m, z0.s, z2.s
999 ; CHECK-NEXT: lsr z1.s, p0/m, z1.s, z3.s
1001 %shr = lshr <vscale x 8 x i32> %a, %b
1002 ret <vscale x 8 x i32> %shr
1009 define <vscale x 16 x i8> @lsrr_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b){
1010 ; CHECK-LABEL: lsrr_i8:
1012 ; CHECK-NEXT: ptrue p0.b
1013 ; CHECK-NEXT: lsrr z0.b, p0/m, z0.b, z1.b
1015 %shr = lshr <vscale x 16 x i8> %b, %a
1016 ret <vscale x 16 x i8> %shr
1019 define <vscale x 8 x i16> @lsrr_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b){
1020 ; CHECK-LABEL: lsrr_i16:
1022 ; CHECK-NEXT: ptrue p0.h
1023 ; CHECK-NEXT: lsrr z0.h, p0/m, z0.h, z1.h
1025 %shr = lshr <vscale x 8 x i16> %b, %a
1026 ret <vscale x 8 x i16> %shr
1029 define <vscale x 4 x i32> @lsrr_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b){
1030 ; CHECK-LABEL: lsrr_i32:
1032 ; CHECK-NEXT: ptrue p0.s
1033 ; CHECK-NEXT: lsrr z0.s, p0/m, z0.s, z1.s
1035 %shr = lshr <vscale x 4 x i32> %b, %a
1036 ret <vscale x 4 x i32> %shr
1039 define <vscale x 2 x i64> @lsrr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b){
1040 ; CHECK-LABEL: lsrr_i64:
1042 ; CHECK-NEXT: ptrue p0.d
1043 ; CHECK-NEXT: lsrr z0.d, p0/m, z0.d, z1.d
1045 %shr = lshr <vscale x 2 x i64> %b, %a
1046 ret <vscale x 2 x i64> %shr
1053 define <vscale x 32 x i1> @cmp_split_32(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) {
1054 ; CHECK-LABEL: cmp_split_32:
1056 ; CHECK-NEXT: ptrue p1.b
1057 ; CHECK-NEXT: cmpgt p0.b, p1/z, z2.b, z0.b
1058 ; CHECK-NEXT: cmpgt p1.b, p1/z, z3.b, z1.b
1060 %cmp = icmp slt <vscale x 32 x i8> %a, %b
1061 ret <vscale x 32 x i1> %cmp
1064 define <vscale x 64 x i1> @cmp_split_64(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) {
1065 ; CHECK-LABEL: cmp_split_64:
1067 ; CHECK-NEXT: ptrue p3.b
1068 ; CHECK-NEXT: cmpgt p0.b, p3/z, z0.b, z4.b
1069 ; CHECK-NEXT: cmpgt p1.b, p3/z, z1.b, z5.b
1070 ; CHECK-NEXT: cmpgt p2.b, p3/z, z2.b, z6.b
1071 ; CHECK-NEXT: cmpgt p3.b, p3/z, z3.b, z7.b
1073 %cmp = icmp sgt <vscale x 64 x i8> %a, %b
1074 ret <vscale x 64 x i1> %cmp
1078 declare <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
1079 declare <vscale x 4 x i64> @llvm.fshl.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i64>)
1080 declare <vscale x 2 x i64> @llvm.fshr.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
1081 define <vscale x 2 x i64> @fshl_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c){
1082 ; CHECK-LABEL: fshl_i64:
1084 ; CHECK-NEXT: ptrue p0.d
1085 ; CHECK-NEXT: mov z3.d, #63 // =0x3f
1086 ; CHECK-NEXT: mov z4.d, z2.d
1087 ; CHECK-NEXT: lsr z1.d, z1.d, #1
1088 ; CHECK-NEXT: bic z2.d, z3.d, z2.d
1089 ; CHECK-NEXT: and z4.d, z4.d, #0x3f
1090 ; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z4.d
1091 ; CHECK-NEXT: lsr z1.d, p0/m, z1.d, z2.d
1092 ; CHECK-NEXT: orr z0.d, z0.d, z1.d
1094 %fshl = call <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c)
1095 ret <vscale x 2 x i64> %fshl
1098 define <vscale x 4 x i64> @fshl_illegal_i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, <vscale x 4 x i64> %c){
1099 ; CHECK-LABEL: fshl_illegal_i64:
1101 ; CHECK-NEXT: ptrue p0.d
1102 ; CHECK-NEXT: mov z6.d, #63 // =0x3f
1103 ; CHECK-NEXT: mov z7.d, z4.d
1104 ; CHECK-NEXT: lsr z2.d, z2.d, #1
1105 ; CHECK-NEXT: lsr z3.d, z3.d, #1
1106 ; CHECK-NEXT: bic z4.d, z6.d, z4.d
1107 ; CHECK-NEXT: and z7.d, z7.d, #0x3f
1108 ; CHECK-NEXT: bic z6.d, z6.d, z5.d
1109 ; CHECK-NEXT: and z5.d, z5.d, #0x3f
1110 ; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z7.d
1111 ; CHECK-NEXT: lsr z2.d, p0/m, z2.d, z4.d
1112 ; CHECK-NEXT: lsr z3.d, p0/m, z3.d, z6.d
1113 ; CHECK-NEXT: lsl z1.d, p0/m, z1.d, z5.d
1114 ; CHECK-NEXT: orr z0.d, z0.d, z2.d
1115 ; CHECK-NEXT: orr z1.d, z1.d, z3.d
1117 %fshl = call <vscale x 4 x i64> @llvm.fshl.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b, <vscale x 4 x i64> %c)
1118 ret <vscale x 4 x i64> %fshl
1121 define <vscale x 2 x i64> @fshl_rot_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b){
1122 ; CHECK-LABEL: fshl_rot_i64:
1124 ; CHECK-NEXT: ptrue p0.d
1125 ; CHECK-NEXT: mov z2.d, z1.d
1126 ; CHECK-NEXT: subr z1.d, z1.d, #0 // =0x0
1127 ; CHECK-NEXT: and z2.d, z2.d, #0x3f
1128 ; CHECK-NEXT: and z1.d, z1.d, #0x3f
1129 ; CHECK-NEXT: lslr z2.d, p0/m, z2.d, z0.d
1130 ; CHECK-NEXT: lsr z0.d, p0/m, z0.d, z1.d
1131 ; CHECK-NEXT: orr z0.d, z2.d, z0.d
1133 %fshl = call <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
1134 ret <vscale x 2 x i64> %fshl
1138 define <vscale x 4 x i64> @fshl_rot_illegal_i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b){
1139 ; CHECK-LABEL: fshl_rot_illegal_i64:
1141 ; CHECK-NEXT: ptrue p0.d
1142 ; CHECK-NEXT: mov z4.d, z2.d
1143 ; CHECK-NEXT: subr z2.d, z2.d, #0 // =0x0
1144 ; CHECK-NEXT: mov z5.d, z3.d
1145 ; CHECK-NEXT: subr z3.d, z3.d, #0 // =0x0
1146 ; CHECK-NEXT: and z4.d, z4.d, #0x3f
1147 ; CHECK-NEXT: and z2.d, z2.d, #0x3f
1148 ; CHECK-NEXT: and z3.d, z3.d, #0x3f
1149 ; CHECK-NEXT: and z5.d, z5.d, #0x3f
1150 ; CHECK-NEXT: lslr z4.d, p0/m, z4.d, z0.d
1151 ; CHECK-NEXT: lsr z0.d, p0/m, z0.d, z2.d
1152 ; CHECK-NEXT: movprfx z2, z1
1153 ; CHECK-NEXT: lsl z2.d, p0/m, z2.d, z5.d
1154 ; CHECK-NEXT: lsr z1.d, p0/m, z1.d, z3.d
1155 ; CHECK-NEXT: orr z0.d, z4.d, z0.d
1156 ; CHECK-NEXT: orr z1.d, z2.d, z1.d
1158 %fshl = call <vscale x 4 x i64> @llvm.fshl.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b)
1159 ret <vscale x 4 x i64> %fshl
1162 define <vscale x 2 x i64> @fshl_rot_const_i64(<vscale x 2 x i64> %a){
1163 ; CHECK-LABEL: fshl_rot_const_i64:
1165 ; CHECK-NEXT: lsr z1.d, z0.d, #61
1166 ; CHECK-NEXT: lsl z0.d, z0.d, #3
1167 ; CHECK-NEXT: orr z0.d, z0.d, z1.d
1169 %insert = insertelement <vscale x 2 x i64> poison, i64 3, i32 0
1170 %shuf = shufflevector <vscale x 2 x i64> %insert, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
1171 %fshl = call <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> %shuf)
1172 ret <vscale x 2 x i64> %fshl
1175 define <vscale x 2 x i64> @fshr_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c){
1176 ; CHECK-LABEL: fshr_i64:
1178 ; CHECK-NEXT: ptrue p0.d
1179 ; CHECK-NEXT: mov z3.d, #63 // =0x3f
1180 ; CHECK-NEXT: mov z4.d, z2.d
1181 ; CHECK-NEXT: lsl z0.d, z0.d, #1
1182 ; CHECK-NEXT: bic z2.d, z3.d, z2.d
1183 ; CHECK-NEXT: and z4.d, z4.d, #0x3f
1184 ; CHECK-NEXT: lsr z1.d, p0/m, z1.d, z4.d
1185 ; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z2.d
1186 ; CHECK-NEXT: orr z0.d, z0.d, z1.d
1188 %fshr = call <vscale x 2 x i64> @llvm.fshr.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c)
1189 ret <vscale x 2 x i64> %fshr
1192 define <vscale x 2 x i64> @fshr_rot_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b){
1193 ; CHECK-LABEL: fshr_rot_i64:
1195 ; CHECK-NEXT: ptrue p0.d
1196 ; CHECK-NEXT: mov z2.d, z1.d
1197 ; CHECK-NEXT: subr z1.d, z1.d, #0 // =0x0
1198 ; CHECK-NEXT: and z2.d, z2.d, #0x3f
1199 ; CHECK-NEXT: and z1.d, z1.d, #0x3f
1200 ; CHECK-NEXT: lsrr z2.d, p0/m, z2.d, z0.d
1201 ; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d
1202 ; CHECK-NEXT: orr z0.d, z2.d, z0.d
1204 %fshr = call <vscale x 2 x i64> @llvm.fshr.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
1205 ret <vscale x 2 x i64> %fshr