1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
4 declare <1 x i8> @llvm.ssub.sat.v1i8(<1 x i8>, <1 x i8>)
5 declare <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8>, <2 x i8>)
6 declare <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8>, <4 x i8>)
7 declare <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8>, <8 x i8>)
8 declare <12 x i8> @llvm.ssub.sat.v12i8(<12 x i8>, <12 x i8>)
9 declare <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8>, <16 x i8>)
10 declare <32 x i8> @llvm.ssub.sat.v32i8(<32 x i8>, <32 x i8>)
11 declare <64 x i8> @llvm.ssub.sat.v64i8(<64 x i8>, <64 x i8>)
13 declare <1 x i16> @llvm.ssub.sat.v1i16(<1 x i16>, <1 x i16>)
14 declare <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16>, <2 x i16>)
15 declare <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16>, <4 x i16>)
16 declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>)
17 declare <12 x i16> @llvm.ssub.sat.v12i16(<12 x i16>, <12 x i16>)
18 declare <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16>, <16 x i16>)
19 declare <32 x i16> @llvm.ssub.sat.v32i16(<32 x i16>, <32 x i16>)
21 declare <16 x i1> @llvm.ssub.sat.v16i1(<16 x i1>, <16 x i1>)
22 declare <16 x i4> @llvm.ssub.sat.v16i4(<16 x i4>, <16 x i4>)
24 declare <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32>, <2 x i32>)
25 declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)
26 declare <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32>, <8 x i32>)
27 declare <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32>, <16 x i32>)
28 declare <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64>, <2 x i64>)
29 declare <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64>, <4 x i64>)
30 declare <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64>, <8 x i64>)
32 declare <4 x i24> @llvm.ssub.sat.v4i24(<4 x i24>, <4 x i24>)
33 declare <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128>, <2 x i128>)
36 define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
39 ; CHECK-NEXT: sqsub v0.16b, v0.16b, v1.16b
41 %z = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
45 define <32 x i8> @v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {
48 ; CHECK-NEXT: sqsub v1.16b, v1.16b, v3.16b
49 ; CHECK-NEXT: sqsub v0.16b, v0.16b, v2.16b
51 %z = call <32 x i8> @llvm.ssub.sat.v32i8(<32 x i8> %x, <32 x i8> %y)
55 define <64 x i8> @v64i8(<64 x i8> %x, <64 x i8> %y) nounwind {
58 ; CHECK-NEXT: sqsub v2.16b, v2.16b, v6.16b
59 ; CHECK-NEXT: sqsub v0.16b, v0.16b, v4.16b
60 ; CHECK-NEXT: sqsub v1.16b, v1.16b, v5.16b
61 ; CHECK-NEXT: sqsub v3.16b, v3.16b, v7.16b
63 %z = call <64 x i8> @llvm.ssub.sat.v64i8(<64 x i8> %x, <64 x i8> %y)
67 define <8 x i16> @v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
70 ; CHECK-NEXT: sqsub v0.8h, v0.8h, v1.8h
72 %z = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
76 define <16 x i16> @v16i16(<16 x i16> %x, <16 x i16> %y) nounwind {
77 ; CHECK-LABEL: v16i16:
79 ; CHECK-NEXT: sqsub v1.8h, v1.8h, v3.8h
80 ; CHECK-NEXT: sqsub v0.8h, v0.8h, v2.8h
82 %z = call <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16> %x, <16 x i16> %y)
86 define <32 x i16> @v32i16(<32 x i16> %x, <32 x i16> %y) nounwind {
87 ; CHECK-LABEL: v32i16:
89 ; CHECK-NEXT: sqsub v2.8h, v2.8h, v6.8h
90 ; CHECK-NEXT: sqsub v0.8h, v0.8h, v4.8h
91 ; CHECK-NEXT: sqsub v1.8h, v1.8h, v5.8h
92 ; CHECK-NEXT: sqsub v3.8h, v3.8h, v7.8h
94 %z = call <32 x i16> @llvm.ssub.sat.v32i16(<32 x i16> %x, <32 x i16> %y)
98 define void @v8i8(ptr %px, ptr %py, ptr %pz) nounwind {
101 ; CHECK-NEXT: ldr d0, [x0]
102 ; CHECK-NEXT: ldr d1, [x1]
103 ; CHECK-NEXT: sqsub v0.8b, v0.8b, v1.8b
104 ; CHECK-NEXT: str d0, [x2]
106 %x = load <8 x i8>, ptr %px
107 %y = load <8 x i8>, ptr %py
108 %z = call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> %x, <8 x i8> %y)
109 store <8 x i8> %z, ptr %pz
113 define void @v4i8(ptr %px, ptr %py, ptr %pz) nounwind {
116 ; CHECK-NEXT: ldr s0, [x0]
117 ; CHECK-NEXT: ldr s1, [x1]
118 ; CHECK-NEXT: sshll v0.8h, v0.8b, #0
119 ; CHECK-NEXT: sshll v1.8h, v1.8b, #0
120 ; CHECK-NEXT: shl v1.4h, v1.4h, #8
121 ; CHECK-NEXT: shl v0.4h, v0.4h, #8
122 ; CHECK-NEXT: sqsub v0.4h, v0.4h, v1.4h
123 ; CHECK-NEXT: sshr v0.4h, v0.4h, #8
124 ; CHECK-NEXT: xtn v0.8b, v0.8h
125 ; CHECK-NEXT: str s0, [x2]
127 %x = load <4 x i8>, ptr %px
128 %y = load <4 x i8>, ptr %py
129 %z = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> %x, <4 x i8> %y)
130 store <4 x i8> %z, ptr %pz
134 define void @v2i8(ptr %px, ptr %py, ptr %pz) nounwind {
137 ; CHECK-NEXT: ld1 { v0.b }[0], [x0]
138 ; CHECK-NEXT: ld1 { v1.b }[0], [x1]
139 ; CHECK-NEXT: add x8, x0, #1
140 ; CHECK-NEXT: add x9, x1, #1
141 ; CHECK-NEXT: ld1 { v0.b }[4], [x8]
142 ; CHECK-NEXT: ld1 { v1.b }[4], [x9]
143 ; CHECK-NEXT: shl v1.2s, v1.2s, #24
144 ; CHECK-NEXT: shl v0.2s, v0.2s, #24
145 ; CHECK-NEXT: sqsub v0.2s, v0.2s, v1.2s
146 ; CHECK-NEXT: ushr v0.2s, v0.2s, #24
147 ; CHECK-NEXT: mov w8, v0.s[1]
148 ; CHECK-NEXT: fmov w9, s0
149 ; CHECK-NEXT: strb w9, [x2]
150 ; CHECK-NEXT: strb w8, [x2, #1]
152 %x = load <2 x i8>, ptr %px
153 %y = load <2 x i8>, ptr %py
154 %z = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %x, <2 x i8> %y)
155 store <2 x i8> %z, ptr %pz
159 define void @v4i16(ptr %px, ptr %py, ptr %pz) nounwind {
160 ; CHECK-LABEL: v4i16:
162 ; CHECK-NEXT: ldr d0, [x0]
163 ; CHECK-NEXT: ldr d1, [x1]
164 ; CHECK-NEXT: sqsub v0.4h, v0.4h, v1.4h
165 ; CHECK-NEXT: str d0, [x2]
167 %x = load <4 x i16>, ptr %px
168 %y = load <4 x i16>, ptr %py
169 %z = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %x, <4 x i16> %y)
170 store <4 x i16> %z, ptr %pz
174 define void @v2i16(ptr %px, ptr %py, ptr %pz) nounwind {
175 ; CHECK-LABEL: v2i16:
177 ; CHECK-NEXT: ld1 { v0.h }[0], [x0]
178 ; CHECK-NEXT: ld1 { v1.h }[0], [x1]
179 ; CHECK-NEXT: add x8, x0, #2
180 ; CHECK-NEXT: add x9, x1, #2
181 ; CHECK-NEXT: ld1 { v0.h }[2], [x8]
182 ; CHECK-NEXT: ld1 { v1.h }[2], [x9]
183 ; CHECK-NEXT: shl v1.2s, v1.2s, #16
184 ; CHECK-NEXT: shl v0.2s, v0.2s, #16
185 ; CHECK-NEXT: sqsub v0.2s, v0.2s, v1.2s
186 ; CHECK-NEXT: ushr v0.2s, v0.2s, #16
187 ; CHECK-NEXT: mov w8, v0.s[1]
188 ; CHECK-NEXT: fmov w9, s0
189 ; CHECK-NEXT: strh w9, [x2]
190 ; CHECK-NEXT: strh w8, [x2, #2]
192 %x = load <2 x i16>, ptr %px
193 %y = load <2 x i16>, ptr %py
194 %z = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %x, <2 x i16> %y)
195 store <2 x i16> %z, ptr %pz
199 define <12 x i8> @v12i8(<12 x i8> %x, <12 x i8> %y) nounwind {
200 ; CHECK-LABEL: v12i8:
202 ; CHECK-NEXT: sqsub v0.16b, v0.16b, v1.16b
204 %z = call <12 x i8> @llvm.ssub.sat.v12i8(<12 x i8> %x, <12 x i8> %y)
208 define void @v12i16(ptr %px, ptr %py, ptr %pz) nounwind {
209 ; CHECK-LABEL: v12i16:
211 ; CHECK-NEXT: ldp q0, q3, [x1]
212 ; CHECK-NEXT: ldp q1, q2, [x0]
213 ; CHECK-NEXT: sqsub v0.8h, v1.8h, v0.8h
214 ; CHECK-NEXT: sqsub v1.8h, v2.8h, v3.8h
215 ; CHECK-NEXT: str q0, [x2]
216 ; CHECK-NEXT: str d1, [x2, #16]
218 %x = load <12 x i16>, ptr %px
219 %y = load <12 x i16>, ptr %py
220 %z = call <12 x i16> @llvm.ssub.sat.v12i16(<12 x i16> %x, <12 x i16> %y)
221 store <12 x i16> %z, ptr %pz
225 define void @v1i8(ptr %px, ptr %py, ptr %pz) nounwind {
228 ; CHECK-NEXT: ldr b0, [x0]
229 ; CHECK-NEXT: ldr b1, [x1]
230 ; CHECK-NEXT: sqsub v0.8b, v0.8b, v1.8b
231 ; CHECK-NEXT: st1 { v0.b }[0], [x2]
233 %x = load <1 x i8>, ptr %px
234 %y = load <1 x i8>, ptr %py
235 %z = call <1 x i8> @llvm.ssub.sat.v1i8(<1 x i8> %x, <1 x i8> %y)
236 store <1 x i8> %z, ptr %pz
240 define void @v1i16(ptr %px, ptr %py, ptr %pz) nounwind {
241 ; CHECK-LABEL: v1i16:
243 ; CHECK-NEXT: ldr h0, [x0]
244 ; CHECK-NEXT: ldr h1, [x1]
245 ; CHECK-NEXT: sqsub v0.4h, v0.4h, v1.4h
246 ; CHECK-NEXT: str h0, [x2]
248 %x = load <1 x i16>, ptr %px
249 %y = load <1 x i16>, ptr %py
250 %z = call <1 x i16> @llvm.ssub.sat.v1i16(<1 x i16> %x, <1 x i16> %y)
251 store <1 x i16> %z, ptr %pz
255 define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
256 ; CHECK-LABEL: v16i4:
258 ; CHECK-NEXT: shl v0.16b, v0.16b, #4
259 ; CHECK-NEXT: shl v1.16b, v1.16b, #4
260 ; CHECK-NEXT: sshr v0.16b, v0.16b, #4
261 ; CHECK-NEXT: sshr v1.16b, v1.16b, #4
262 ; CHECK-NEXT: shl v1.16b, v1.16b, #4
263 ; CHECK-NEXT: shl v0.16b, v0.16b, #4
264 ; CHECK-NEXT: sqsub v0.16b, v0.16b, v1.16b
265 ; CHECK-NEXT: sshr v0.16b, v0.16b, #4
267 %z = call <16 x i4> @llvm.ssub.sat.v16i4(<16 x i4> %x, <16 x i4> %y)
271 define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind {
272 ; CHECK-LABEL: v16i1:
274 ; CHECK-NEXT: movi v2.16b, #1
275 ; CHECK-NEXT: eor v1.16b, v1.16b, v2.16b
276 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
278 %z = call <16 x i1> @llvm.ssub.sat.v16i1(<16 x i1> %x, <16 x i1> %y)
282 define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
283 ; CHECK-LABEL: v2i32:
285 ; CHECK-NEXT: sqsub v0.2s, v0.2s, v1.2s
287 %z = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %x, <2 x i32> %y)
291 define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
292 ; CHECK-LABEL: v4i32:
294 ; CHECK-NEXT: sqsub v0.4s, v0.4s, v1.4s
296 %z = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
300 define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind {
301 ; CHECK-LABEL: v8i32:
303 ; CHECK-NEXT: sqsub v1.4s, v1.4s, v3.4s
304 ; CHECK-NEXT: sqsub v0.4s, v0.4s, v2.4s
306 %z = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> %x, <8 x i32> %y)
310 define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
311 ; CHECK-LABEL: v16i32:
313 ; CHECK-NEXT: sqsub v2.4s, v2.4s, v6.4s
314 ; CHECK-NEXT: sqsub v0.4s, v0.4s, v4.4s
315 ; CHECK-NEXT: sqsub v1.4s, v1.4s, v5.4s
316 ; CHECK-NEXT: sqsub v3.4s, v3.4s, v7.4s
318 %z = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %x, <16 x i32> %y)
322 define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
323 ; CHECK-LABEL: v2i64:
325 ; CHECK-NEXT: sqsub v0.2d, v0.2d, v1.2d
327 %z = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %x, <2 x i64> %y)
331 define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
332 ; CHECK-LABEL: v4i64:
334 ; CHECK-NEXT: sqsub v1.2d, v1.2d, v3.2d
335 ; CHECK-NEXT: sqsub v0.2d, v0.2d, v2.2d
337 %z = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> %x, <4 x i64> %y)
341 define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
342 ; CHECK-LABEL: v8i64:
344 ; CHECK-NEXT: sqsub v2.2d, v2.2d, v6.2d
345 ; CHECK-NEXT: sqsub v0.2d, v0.2d, v4.2d
346 ; CHECK-NEXT: sqsub v1.2d, v1.2d, v5.2d
347 ; CHECK-NEXT: sqsub v3.2d, v3.2d, v7.2d
349 %z = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> %x, <8 x i64> %y)
353 define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
354 ; CHECK-LABEL: v2i128:
356 ; CHECK-NEXT: subs x8, x2, x6
357 ; CHECK-NEXT: sbcs x9, x3, x7
358 ; CHECK-NEXT: asr x10, x9, #63
359 ; CHECK-NEXT: eor x11, x10, #0x8000000000000000
360 ; CHECK-NEXT: csel x2, x10, x8, vs
361 ; CHECK-NEXT: csel x3, x11, x9, vs
362 ; CHECK-NEXT: subs x8, x0, x4
363 ; CHECK-NEXT: sbcs x9, x1, x5
364 ; CHECK-NEXT: asr x10, x9, #63
365 ; CHECK-NEXT: csel x8, x10, x8, vs
366 ; CHECK-NEXT: eor x11, x10, #0x8000000000000000
367 ; CHECK-NEXT: fmov d0, x8
368 ; CHECK-NEXT: csel x1, x11, x9, vs
369 ; CHECK-NEXT: mov v0.d[1], x1
370 ; CHECK-NEXT: fmov x0, d0
372 %z = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %x, <2 x i128> %y)