1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
3 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme < %s | FileCheck %s
5 ; Since UQDEC{B|H|W|D|P} and UQINC{B|H|W|D|P} have identical semantics, the tests for
6 ; * @llvm.aarch64.sve.uqinc{b|h|w|d|p}, and
7 ; * @llvm.aarch64.sve.uqdec{b|h|w|d|p}
8 ; should also be identical (with the instruction name being adjusted). When
9 ; updating this file remember to make similar changes in the file testing the
16 define <vscale x 8 x i16> @uqdech(<vscale x 8 x i16> %a) {
17 ; CHECK-LABEL: uqdech:
19 ; CHECK-NEXT: uqdech z0.h, pow2
21 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16> %a,
23 ret <vscale x 8 x i16> %out
30 define <vscale x 4 x i32> @uqdecw(<vscale x 4 x i32> %a) {
31 ; CHECK-LABEL: uqdecw:
33 ; CHECK-NEXT: uqdecw z0.s, vl1, mul #2
35 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqdecw.nxv4i32(<vscale x 4 x i32> %a,
37 ret <vscale x 4 x i32> %out
44 define <vscale x 2 x i64> @uqdecd(<vscale x 2 x i64> %a) {
45 ; CHECK-LABEL: uqdecd:
47 ; CHECK-NEXT: uqdecd z0.d, vl2, mul #3
49 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqdecd.nxv2i64(<vscale x 2 x i64> %a,
51 ret <vscale x 2 x i64> %out
58 define <vscale x 8 x i16> @uqdecp_b16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %b) {
59 ; CHECK-LABEL: uqdecp_b16:
61 ; CHECK-NEXT: uqdecp z0.h, p0.h
63 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqdecp.nxv8i16(<vscale x 8 x i16> %a,
65 ret <vscale x 8 x i16> %out
68 define <vscale x 4 x i32> @uqdecp_b32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %b) {
69 ; CHECK-LABEL: uqdecp_b32:
71 ; CHECK-NEXT: uqdecp z0.s, p0.s
73 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqdecp.nxv4i32(<vscale x 4 x i32> %a,
75 ret <vscale x 4 x i32> %out
78 define <vscale x 2 x i64> @uqdecp_b64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %b) {
79 ; CHECK-LABEL: uqdecp_b64:
81 ; CHECK-NEXT: uqdecp z0.d, p0.d
83 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqdecp.nxv2i64(<vscale x 2 x i64> %a,
85 ret <vscale x 2 x i64> %out
92 define i32 @uqdecb_n32(i32 %a) {
93 ; CHECK-LABEL: uqdecb_n32:
95 ; CHECK-NEXT: uqdecb w0, vl3, mul #4
97 %out = call i32 @llvm.aarch64.sve.uqdecb.n32(i32 %a, i32 3, i32 4)
101 define i64 @uqdecb_n64(i64 %a) {
102 ; CHECK-LABEL: uqdecb_n64:
104 ; CHECK-NEXT: uqdecb x0, vl4, mul #5
106 %out = call i64 @llvm.aarch64.sve.uqdecb.n64(i64 %a, i32 4, i32 5)
114 define i32 @uqdech_n32(i32 %a) {
115 ; CHECK-LABEL: uqdech_n32:
117 ; CHECK-NEXT: uqdech w0, vl5, mul #6
119 %out = call i32 @llvm.aarch64.sve.uqdech.n32(i32 %a, i32 5, i32 6)
123 define i64 @uqdech_n64(i64 %a) {
124 ; CHECK-LABEL: uqdech_n64:
126 ; CHECK-NEXT: uqdech x0, vl6, mul #7
128 %out = call i64 @llvm.aarch64.sve.uqdech.n64(i64 %a, i32 6, i32 7)
136 define i32 @uqdecw_n32(i32 %a) {
137 ; CHECK-LABEL: uqdecw_n32:
139 ; CHECK-NEXT: uqdecw w0, vl7, mul #8
141 %out = call i32 @llvm.aarch64.sve.uqdecw.n32(i32 %a, i32 7, i32 8)
145 define i64 @uqdecw_n64(i64 %a) {
146 ; CHECK-LABEL: uqdecw_n64:
148 ; CHECK-NEXT: uqdecw x0, vl8, mul #9
150 %out = call i64 @llvm.aarch64.sve.uqdecw.n64(i64 %a, i32 8, i32 9)
158 define i32 @uqdecd_n32(i32 %a) {
159 ; CHECK-LABEL: uqdecd_n32:
161 ; CHECK-NEXT: uqdecd w0, vl16, mul #10
163 %out = call i32 @llvm.aarch64.sve.uqdecd.n32(i32 %a, i32 9, i32 10)
167 define i64 @uqdecd_n64(i64 %a) {
168 ; CHECK-LABEL: uqdecd_n64:
170 ; CHECK-NEXT: uqdecd x0, vl32, mul #11
172 %out = call i64 @llvm.aarch64.sve.uqdecd.n64(i64 %a, i32 10, i32 11)
180 define i32 @uqdecp_n32_b8(i32 %a, <vscale x 16 x i1> %b) {
181 ; CHECK-LABEL: uqdecp_n32_b8:
183 ; CHECK-NEXT: uqdecp w0, p0.b
185 %out = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv16i1(i32 %a, <vscale x 16 x i1> %b)
189 define i32 @uqdecp_n32_b16(i32 %a, <vscale x 8 x i1> %b) {
190 ; CHECK-LABEL: uqdecp_n32_b16:
192 ; CHECK-NEXT: uqdecp w0, p0.h
194 %out = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv8i1(i32 %a, <vscale x 8 x i1> %b)
198 define i32 @uqdecp_n32_b32(i32 %a, <vscale x 4 x i1> %b) {
199 ; CHECK-LABEL: uqdecp_n32_b32:
201 ; CHECK-NEXT: uqdecp w0, p0.s
203 %out = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv4i1(i32 %a, <vscale x 4 x i1> %b)
207 define i32 @uqdecp_n32_b64(i32 %a, <vscale x 2 x i1> %b) {
208 ; CHECK-LABEL: uqdecp_n32_b64:
210 ; CHECK-NEXT: uqdecp w0, p0.d
212 %out = call i32 @llvm.aarch64.sve.uqdecp.n32.nxv2i1(i32 %a, <vscale x 2 x i1> %b)
216 define i64 @uqdecp_n64_b8(i64 %a, <vscale x 16 x i1> %b) {
217 ; CHECK-LABEL: uqdecp_n64_b8:
219 ; CHECK-NEXT: uqdecp x0, p0.b
221 %out = call i64 @llvm.aarch64.sve.uqdecp.n64.nxv16i1(i64 %a, <vscale x 16 x i1> %b)
225 define i64 @uqdecp_n64_b16(i64 %a, <vscale x 8 x i1> %b) {
226 ; CHECK-LABEL: uqdecp_n64_b16:
228 ; CHECK-NEXT: uqdecp x0, p0.h
230 %out = call i64 @llvm.aarch64.sve.uqdecp.n64.nxv8i1(i64 %a, <vscale x 8 x i1> %b)
234 define i64 @uqdecp_n64_b32(i64 %a, <vscale x 4 x i1> %b) {
235 ; CHECK-LABEL: uqdecp_n64_b32:
237 ; CHECK-NEXT: uqdecp x0, p0.s
239 %out = call i64 @llvm.aarch64.sve.uqdecp.n64.nxv4i1(i64 %a, <vscale x 4 x i1> %b)
243 define i64 @uqdecp_n64_b64(i64 %a, <vscale x 2 x i1> %b) {
244 ; CHECK-LABEL: uqdecp_n64_b64:
246 ; CHECK-NEXT: uqdecp x0, p0.d
248 %out = call i64 @llvm.aarch64.sve.uqdecp.n64.nxv2i1(i64 %a, <vscale x 2 x i1> %b)
252 ; uqdec{h|w|d}(vector, pattern, multiplier)
253 declare <vscale x 8 x i16> @llvm.aarch64.sve.uqdech.nxv8i16(<vscale x 8 x i16>, i32, i32)
254 declare <vscale x 4 x i32> @llvm.aarch64.sve.uqdecw.nxv4i32(<vscale x 4 x i32>, i32, i32)
255 declare <vscale x 2 x i64> @llvm.aarch64.sve.uqdecd.nxv2i64(<vscale x 2 x i64>, i32, i32)
257 ; uqdec{b|h|w|d}(scalar, pattern, multiplier)
258 declare i32 @llvm.aarch64.sve.uqdecb.n32(i32, i32, i32)
259 declare i64 @llvm.aarch64.sve.uqdecb.n64(i64, i32, i32)
260 declare i32 @llvm.aarch64.sve.uqdech.n32(i32, i32, i32)
261 declare i64 @llvm.aarch64.sve.uqdech.n64(i64, i32, i32)
262 declare i32 @llvm.aarch64.sve.uqdecw.n32(i32, i32, i32)
263 declare i64 @llvm.aarch64.sve.uqdecw.n64(i64, i32, i32)
264 declare i32 @llvm.aarch64.sve.uqdecd.n32(i32, i32, i32)
265 declare i64 @llvm.aarch64.sve.uqdecd.n64(i64, i32, i32)
267 ; uqdecp(scalar, predicate)
268 declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv16i1(i32, <vscale x 16 x i1>)
269 declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv8i1(i32, <vscale x 8 x i1>)
270 declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv4i1(i32, <vscale x 4 x i1>)
271 declare i32 @llvm.aarch64.sve.uqdecp.n32.nxv2i1(i32, <vscale x 2 x i1>)
273 declare i64 @llvm.aarch64.sve.uqdecp.n64.nxv16i1(i64, <vscale x 16 x i1>)
274 declare i64 @llvm.aarch64.sve.uqdecp.n64.nxv8i1(i64, <vscale x 8 x i1>)
275 declare i64 @llvm.aarch64.sve.uqdecp.n64.nxv4i1(i64, <vscale x 4 x i1>)
276 declare i64 @llvm.aarch64.sve.uqdecp.n64.nxv2i1(i64, <vscale x 2 x i1>)
278 ; uqdecp(vector, predicate)
279 declare <vscale x 8 x i16> @llvm.aarch64.sve.uqdecp.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>)
280 declare <vscale x 4 x i32> @llvm.aarch64.sve.uqdecp.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>)
281 declare <vscale x 2 x i64> @llvm.aarch64.sve.uqdecp.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>)