1 ; RUN: llc -mtriple aarch64 -mattr=+sve -asm-verbose=0 < %s | FileCheck %s
2 ; RUN: opt -mtriple=aarch64 -codegenprepare -S < %s | llc -mtriple=aarch64 -mattr=+sve -asm-verbose=0 | FileCheck %s
8 ; CHECK-LABEL: rdvl_i8:
11 define i8 @rdvl_i8() nounwind {
12 %vscale = call i8 @llvm.vscale.i8()
13 %1 = mul nsw i8 %vscale, 16
17 ; CHECK-LABEL: rdvl_i16:
20 define i16 @rdvl_i16() nounwind {
21 %vscale = call i16 @llvm.vscale.i16()
22 %1 = mul nsw i16 %vscale, 16
26 ; CHECK-LABEL: rdvl_i32:
29 define i32 @rdvl_i32() nounwind {
30 %vscale = call i32 @llvm.vscale.i32()
31 %1 = mul nsw i32 %vscale, 16
35 ; CHECK-LABEL: rdvl_i64:
38 define i64 @rdvl_i64() nounwind {
39 %vscale = call i64 @llvm.vscale.i64()
40 %1 = mul nsw i64 %vscale, 16
44 ; CHECK-LABEL: rdvl_const:
47 define i32 @rdvl_const() nounwind {
48 %vscale.ptr = getelementptr <vscale x 1 x i8>, ptr null, i64 1
49 %vscale.int = ptrtoint ptr %vscale.ptr to i32
50 %vscale.scaled = mul nsw i32 %vscale.int, 16
51 ret i32 %vscale.scaled
54 define i32 @vscale_1() nounwind {
55 ; CHECK-LABEL: vscale_1:
56 ; CHECK: rdvl [[TMP:x[0-9]+]], #1
57 ; CHECK-NEXT: lsr x0, [[TMP]], #4
59 %vscale = call i32 @llvm.vscale.i32()
63 define i32 @vscale_neg1() nounwind {
64 ; CHECK-LABEL: vscale_neg1:
65 ; CHECK: rdvl [[TMP:x[0-9]+]], #-1
66 ; CHECK-NEXT: asr x0, [[TMP]], #4
68 %vscale = call i32 @llvm.vscale.i32()
69 %neg = mul nsw i32 -1, %vscale
73 ; CHECK-LABEL: rdvl_3:
74 ; CHECK: rdvl [[VL_B:x[0-9]+]], #1
75 ; CHECK-NEXT: mov w[[MUL:[0-9]+]], #3
76 ; CHECK-NEXT: lsr [[VL_Q:x[0-9]+]], [[VL_B]], #4
77 ; CHECK-NEXT: mul x0, [[VL_Q]], x[[MUL]]
79 define i32 @rdvl_3() nounwind {
80 %vscale = call i32 @llvm.vscale.i32()
81 %1 = mul nsw i32 %vscale, 3
86 ; CHECK-LABEL: rdvl_min:
87 ; CHECK: rdvl x0, #-32
89 define i32 @rdvl_min() nounwind {
90 %vscale = call i32 @llvm.vscale.i32()
91 %1 = mul nsw i32 %vscale, -512
95 ; CHECK-LABEL: rdvl_max:
98 define i32 @rdvl_max() nounwind {
99 %vscale = call i32 @llvm.vscale.i32()
100 %1 = mul nsw i32 %vscale, 496
104 define i1 @rdvl_i1() {
105 ; CHECK-LABEL: rdvl_i1:
106 ; CHECK: rdvl x8, #-1
107 ; CHECK-NEXT: asr x8, x8, #4
108 ; CHECK-NEXT: and w0, w8, #0x1
110 %a = tail call i64 @llvm.vscale.i64()
111 %b = trunc i64 %a to i1
120 ; CHECK: cnth x0{{$}}
122 define i32 @cnth() nounwind {
123 %vscale = call i32 @llvm.vscale.i32()
124 %1 = shl nsw i32 %vscale, 3
128 ; CHECK-LABEL: cnth_max:
129 ; CHECK: cnth x0, all, mul #15
131 define i32 @cnth_max() nounwind {
132 %vscale = call i32 @llvm.vscale.i32()
133 %1 = mul nsw i32 %vscale, 120
137 ; CHECK-LABEL: cnth_neg:
138 ; CHECK: cnth [[CNT:x[0-9]+]]
139 ; CHECK: neg x0, [[CNT]]
141 define i32 @cnth_neg() nounwind {
142 %vscale = call i32 @llvm.vscale.i32()
143 %1 = mul nsw i32 %vscale, -8
152 ; CHECK: cntw x0{{$}}
154 define i32 @cntw() nounwind {
155 %vscale = call i32 @llvm.vscale.i32()
156 %1 = shl nsw i32 %vscale, 2
160 ; CHECK-LABEL: cntw_max:
161 ; CHECK: cntw x0, all, mul #15
163 define i32 @cntw_max() nounwind {
164 %vscale = call i32 @llvm.vscale.i32()
165 %1 = mul nsw i32 %vscale, 60
169 ; CHECK-LABEL: cntw_neg:
170 ; CHECK: cntw [[CNT:x[0-9]+]]
171 ; CHECK: neg x0, [[CNT]]
173 define i32 @cntw_neg() nounwind {
174 %vscale = call i32 @llvm.vscale.i32()
175 %1 = mul nsw i32 %vscale, -4
184 ; CHECK: cntd x0{{$}}
186 define i32 @cntd() nounwind {
187 %vscale = call i32 @llvm.vscale.i32()
188 %1 = shl nsw i32 %vscale, 1
192 ; CHECK-LABEL: cntd_max:
193 ; CHECK: cntd x0, all, mul #15
195 define i32 @cntd_max() nounwind {
196 %vscale = call i32 @llvm.vscale.i32()
197 %1 = mul nsw i32 %vscale, 30
201 ; CHECK-LABEL: cntd_neg:
202 ; CHECK: cntd [[CNT:x[0-9]+]]
203 ; CHECK: neg x0, [[CNT]]
205 define i32 @cntd_neg() nounwind {
206 %vscale = call i32 @llvm.vscale.i32()
207 %1 = mul nsw i32 %vscale, -2
211 declare i8 @llvm.vscale.i8()
212 declare i16 @llvm.vscale.i16()
213 declare i32 @llvm.vscale.i32()
214 declare i64 @llvm.vscale.i64()