1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -verify-machineinstrs < %s | FileCheck %s
4 define <vscale x 16 x i1> @psel_b(<vscale x 16 x i1> %p1, <vscale x 16 x i1> %p2, i32 %idx) {
7 ; CHECK-NEXT: mov w12, w0
8 ; CHECK-NEXT: psel p0, p0, p1.b[w12, 0]
10 %res = call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv16i1(<vscale x 16 x i1> %p1, <vscale x 16 x i1> %p2, i32 %idx)
11 ret <vscale x 16 x i1> %res
14 define <vscale x 16 x i1> @psel_b_imm(<vscale x 16 x i1> %p1, <vscale x 16 x i1> %p2, i32 %idx) {
15 ; CHECK-LABEL: psel_b_imm:
17 ; CHECK-NEXT: mov w12, w0
18 ; CHECK-NEXT: psel p0, p0, p1.b[w12, 15]
20 %add = add i32 %idx, 15
21 %res = call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv16i1(<vscale x 16 x i1> %p1, <vscale x 16 x i1> %p2, i32 %add)
22 ret <vscale x 16 x i1> %res
25 define <vscale x 16 x i1> @psel_h(<vscale x 16 x i1> %p1, <vscale x 8 x i1> %p2, i32 %idx) {
26 ; CHECK-LABEL: psel_h:
28 ; CHECK-NEXT: mov w12, w0
29 ; CHECK-NEXT: psel p0, p0, p1.h[w12, 0]
31 %res = call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv8i1(<vscale x 16 x i1> %p1, <vscale x 8 x i1> %p2, i32 %idx)
32 ret <vscale x 16 x i1> %res
35 define <vscale x 16 x i1> @psel_h_imm(<vscale x 16 x i1> %p1, <vscale x 8 x i1> %p2, i32 %idx) {
36 ; CHECK-LABEL: psel_h_imm:
38 ; CHECK-NEXT: mov w12, w0
39 ; CHECK-NEXT: psel p0, p0, p1.h[w12, 7]
41 %add = add i32 %idx, 7
42 %res = call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv8i1(<vscale x 16 x i1> %p1, <vscale x 8 x i1> %p2, i32 %add)
43 ret <vscale x 16 x i1> %res
46 define <vscale x 16 x i1> @psel_s(<vscale x 16 x i1> %p1, <vscale x 4 x i1> %p2, i32 %idx) {
47 ; CHECK-LABEL: psel_s:
49 ; CHECK-NEXT: mov w12, w0
50 ; CHECK-NEXT: psel p0, p0, p1.s[w12, 0]
52 %res = call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv4i1(<vscale x 16 x i1> %p1, <vscale x 4 x i1> %p2, i32 %idx)
53 ret <vscale x 16 x i1> %res
56 define <vscale x 16 x i1> @psel_s_imm(<vscale x 16 x i1> %p1, <vscale x 4 x i1> %p2, i32 %idx) {
57 ; CHECK-LABEL: psel_s_imm:
59 ; CHECK-NEXT: mov w12, w0
60 ; CHECK-NEXT: psel p0, p0, p1.s[w12, 3]
62 %add = add i32 %idx, 3
63 %res = call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv4i1(<vscale x 16 x i1> %p1, <vscale x 4 x i1> %p2, i32 %add)
64 ret <vscale x 16 x i1> %res
67 define <vscale x 16 x i1> @psel_d(<vscale x 16 x i1> %p1, <vscale x 2 x i1> %p2, i32 %idx) {
68 ; CHECK-LABEL: psel_d:
70 ; CHECK-NEXT: mov w12, w0
71 ; CHECK-NEXT: psel p0, p0, p1.d[w12, 0]
73 %res = call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv2i1(<vscale x 16 x i1> %p1, <vscale x 2 x i1> %p2, i32 %idx)
74 ret <vscale x 16 x i1> %res
77 define <vscale x 16 x i1> @psel_d_imm(<vscale x 16 x i1> %p1, <vscale x 2 x i1> %p2, i32 %idx) {
78 ; CHECK-LABEL: psel_d_imm:
80 ; CHECK-NEXT: mov w12, w0
81 ; CHECK-NEXT: psel p0, p0, p1.d[w12, 1]
83 %add = add i32 %idx, 1
84 %res = call <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv2i1(<vscale x 16 x i1> %p1, <vscale x 2 x i1> %p2, i32 %add)
85 ret <vscale x 16 x i1> %res
88 declare <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, i32)
89 declare <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv8i1(<vscale x 16 x i1>, <vscale x 8 x i1>, i32)
90 declare <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv4i1(<vscale x 16 x i1>, <vscale x 4 x i1>, i32)
91 declare <vscale x 16 x i1> @llvm.aarch64.sve.psel.nxv2i1(<vscale x 16 x i1>, <vscale x 2 x i1>, i32)