[InstCombine] Set disjoint flag when turning Add into Or. (#72702)
commit03d4a9d94da30590ebfc444cf13a8763f47b7bb9
authorCraig Topper <craig.topper@sifive.com>
Mon, 27 Nov 2023 20:54:11 +0000 (27 12:54 -0800)
committerGitHub <noreply@github.com>
Mon, 27 Nov 2023 20:54:11 +0000 (27 12:54 -0800)
treea26fd0978b8a4a9f7756b7bfabeb9b49264d84cf
parente666e27485d69ca60747c198418e64922c72238f
[InstCombine] Set disjoint flag when turning Add into Or. (#72702)

The disjoint flag was recently added to IR in #72583
45 files changed:
clang/test/CodeGen/aarch64-ls64-inline-asm.c
clang/test/CodeGen/ms-intrinsics.c
llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
llvm/test/Analysis/ValueTracking/assume.ll
llvm/test/Transforms/InstCombine/add.ll
llvm/test/Transforms/InstCombine/add2.ll
llvm/test/Transforms/InstCombine/apint-add.ll
llvm/test/Transforms/InstCombine/apint-shift.ll
llvm/test/Transforms/InstCombine/bitreverse-known-bits.ll
llvm/test/Transforms/InstCombine/masked-merge-add.ll
llvm/test/Transforms/InstCombine/minmax-intrinsics.ll
llvm/test/Transforms/InstCombine/or.ll
llvm/test/Transforms/InstCombine/pr72433.ll
llvm/test/Transforms/InstCombine/ptrtoint-nullgep.ll
llvm/test/Transforms/InstCombine/rem.ll
llvm/test/Transforms/LoopUnroll/AArch64/runtime-unroll-generic.ll
llvm/test/Transforms/LoopUnroll/WebAssembly/basic-unrolling.ll
llvm/test/Transforms/LoopUnroll/runtime-multiexit-heuristic.ll
llvm/test/Transforms/LoopUnroll/runtime-unroll-remainder.ll
llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
llvm/test/Transforms/LoopVectorize/SystemZ/addressing.ll
llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll
llvm/test/Transforms/LoopVectorize/X86/parallel-loops.ll
llvm/test/Transforms/LoopVectorize/X86/small-size.ll
llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-accesses-masked-group.ll
llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-store-accesses-with-gaps.ll
llvm/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll
llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
llvm/test/Transforms/LoopVectorize/float-induction.ll
llvm/test/Transforms/LoopVectorize/forked-pointers.ll
llvm/test/Transforms/LoopVectorize/induction.ll
llvm/test/Transforms/LoopVectorize/interleaved-accesses-pred-stores.ll
llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
llvm/test/Transforms/LoopVectorize/loop-scalars.ll
llvm/test/Transforms/LoopVectorize/reduction-inloop-cond.ll
llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
llvm/test/Transforms/LoopVectorize/reduction-predselect.ll
llvm/test/Transforms/LoopVectorize/reduction.ll
llvm/test/Transforms/LoopVectorize/scalar_after_vectorization.ll
llvm/test/Transforms/LoopVectorize/uniform-args-call-variants.ll
llvm/test/Transforms/PhaseOrdering/AArch64/peel-multiple-unreachable-exits-for-vectorization.ll
llvm/test/Transforms/PhaseOrdering/X86/SROA-after-final-loop-unrolling-2.ll
llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr.ll