[SVE][CodeGen] Add patterns for ADD/SUB + element count
commit1a2e90199f83e7e3a7267b8fa9715d87ed5b2f88
authorKerry McLaughlin <kerry.mclaughlin@arm.com>
Wed, 13 Oct 2021 09:24:43 +0000 (13 10:24 +0100)
committerKerry McLaughlin <kerry.mclaughlin@arm.com>
Wed, 13 Oct 2021 10:36:15 +0000 (13 11:36 +0100)
tree3578b6977ab7c38707b0e5f219f9d4538de3cb67
parent93fd30a1632743d377d8c6525401074ef9eca562
[SVE][CodeGen] Add patterns for ADD/SUB + element count

This patch adds patterns to match the following with INC/DEC:
 - @llvm.aarch64.sve.cnt[b|h|w|d] intrinsics + ADD/SUB
 - vscale + ADD/SUB

For some implementations of SVE, INC/DEC VL is not as cheap as ADD/SUB and
so this behaviour is guarded by the "use-scalar-inc-vl" feature flag, which for SVE
is off by default. There are no known issues with SVE2, so this feature is
enabled by default when targeting SVE2.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D111441
16 files changed:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/Target/AArch64/AArch64.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/AArch64Subtarget.h
llvm/lib/Target/AArch64/SVEInstrFormats.td
llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
llvm/test/CodeGen/AArch64/sve-gep.ll
llvm/test/CodeGen/AArch64/sve-insert-element.ll
llvm/test/CodeGen/AArch64/sve-insert-vector.ll
llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems.ll
llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
llvm/test/CodeGen/AArch64/sve-split-insert-elt.ll
llvm/test/CodeGen/AArch64/sve-stepvector.ll
llvm/test/CodeGen/AArch64/sve-vl-arith.ll [new file with mode: 0644]