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[AMDGPU] Add True16 register classes.
commit469b3bfad20550968ac428738eb1f8bb8ce3e96d
authorIvan Kosarev <ivan.kosarev@amd.com>
Thu, 21 Sep 2023 12:56:17 +0000 (21 13:56 +0100)
committerIvan Kosarev <ivan.kosarev@amd.com>
Fri, 22 Sep 2023 09:17:02 +0000 (22 10:17 +0100)
treeaad9aa43df82760f0aacda14991eb0cf16e9077btree | snapshot (tar.gz zip)
parentcb3a39444a38b65ac8696c3df05c48384dbed5fdcommit | diff
[AMDGPU] Add True16 register classes.

Reviewed By: rampitec, Joe_Nash

Differential Revision: https://reviews.llvm.org/D156099
12 files changed:
llvm/lib/Target/AMDGPU/SIRegisterInfo.td diff | blob | blame | history
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll diff | blob | blame | history
llvm/test/CodeGen/AMDGPU/branch-relax-indirect-branch.mir diff | blob | blame | history
llvm/test/CodeGen/AMDGPU/branch-relax-no-terminators.mir diff | blob | blame | history
llvm/test/CodeGen/AMDGPU/coalescer-early-clobber-subreg.mir diff | blob | blame | history
llvm/test/CodeGen/AMDGPU/inline-asm.i128.ll diff | blob | blame | history
llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll diff | blob | blame | history
llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir diff | blob | blame | history
llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir diff | blob | blame | history
llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll diff | blob | blame | history
llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir diff | blob | blame | history
llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected diff | blob | blame | history
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