[RISCV] Remove XSfcie extension.
commit6dc5ba4cca72a5c25597722b8a8c7dcff5fb67be
authorCraig Topper <craig.topper@sifive.com>
Thu, 28 Dec 2023 20:21:22 +0000 (28 12:21 -0800)
committerCraig Topper <craig.topper@sifive.com>
Thu, 28 Dec 2023 21:54:15 +0000 (28 13:54 -0800)
treedcd67a3e403c1e39295a145af4f1098984cf3d60
parent76facde32c2151c3ba6774ff7416281c680bf8bf
[RISCV] Remove XSfcie extension.

This reverts 0d3eee33f262402562a1ff28106dbb2f59031bdb and
4c37d30e22ae655394c8b3a7e292c06d393b9b44.

XSfcie is not an official SiFive extension name. It stands for
SiFive Custom Instruction Extension, which is mentioned in the S76
manual, but then elsewhere in the manual says it is not supported
for S76.

LLVM had various instructions and CSRs listed as part of this
extension, but as far as SiFive is concerned, none of them are part
of it. There are no documented extension names for these instructions
and CSRs either externally or internally.

If these are important to LLVM users, I can facilitate creating
extension names for them and have them documented. For now I'm
removing everything.

Unfortunately, these instructions and CSRs are in LLVM 17 so this
is an incompatible change.
19 files changed:
clang/test/Driver/riscv-cpus.c
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/docs/ReleaseNotes.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
llvm/lib/Target/RISCV/RISCVProcessors.td
llvm/lib/Target/RISCV/RISCVSystemOperands.td
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/machine-csr-names.s
llvm/test/MC/RISCV/xsfcie-invalid.s [deleted file]
llvm/test/MC/RISCV/xsfcie-valid.s [deleted file]
llvm/unittests/Support/RISCVISAInfoTest.cpp