| commit | 83cad6805d144d941bdda99d71a6df2cf113a76d | |
| author | Srinivasa Ravi <srinivasar@nvidia.com> | |
| Sat, 1 Feb 2025 06:02:44 +0000 (1 11:32 +0530) | ||
| committer | GitHub <noreply@github.com> | |
| Sat, 1 Feb 2025 06:02:44 +0000 (1 11:32 +0530) | ||
| tree | c62afbc627797cf961d4002207b91738965271a2 | treesnapshot (tar.gz zip) |
| parent | 028b69009a221e16076be77752514525b321d012 | commitdiff |
[MLIR][NVVM] Update Float to TF32 conversion Op (#125048)
This change updates the Float to TF32 conversion MLIR Op to include
lowering to the new intrinsics introduced in sm_100 through ptx8.6:
- `nvvm_f2tf32_rn_satfinite`
- `nvvm_f2tf32_rn_relu_satfinite`
- `nvvm_f2tf32_rz_satfinite`
- `nvvm_f2tf32_rz_relu_satfinite`
PTX Spec Reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt
This change updates the Float to TF32 conversion MLIR Op to include
lowering to the new intrinsics introduced in sm_100 through ptx8.6:
- `nvvm_f2tf32_rn_satfinite`
- `nvvm_f2tf32_rn_relu_satfinite`
- `nvvm_f2tf32_rz_satfinite`
- `nvvm_f2tf32_rz_relu_satfinite`
PTX Spec Reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt
| mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp | diffblobblamehistory | |
| mlir/test/Target/LLVMIR/nvvm/cvt_tf32.mlir | diffblobblamehistory | |
| mlir/test/Target/LLVMIR/nvvmir-invalid.mlir | diffblobblamehistory |