| commit | b3052013b43617defd777b1f3b4339540c4c07df | |
| author | Ben Shi <powerman1st@163.com> | |
| Sun, 19 Sep 2021 09:42:20 +0000 (19 09:42 +0000) | ||
| committer | Ben Shi <powerman1st@163.com> | |
| Tue, 21 Sep 2021 14:13:14 +0000 (21 14:13 +0000) | ||
| tree | 52ca4cb9f183faaaa7690b24fba4dfe27e34824c | treesnapshot (tar.gz zip) |
| parent | 32b994bca66641cdac8586f25315daf349921ebc | commitdiff |
[RISCV] Optimize (add (mul x, c0), c1)
Optimize (add (mul x, c0), c1) -> (ADDI (MUL (ADDI, c1/c0), c0), c1%c0),
if c1/c0 and c1%c0 are simm12, while c1 is not.
Optimize (add (mul x, c0), c1) -> (MUL (ADDI, c1/c0), c0),
if c1%c0 is zero, and c1/c0 is simm12 while c1 is not.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D108607
Optimize (add (mul x, c0), c1) -> (ADDI (MUL (ADDI, c1/c0), c0), c1%c0),
if c1/c0 and c1%c0 are simm12, while c1 is not.
Optimize (add (mul x, c0), c1) -> (MUL (ADDI, c1/c0), c0),
if c1%c0 is zero, and c1/c0 is simm12 while c1 is not.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D108607
| llvm/lib/Target/RISCV/RISCVISelLowering.cpp | diffblobblamehistory | |
| llvm/test/CodeGen/RISCV/addimm-mulimm.ll | diffblobblamehistory |