| commit | d043822daab9b4e7176a48c6794cb454e7398ec0 | |
| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | |
| Tue, 11 Jan 2022 22:03:58 +0000 (11 14:03 -0800) | ||
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | |
| Thu, 13 Jan 2022 00:37:08 +0000 (12 16:37 -0800) | ||
| tree | dbf9eeed4ec4083d6afc29a70baf10f871744654 | treesnapshot (tar.gz zip) |
| parent | 1e36bd8516f23e2eaf9c3c6c2005a8cf66070896 | commitdiff |
[AMDGPU] Fixed physreg asm constraint parsing
We are always failing parsing of the physreg constraint because
we do not drop trailing brace, thus getAsInteger() returns a
non-empty string and we delegate reparsing to the TargetLowering.
In addition it did not parse register tuples.
Fixed which has allowed to remove w/a in two places we call it.
Differential Revision: https://reviews.llvm.org/D117055
We are always failing parsing of the physreg constraint because
we do not drop trailing brace, thus getAsInteger() returns a
non-empty string and we delegate reparsing to the TargetLowering.
In addition it did not parse register tuples.
Fixed which has allowed to remove w/a in two places we call it.
Differential Revision: https://reviews.llvm.org/D117055
| llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp | diffblobblamehistory | |
| llvm/lib/Target/AMDGPU/SIISelLowering.cpp | diffblobblamehistory |