[DAG] SimplifyDemandedBits - don't fold sext(x) -> aext(x) if we lose an 0/-1 allsign...
commitd460c1de3b989cea919b9d60c21644f28f987950
authorSimon Pilgrim <RKSimon@users.noreply.github.com>
Mon, 8 Jan 2024 18:01:41 +0000 (8 18:01 +0000)
committerGitHub <noreply@github.com>
Mon, 8 Jan 2024 18:01:41 +0000 (8 18:01 +0000)
tree18e7fed4f9add3650ae2b4e6167e517eb9e5040c
parent5351ded68d579921a61b26a34e36046c22f668bd
[DAG] SimplifyDemandedBits - don't fold sext(x) -> aext(x) if we lose an 0/-1 allsignbits mask (#77296)

For targets that use 0/-1 boolean results, we want to keep this pattern through extensions/truncations as much as possible - so avoid simplifying to any_extend even if we don't demand the upper bits.

Noticed in triage for https://reviews.llvm.org/D152928
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/test/CodeGen/AArch64/arm64-zip.ll
llvm/test/CodeGen/AArch64/vselect-ext.ll
llvm/test/CodeGen/SystemZ/vec-perm-14.ll
llvm/test/CodeGen/X86/test-shrink-bug.ll
llvm/test/CodeGen/X86/vec_setcc.ll