lib/CodeGen/RegisterScavenging.cpp

   1 //===-- RegisterScavenging.cpp - Machine register scavenging --------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the machine register scavenger. It can provide
  11 // information, such as unused registers, at any point in a machine basic block.
  12 // It also provides a mechanism to make registers available by evicting them to
  13 // spill slots.
  14 //
  15 //===----------------------------------------------------------------------===//
  16
  17 #define DEBUG_TYPE "reg-scavenging"
  18 #include "llvm/CodeGen/RegisterScavenging.h"
  19 #include "llvm/CodeGen/MachineFrameInfo.h"
  20 #include "llvm/CodeGen/MachineFunction.h"
  21 #include "llvm/CodeGen/MachineBasicBlock.h"
  22 #include "llvm/CodeGen/MachineInstr.h"
  23 #include "llvm/CodeGen/MachineRegisterInfo.h"
  24 #include "llvm/Support/ErrorHandling.h"
  25 #include "llvm/Target/TargetRegisterInfo.h"
  26 #include "llvm/Target/TargetInstrInfo.h"
  27 #include "llvm/Target/TargetMachine.h"
  28 #include "llvm/ADT/SmallPtrSet.h"
  29 #include "llvm/ADT/SmallVector.h"
  30 #include "llvm/ADT/STLExtras.h"
  31 using namespace llvm;
  32
  33 /// RedefinesSuperRegPart - Return true if the specified register is redefining
  34 /// part of a super-register.
  35 static bool RedefinesSuperRegPart(const MachineInstr *MI, unsigned SubReg,
  36                                   const TargetRegisterInfo *TRI) {
  37   bool SeenSuperUse = false;
  38   bool SeenSuperDef = false;
  39   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
  40     const MachineOperand &MO = MI->getOperand(i);
  41     if (!MO.isReg() || MO.isUndef())
  42       continue;
  43     if (TRI->isSuperRegister(SubReg, MO.getReg())) {
  44       if (MO.isUse())
  45         SeenSuperUse = true;
  46       else if (MO.isImplicit())
  47         SeenSuperDef = true;
  48     }
  49   }
  50
  51   return SeenSuperDef && SeenSuperUse;
  52 }
  53
  54 static bool RedefinesSuperRegPart(const MachineInstr *MI,
  55                                   const MachineOperand &MO,
  56                                   const TargetRegisterInfo *TRI) {
  57   assert(MO.isReg() && MO.isDef() && "Not a register def!");
  58   return RedefinesSuperRegPart(MI, MO.getReg(), TRI);
  59 }
  60
  61 bool RegScavenger::isSuperRegUsed(unsigned Reg) const {
  62   for (const unsigned *SuperRegs = TRI->getSuperRegisters(Reg);
  63        unsigned SuperReg = *SuperRegs; ++SuperRegs)
  64     if (isUsed(SuperReg))
  65       return true;
  66   return false;
  67 }
  68
  69 /// setUsed - Set the register and its sub-registers as being used.
  70 void RegScavenger::setUsed(unsigned Reg) {
  71   RegsAvailable.reset(Reg);
  72
  73   for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
  74        unsigned SubReg = *SubRegs; ++SubRegs)
  75     RegsAvailable.reset(SubReg);
  76 }
  77
  78 /// setUnused - Set the register and its sub-registers as being unused.
  79 void RegScavenger::setUnused(unsigned Reg, const MachineInstr *MI) {
  80   RegsAvailable.set(Reg);
  81
  82   for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
  83        unsigned SubReg = *SubRegs; ++SubRegs)
  84     if (!RedefinesSuperRegPart(MI, Reg, TRI))
  85       RegsAvailable.set(SubReg);
  86 }
  87
  88 void RegScavenger::initRegState() {
  89   ScavengedReg = 0;
  90   ScavengedRC = NULL;
  91   ScavengeRestore = NULL;
  92   CurrDist = 0;
  93   DistanceMap.clear();
  94
  95   // All registers started out unused.
  96   RegsAvailable.set();
  97
  98   // Reserved registers are always used.
  99   RegsAvailable ^= ReservedRegs;
 100
 101   // Live-in registers are in use.
 102   if (MBB) {
 103     if (!MBB->livein_empty())
 104       for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
 105              E = MBB->livein_end(); I != E; ++I)
 106         setUsed(*I);
 107   }
 108 }
 109
 110 void RegScavenger::enterBasicBlock(MachineBasicBlock *mbb) {
 111   MachineFunction &MF = *mbb->getParent();
 112   const TargetMachine &TM = MF.getTarget();
 113   TII = TM.getInstrInfo();
 114   TRI = TM.getRegisterInfo();
 115   MRI = &MF.getRegInfo();
 116
 117   assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
 118          "Target changed?");
 119
 120   // Self-initialize.
 121   if (!MBB) {
 122     NumPhysRegs = TRI->getNumRegs();
 123     RegsAvailable.resize(NumPhysRegs);
 124
 125     // Create reserved registers bitvector.
 126     ReservedRegs = TRI->getReservedRegs(MF);
 127
 128     // Create callee-saved registers bitvector.
 129     CalleeSavedRegs.resize(NumPhysRegs);
 130     const unsigned *CSRegs = TRI->getCalleeSavedRegs();
 131     if (CSRegs != NULL) {
 132       // At this point we know which CSRs are used by the current function,
 133       // so allow those that are _not_ already used to be available to RS.
 134       MachineFrameInfo *FFI = MF.getFrameInfo();
 135       const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
 136
 137       for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
 138         CalleeSavedRegs.set(CSI[i].getReg());
 139       }
 140     }
 141   }
 142
 143   //  RS used within emit{Pro,Epi}logue()
 144   if (mbb != MBB) {
 145     MBB = mbb;
 146     initRegState();
 147   }
 148
 149   Tracking = false;
 150 }
 151
 152 void RegScavenger::restoreScavengedReg() {
 153   TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
 154                             ScavengingFrameIndex, ScavengedRC);
 155   MachineBasicBlock::iterator II = prior(MBBI);
 156   TRI->eliminateFrameIndex(II, 0, this);
 157   setUsed(ScavengedReg);
 158   ScavengedReg = 0;
 159   ScavengedRC = NULL;
 160 }
 161
 162 #ifndef NDEBUG
 163 /// isLiveInButUnusedBefore - Return true if register is livein the MBB not
 164 /// not used before it reaches the MI that defines register.
 165 static bool isLiveInButUnusedBefore(unsigned Reg, MachineInstr *MI,
 166                                     MachineBasicBlock *MBB,
 167                                     const TargetRegisterInfo *TRI,
 168                                     MachineRegisterInfo* MRI) {
 169   // First check if register is livein.
 170   bool isLiveIn = false;
 171   for (MachineBasicBlock::const_livein_iterator I = MBB->livein_begin(),
 172          E = MBB->livein_end(); I != E; ++I)
 173     if (Reg == *I || TRI->isSuperRegister(Reg, *I)) {
 174       isLiveIn = true;
 175       break;
 176     }
 177   if (!isLiveIn)
 178     return false;
 179
 180   // Is there any use of it before the specified MI?
 181   SmallPtrSet<MachineInstr*, 4> UsesInMBB;
 182   for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
 183          UE = MRI->use_end(); UI != UE; ++UI) {
 184     MachineOperand &UseMO = UI.getOperand();
 185     if (UseMO.isReg() && UseMO.isUndef())
 186       continue;
 187     MachineInstr *UseMI = &*UI;
 188     if (UseMI->getParent() == MBB)
 189       UsesInMBB.insert(UseMI);
 190   }
 191   if (UsesInMBB.empty())
 192     return true;
 193
 194   for (MachineBasicBlock::iterator I = MBB->begin(), E = MI; I != E; ++I)
 195     if (UsesInMBB.count(&*I))
 196       return false;
 197   return true;
 198 }
 199 #endif
 200
 201 void RegScavenger::forward() {
 202   // Move ptr forward.
 203   if (!Tracking) {
 204     MBBI = MBB->begin();
 205     Tracking = true;
 206   } else {
 207     assert(MBBI != MBB->end() && "Already at the end of the basic block!");
 208     MBBI = next(MBBI);
 209   }
 210
 211   MachineInstr *MI = MBBI;
 212   DistanceMap.insert(std::make_pair(MI, CurrDist++));
 213
 214   if (MI == ScavengeRestore) {
 215     ScavengedReg = 0;
 216     ScavengedRC = NULL;
 217     ScavengeRestore = NULL;
 218   }
 219
 220 #if 0
 221   if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
 222     return;
 223 #endif
 224
 225   // Separate register operands into 3 classes: uses, defs, earlyclobbers.
 226   SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs;
 227   SmallVector<std::pair<const MachineOperand*,unsigned>, 4> DefMOs;
 228   SmallVector<std::pair<const MachineOperand*,unsigned>, 4> EarlyClobberMOs;
 229   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
 230     const MachineOperand &MO = MI->getOperand(i);
 231     if (!MO.isReg() || MO.getReg() == 0 || MO.isUndef())
 232       continue;
 233     if (MO.isUse())
 234       UseMOs.push_back(std::make_pair(&MO,i));
 235     else if (MO.isEarlyClobber())
 236       EarlyClobberMOs.push_back(std::make_pair(&MO,i));
 237     else if (MO.isDef())
 238       DefMOs.push_back(std::make_pair(&MO,i));
 239   }
 240
 241   // Process uses first.
 242   BitVector KillRegs(NumPhysRegs);
 243   for (unsigned i = 0, e = UseMOs.size(); i != e; ++i) {
 244     const MachineOperand MO = *UseMOs[i].first;
 245     unsigned Idx = UseMOs[i].second;
 246     unsigned Reg = MO.getReg();
 247
 248     // Allow free CSRs to be processed as uses.
 249     assert((isUsed(Reg) || !CalleeSavedRegs[Reg]) &&
 250            "Using an undefined register!");
 251
 252     // Two-address operands implicitly kill.
 253     if ((MO.isKill() || MI->isRegTiedToDefOperand(Idx)) && !isReserved(Reg)) {
 254       KillRegs.set(Reg);
 255
 256       // Mark sub-registers as used.
 257       for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
 258            unsigned SubReg = *SubRegs; ++SubRegs)
 259         KillRegs.set(SubReg);
 260     }
 261   }
 262
 263   // Change states of all registers after all the uses are processed to guard
 264   // against multiple uses.
 265   setUnused(KillRegs);
 266
 267   // Process early clobber defs then process defs. We can have a early clobber
 268   // that is dead, it should not conflict with a def that happens one "slot"
 269   // (see InstrSlots in LiveIntervalAnalysis.h) later.
 270   unsigned NumECs = EarlyClobberMOs.size();
 271   unsigned NumDefs = DefMOs.size();
 272
 273   for (unsigned i = 0, e = NumECs + NumDefs; i != e; ++i) {
 274     const MachineOperand &MO = (i < NumECs)
 275       ? *EarlyClobberMOs[i].first : *DefMOs[i-NumECs].first;
 276     unsigned Reg = MO.getReg();
 277     if (MO.isUndef())
 278       continue;
 279
 280     // If it's dead upon def, then it is now free.
 281     if (MO.isDead()) {
 282       setUnused(Reg, MI);
 283       continue;
 284     }
 285
 286     // Skip if this is merely redefining part of a super-register.
 287     if (RedefinesSuperRegPart(MI, MO, TRI))
 288       continue;
 289
 290     assert((isReserved(Reg) || isUnused(Reg) || isSuperRegUsed(Reg) ||
 291             isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &&
 292            "Re-defining a live register!");
 293     setUsed(Reg);
 294   }
 295 }
 296
 297 void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
 298   if (includeReserved)
 299     used = ~RegsAvailable;
 300   else
 301     used = ~RegsAvailable & ~ReservedRegs;
 302 }
 303
 304 /// CreateRegClassMask - Set the bits that represent the registers in the
 305 /// TargetRegisterClass.
 306 static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {
 307   for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E;
 308        ++I)
 309     Mask.set(*I);
 310 }
 311
 312 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
 313                                      const BitVector &Candidates) const {
 314   // Mask off the registers which are not in the TargetRegisterClass.
 315   BitVector RegsAvailableCopy(NumPhysRegs, false);
 316   CreateRegClassMask(RegClass, RegsAvailableCopy);
 317   RegsAvailableCopy &= RegsAvailable;
 318
 319   // Restrict the search to candidates.
 320   RegsAvailableCopy &= Candidates;
 321
 322   // Returns the first unused (bit is set) register, or 0 is none is found.
 323   int Reg = RegsAvailableCopy.find_first();
 324   return (Reg == -1) ? 0 : Reg;
 325 }
 326
 327 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RegClass,
 328                                      bool ExCalleeSaved) const {
 329   // Mask off the registers which are not in the TargetRegisterClass.
 330   BitVector RegsAvailableCopy(NumPhysRegs, false);
 331   CreateRegClassMask(RegClass, RegsAvailableCopy);
 332   RegsAvailableCopy &= RegsAvailable;
 333
 334   // If looking for a non-callee-saved register, mask off all the callee-saved
 335   // registers.
 336   if (ExCalleeSaved)
 337     RegsAvailableCopy &= ~CalleeSavedRegs;
 338
 339   // Returns the first unused (bit is set) register, or 0 is none is found.
 340   int Reg = RegsAvailableCopy.find_first();
 341   return (Reg == -1) ? 0 : Reg;
 342 }
 343
 344 /// findFirstUse - Calculate the distance to the first use of the
 345 /// specified register.
 346 MachineInstr*
 347 RegScavenger::findFirstUse(MachineBasicBlock *MBB,
 348                            MachineBasicBlock::iterator I, unsigned Reg,
 349                            unsigned &Dist) {
 350   MachineInstr *UseMI = 0;
 351   Dist = ~0U;
 352   for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(Reg),
 353          RE = MRI->reg_end(); RI != RE; ++RI) {
 354     MachineInstr *UDMI = &*RI;
 355     if (UDMI->getParent() != MBB)
 356       continue;
 357     DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UDMI);
 358     if (DI == DistanceMap.end()) {
 359       // If it's not in map, it's below current MI, let's initialize the
 360       // map.
 361       I = next(I);
 362       unsigned Dist = CurrDist + 1;
 363       while (I != MBB->end()) {
 364         DistanceMap.insert(std::make_pair(I, Dist++));
 365         I = next(I);
 366       }
 367     }
 368     DI = DistanceMap.find(UDMI);
 369     if (DI->second > CurrDist && DI->second < Dist) {
 370       Dist = DI->second;
 371       UseMI = UDMI;
 372     }
 373   }
 374   return UseMI;
 375 }
 376
 377 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
 378                                         MachineBasicBlock::iterator I,
 379                                         int SPAdj) {
 380   assert(ScavengingFrameIndex >= 0 &&
 381          "Cannot scavenge a register without an emergency spill slot!");
 382
 383   // Mask off the registers which are not in the TargetRegisterClass.
 384   BitVector Candidates(NumPhysRegs, false);
 385   CreateRegClassMask(RC, Candidates);
 386   // Do not include reserved registers.
 387   Candidates ^= ReservedRegs & Candidates;
 388
 389   // Exclude all the registers being used by the instruction.
 390   for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
 391     MachineOperand &MO = I->getOperand(i);
 392     if (MO.isReg())
 393       Candidates.reset(MO.getReg());
 394   }
 395
 396   // Find the register whose use is furthest away.
 397   unsigned SReg = 0;
 398   unsigned MaxDist = 0;
 399   MachineInstr *MaxUseMI = 0;
 400   int Reg = Candidates.find_first();
 401   while (Reg != -1) {
 402     unsigned Dist;
 403     MachineInstr *UseMI = findFirstUse(MBB, I, Reg, Dist);
 404     for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
 405       unsigned AsDist;
 406       MachineInstr *AsUseMI = findFirstUse(MBB, I, *AS, AsDist);
 407       if (AsDist < Dist) {
 408         Dist = AsDist;
 409         UseMI = AsUseMI;
 410       }
 411     }
 412     if (Dist >= MaxDist) {
 413       MaxDist = Dist;
 414       MaxUseMI = UseMI;
 415       SReg = Reg;
 416     }
 417     Reg = Candidates.find_next(Reg);
 418   }
 419
 420   assert(ScavengedReg == 0 &&
 421          "Scavenger slot is live, unable to scavenge another register!");
 422
 423   // Avoid infinite regress
 424   ScavengedReg = SReg;
 425
 426   // Make sure SReg is marked as used. It could be considered available
 427   // if it is one of the callee saved registers, but hasn't been spilled.
 428   if (!isUsed(SReg)) {
 429     MBB->addLiveIn(SReg);
 430     setUsed(SReg);
 431   }
 432
 433   // Spill the scavenged register before I.
 434   TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
 435   MachineBasicBlock::iterator II = prior(I);
 436   TRI->eliminateFrameIndex(II, SPAdj, this);
 437
 438   // Restore the scavenged register before its use (or first terminator).
 439   II = MaxUseMI
 440     ? MachineBasicBlock::iterator(MaxUseMI) : MBB->getFirstTerminator();
 441   TII->loadRegFromStackSlot(*MBB, II, SReg, ScavengingFrameIndex, RC);
 442   ScavengeRestore = prior(II);
 443   // Doing this here leads to infinite regress
 444   // ScavengedReg = SReg;
 445   ScavengedRC = RC;
 446
 447   return SReg;
 448 }