lib/CodeGen/LiveStackAnalysis.cpp

   1 //===-- LiveStackAnalysis.cpp - Live Stack Slot Analysis ------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file implements the live stack slot analysis pass. It is analogous to
  11 // live interval analysis except it's analyzing liveness of stack slots rather
  12 // than registers.
  13 //
  14 //===----------------------------------------------------------------------===//
  15
  16 #define DEBUG_TYPE "livestacks"
  17 #include "llvm/CodeGen/LiveStackAnalysis.h"
  18 #include "llvm/CodeGen/Passes.h"
  19 #include "llvm/Target/TargetRegisterInfo.h"
  20 #include "llvm/Support/Debug.h"
  21 #include "llvm/ADT/Statistic.h"
  22 using namespace llvm;
  23
  24 char LiveStacks::ID = 0;
  25 static RegisterPass<LiveStacks> X("livestacks", "Live Stack Slot Analysis");
  26
  27 void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
  28   AU.setPreservesAll();
  29   MachineFunctionPass::getAnalysisUsage(AU);
  30 }
  31
  32 void LiveStacks::releaseMemory() {
  33   // Release VNInfo memroy regions after all VNInfo objects are dtor'd.
  34   VNInfoAllocator.Reset();
  35   S2IMap.clear();
  36   S2RCMap.clear();
  37 }
  38
  39 bool LiveStacks::runOnMachineFunction(MachineFunction &) {
  40   // FIXME: No analysis is being done right now. We are relying on the
  41   // register allocators to provide the information.
  42   return false;
  43 }
  44
  45 /// print - Implement the dump method.
  46 void LiveStacks::print(std::ostream &O, const Module*) const {
  47   O << "********** INTERVALS **********\n";
  48   for (const_iterator I = begin(), E = end(); I != E; ++I) {
  49     I->second.print(O);
  50     int Slot = I->first;
  51     const TargetRegisterClass *RC = getIntervalRegClass(Slot);
  52     if (RC)
  53       O << " [" << RC->getName() << "]\n";
  54     else
  55       O << " [Unknown]\n";
  56   }
  57 }