lib/Target/PowerPC/PPCFrameInfo.h

   1 //===-- PPCFrameInfo.h - Define TargetFrameInfo for PowerPC -----*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef POWERPC_FRAMEINFO_H
  14 #define POWERPC_FRAMEINFO_H
  15
  16 #include "PPC.h"
  17 #include "PPCSubtarget.h"
  18 #include "llvm/Target/TargetFrameInfo.h"
  19 #include "llvm/Target/TargetMachine.h"
  20 #include "llvm/ADT/STLExtras.h"
  21
  22 namespace llvm {
  23
  24 class PPCFrameInfo: public TargetFrameInfo {
  25   const TargetMachine &TM;
  26
  27 public:
  28   PPCFrameInfo(const TargetMachine &tm, bool LP64)
  29     : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0), TM(tm) {
  30   }
  31
  32   /// getReturnSaveOffset - Return the previous frame offset to save the
  33   /// return address.
  34   static unsigned getReturnSaveOffset(bool isPPC64, bool isDarwinABI) {
  35     if (isDarwinABI)
  36       return isPPC64 ? 16 : 8;
  37     // SVR4 ABI:
  38     return isPPC64 ? 16 : 4;
  39   }
  40
  41   /// getFramePointerSaveOffset - Return the previous frame offset to save the
  42   /// frame pointer.
  43   static unsigned getFramePointerSaveOffset(bool isPPC64, bool isDarwinABI) {
  44     // For the Darwin ABI:
  45     // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area
  46     // for saving the frame pointer (if needed.)  While the published ABI has
  47     // not used this slot since at least MacOSX 10.2, there is older code
  48     // around that does use it, and that needs to continue to work.
  49     if (isDarwinABI)
  50       return isPPC64 ? -8U : -4U;
  51
  52     // SVR4 ABI: First slot in the general register save area.
  53     return isPPC64 ? -8U : -4U;
  54   }
  55
  56   /// getLinkageSize - Return the size of the PowerPC ABI linkage area.
  57   ///
  58   static unsigned getLinkageSize(bool isPPC64, bool isDarwinABI) {
  59     if (isDarwinABI || isPPC64)
  60       return 6 * (isPPC64 ? 8 : 4);
  61
  62     // SVR4 ABI:
  63     return 8;
  64   }
  65
  66   /// getMinCallArgumentsSize - Return the size of the minium PowerPC ABI
  67   /// argument area.
  68   static unsigned getMinCallArgumentsSize(bool isPPC64, bool isDarwinABI) {
  69     // For the Darwin ABI / 64-bit SVR4 ABI:
  70     // The prolog code of the callee may store up to 8 GPR argument registers to
  71     // the stack, allowing va_start to index over them in memory if its varargs.
  72     // Because we cannot tell if this is needed on the caller side, we have to
  73     // conservatively assume that it is needed.  As such, make sure we have at
  74     // least enough stack space for the caller to store the 8 GPRs.
  75     if (isDarwinABI || isPPC64)
  76       return 8 * (isPPC64 ? 8 : 4);
  77
  78     // 32-bit SVR4 ABI:
  79     // There is no default stack allocated for the 8 first GPR arguments.
  80     return 0;
  81   }
  82
  83   /// getMinCallFrameSize - Return the minimum size a call frame can be using
  84   /// the PowerPC ABI.
  85   static unsigned getMinCallFrameSize(bool isPPC64, bool isDarwinABI) {
  86     // The call frame needs to be at least big enough for linkage and 8 args.
  87     return getLinkageSize(isPPC64, isDarwinABI) +
  88            getMinCallArgumentsSize(isPPC64, isDarwinABI);
  89   }
  90
  91   // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
  92   const SpillSlot *
  93   getCalleeSavedSpillSlots(unsigned &NumEntries) const {
  94     if (TM.getSubtarget<PPCSubtarget>().isDarwinABI()) {
  95       NumEntries = 1;
  96       if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
  97         static const SpillSlot darwin64Offsets = {PPC::X31, -8};
  98         return &darwin64Offsets;
  99       } else {
 100         static const SpillSlot darwinOffsets = {PPC::R31, -4};
 101         return &darwinOffsets;
 102       }
 103     }
 104
 105     // Early exit if not using the SVR4 ABI.
 106     if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()) {
 107       NumEntries = 0;
 108       return 0;
 109     }
 110
 111     static const SpillSlot Offsets[] = {
 112       // Floating-point register save area offsets.
 113       {PPC::F31, -8},
 114       {PPC::F30, -16},
 115       {PPC::F29, -24},
 116       {PPC::F28, -32},
 117       {PPC::F27, -40},
 118       {PPC::F26, -48},
 119       {PPC::F25, -56},
 120       {PPC::F24, -64},
 121       {PPC::F23, -72},
 122       {PPC::F22, -80},
 123       {PPC::F21, -88},
 124       {PPC::F20, -96},
 125       {PPC::F19, -104},
 126       {PPC::F18, -112},
 127       {PPC::F17, -120},
 128       {PPC::F16, -128},
 129       {PPC::F15, -136},
 130       {PPC::F14, -144},
 131
 132       // General register save area offsets.
 133       {PPC::R31, -4},
 134       {PPC::R30, -8},
 135       {PPC::R29, -12},
 136       {PPC::R28, -16},
 137       {PPC::R27, -20},
 138       {PPC::R26, -24},
 139       {PPC::R25, -28},
 140       {PPC::R24, -32},
 141       {PPC::R23, -36},
 142       {PPC::R22, -40},
 143       {PPC::R21, -44},
 144       {PPC::R20, -48},
 145       {PPC::R19, -52},
 146       {PPC::R18, -56},
 147       {PPC::R17, -60},
 148       {PPC::R16, -64},
 149       {PPC::R15, -68},
 150       {PPC::R14, -72},
 151
 152       // CR save area offset.
 153       // FIXME SVR4: Disable CR save area for now.
 154 //      {PPC::CR2, -4},
 155 //      {PPC::CR3, -4},
 156 //      {PPC::CR4, -4},
 157 //      {PPC::CR2LT, -4},
 158 //      {PPC::CR2GT, -4},
 159 //      {PPC::CR2EQ, -4},
 160 //      {PPC::CR2UN, -4},
 161 //      {PPC::CR3LT, -4},
 162 //      {PPC::CR3GT, -4},
 163 //      {PPC::CR3EQ, -4},
 164 //      {PPC::CR3UN, -4},
 165 //      {PPC::CR4LT, -4},
 166 //      {PPC::CR4GT, -4},
 167 //      {PPC::CR4EQ, -4},
 168 //      {PPC::CR4UN, -4},
 169
 170       // VRSAVE save area offset.
 171       {PPC::VRSAVE, -4},
 172
 173       // Vector register save area
 174       {PPC::V31, -16},
 175       {PPC::V30, -32},
 176       {PPC::V29, -48},
 177       {PPC::V28, -64},
 178       {PPC::V27, -80},
 179       {PPC::V26, -96},
 180       {PPC::V25, -112},
 181       {PPC::V24, -128},
 182       {PPC::V23, -144},
 183       {PPC::V22, -160},
 184       {PPC::V21, -176},
 185       {PPC::V20, -192}
 186     };
 187
 188     static const SpillSlot Offsets64[] = {
 189       // Floating-point register save area offsets.
 190       {PPC::F31, -8},
 191       {PPC::F30, -16},
 192       {PPC::F29, -24},
 193       {PPC::F28, -32},
 194       {PPC::F27, -40},
 195       {PPC::F26, -48},
 196       {PPC::F25, -56},
 197       {PPC::F24, -64},
 198       {PPC::F23, -72},
 199       {PPC::F22, -80},
 200       {PPC::F21, -88},
 201       {PPC::F20, -96},
 202       {PPC::F19, -104},
 203       {PPC::F18, -112},
 204       {PPC::F17, -120},
 205       {PPC::F16, -128},
 206       {PPC::F15, -136},
 207       {PPC::F14, -144},
 208
 209       // General register save area offsets.
 210       // FIXME 64-bit SVR4: Are 32-bit registers actually allocated in 64-bit
 211       //                    mode?
 212       {PPC::R31, -4},
 213       {PPC::R30, -12},
 214       {PPC::R29, -20},
 215       {PPC::R28, -28},
 216       {PPC::R27, -36},
 217       {PPC::R26, -44},
 218       {PPC::R25, -52},
 219       {PPC::R24, -60},
 220       {PPC::R23, -68},
 221       {PPC::R22, -76},
 222       {PPC::R21, -84},
 223       {PPC::R20, -92},
 224       {PPC::R19, -100},
 225       {PPC::R18, -108},
 226       {PPC::R17, -116},
 227       {PPC::R16, -124},
 228       {PPC::R15, -132},
 229       {PPC::R14, -140},
 230
 231       {PPC::X31, -8},
 232       {PPC::X30, -16},
 233       {PPC::X29, -24},
 234       {PPC::X28, -32},
 235       {PPC::X27, -40},
 236       {PPC::X26, -48},
 237       {PPC::X25, -56},
 238       {PPC::X24, -64},
 239       {PPC::X23, -72},
 240       {PPC::X22, -80},
 241       {PPC::X21, -88},
 242       {PPC::X20, -96},
 243       {PPC::X19, -104},
 244       {PPC::X18, -112},
 245       {PPC::X17, -120},
 246       {PPC::X16, -128},
 247       {PPC::X15, -136},
 248       {PPC::X14, -144},
 249
 250       // CR save area offset.
 251       // FIXME SVR4: Disable CR save area for now.
 252 //      {PPC::CR2, -4},
 253 //      {PPC::CR3, -4},
 254 //      {PPC::CR4, -4},
 255 //      {PPC::CR2LT, -4},
 256 //      {PPC::CR2GT, -4},
 257 //      {PPC::CR2EQ, -4},
 258 //      {PPC::CR2UN, -4},
 259 //      {PPC::CR3LT, -4},
 260 //      {PPC::CR3GT, -4},
 261 //      {PPC::CR3EQ, -4},
 262 //      {PPC::CR3UN, -4},
 263 //      {PPC::CR4LT, -4},
 264 //      {PPC::CR4GT, -4},
 265 //      {PPC::CR4EQ, -4},
 266 //      {PPC::CR4UN, -4},
 267
 268       // VRSAVE save area offset.
 269       {PPC::VRSAVE, -4},
 270
 271       // Vector register save area
 272       {PPC::V31, -16},
 273       {PPC::V30, -32},
 274       {PPC::V29, -48},
 275       {PPC::V28, -64},
 276       {PPC::V27, -80},
 277       {PPC::V26, -96},
 278       {PPC::V25, -112},
 279       {PPC::V24, -128},
 280       {PPC::V23, -144},
 281       {PPC::V22, -160},
 282       {PPC::V21, -176},
 283       {PPC::V20, -192}
 284     };
 285
 286     if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
 287       NumEntries = array_lengthof(Offsets64);
 288
 289       return Offsets64;
 290     } else {
 291       NumEntries = array_lengthof(Offsets);
 292
 293       return Offsets;
 294     }
 295   }
 296 };
 297
 298 } // End llvm namespace
 299
 300 #endif