From 0c220395a657c566532175d3c80cc5d7024c8849 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=C3=98yvind=20Harboe?= Date: Mon, 22 Nov 2010 20:51:57 +0100 Subject: [PATCH] zpu: simple fn with stack slots compile This bears some remote resemblance to what I'm after.... clang -ccc-host-triple zpu-none-none test3.c -S int b; int c; void foo(void) { int d = b; int e = c; int f; f = d + e; c = f; } => .file "test3.c" .text .globl foo .align 2 .type foo,@function load b %r0 storestackslot %r0 12, %sp load c %r0 storestackslot %r0 16, %sp loadstackslot 12, %sp %r1 add %r0 %r1 %r0 storestackslot %r0 20, %sp storereg %r0 c $tmp0: .size foo, ($tmp0)-foo .type b,@object .comm b,4,4 .type c,@object .comm c,4,4 --- lib/Target/ZPU/AsmPrinter/ZPUAsmPrinter.cpp | 4 +++- lib/Target/ZPU/ZPUISelDAGToDAG.cpp | 18 ++++++++++------ lib/Target/ZPU/ZPUInstrInfo.td | 22 +++++++++++++++++--- lib/Target/ZPU/ZPURegisterInfo.cpp | 32 ++++++++++++++++++++++++++++- lib/Target/ZPU/ZPURegisterInfo.h | 1 + 5 files changed, 66 insertions(+), 11 deletions(-) diff --git a/lib/Target/ZPU/AsmPrinter/ZPUAsmPrinter.cpp b/lib/Target/ZPU/AsmPrinter/ZPUAsmPrinter.cpp index f7023074bf..cc91093b19 100644 --- a/lib/Target/ZPU/AsmPrinter/ZPUAsmPrinter.cpp +++ b/lib/Target/ZPU/AsmPrinter/ZPUAsmPrinter.cpp @@ -211,7 +211,9 @@ void ZPUAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum, void ZPUAsmPrinter:: printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O, const char *Modifier) { - O << "asm 12"; + printOperand(MI, opNum+1, O); + O << ", "; + printOperand(MI, opNum, O); } void ZPUAsmPrinter:: diff --git a/lib/Target/ZPU/ZPUISelDAGToDAG.cpp b/lib/Target/ZPU/ZPUISelDAGToDAG.cpp index 638a060e82..8187a31d58 100644 --- a/lib/Target/ZPU/ZPUISelDAGToDAG.cpp +++ b/lib/Target/ZPU/ZPUISelDAGToDAG.cpp @@ -78,7 +78,7 @@ private: const ZPUInstrInfo *getInstrInfo() { return getTargetMachine().getInstrInfo(); } - bool SelectAddr(SDValue N, SDValue &Out); + bool SelectAddr(SDValue N, SDValue &sp, SDValue &offset); }; SDNode *ZPUDAGToDAGISel::SelectOperand(SDNode *N) { @@ -114,11 +114,17 @@ SDNode *ZPUDAGToDAGISel::Select(SDNode *N) { return SelectCode(N); } -/// SelectAddr - returns true if it is able pattern match an addressing mode. -/// It returns the operands which make up the maximal addressing mode it can -/// match by reference. -bool ZPUDAGToDAGISel::SelectAddr(SDValue N, SDValue &Out) { - return true; +/* Support only frame indexes here */ +bool ZPUDAGToDAGISel::SelectAddr(SDValue N, SDValue &Base, SDValue &Offset) { + + if (N.getOpcode() != ISD::FrameIndex) + return false; + + int FI = cast(N)->getIndex(); + Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); + /* FIX!!!! how do I get the offset??? */ + Offset = CurDAG->getTargetConstant(0, MVT::i32); + return true; } diff --git a/lib/Target/ZPU/ZPUInstrInfo.td b/lib/Target/ZPU/ZPUInstrInfo.td index a66cd6d595..45f4f93e06 100644 --- a/lib/Target/ZPU/ZPUInstrInfo.td +++ b/lib/Target/ZPU/ZPUInstrInfo.td @@ -25,10 +25,14 @@ def memaddr : Operand { let MIOperandInfo = (ops i32imm); } -def ZPUWrapper: SDNode<"ZPUISD::Wrapper", SDTIntUnaryOp>; - // addressing mode -//def addr : ComplexPattern; +def addr : ComplexPattern; + +// Address operand +def mem : Operand { + let PrintMethod = "printMemOperand"; + let MIOperandInfo = (ops i32imm, CPURegs); +} def IM : ZPUIm <(outs CPURegs:$dst), (ins i32imm:$a), @@ -52,4 +56,16 @@ def ZPUSTOREREG : ZPUIm <(outs), (ins memdst:$dst, CPURegs:$a), def ZPULOAD : ZPUIm <(outs CPURegs:$dst), (ins memdst:$src), "load $src $dst", [(set CPURegs:$dst, (load tglobaladdr:$src))]>; + +def ZPUSTORSTACKSLOT : ZPUIm <(outs), (ins mem:$dst, CPURegs:$a), + "storestackslot $a $dst", + [(store CPURegs:$a, addr:$dst)]>; + +def ZPULOADSTACKSLOT : ZPUIm <(outs CPURegs:$dst), (ins mem:$src), + "loadstackslot $src $dst", + [(set CPURegs:$dst, (load addr:$src))]>; + +def ADDSP : ZPUIm <(outs), (ins mem:$dst, mem:$a, mem:$b), + "addsp $dst $a $b", + [(store (add addr:$a, addr:$b), addr:$dst)]>; \ No newline at end of file diff --git a/lib/Target/ZPU/ZPURegisterInfo.cpp b/lib/Target/ZPU/ZPURegisterInfo.cpp index a891b24553..c8dbfe6830 100644 --- a/lib/Target/ZPU/ZPURegisterInfo.cpp +++ b/lib/Target/ZPU/ZPURegisterInfo.cpp @@ -36,7 +36,9 @@ using namespace llvm; -ZPURegisterInfo::ZPURegisterInfo(const TargetInstrInfo &tii) +ZPURegisterInfo::ZPURegisterInfo(const TargetInstrInfo &tii) : + ZPUGenRegisterInfo(), + TII(tii) { } @@ -152,6 +154,34 @@ void ZPURegisterInfo:: eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, RegScavenger *RS) const { + assert(SPAdj == 0 && "Unxpected"); + + unsigned i = 0; + MachineInstr &MI = *II; + MachineFunction &MF = *MI.getParent()->getParent(); + while (!MI.getOperand(i).isFI()) { + ++i; + assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); + } + + int FrameIndex = MI.getOperand(i).getIndex(); + + unsigned BasePtr = ZPU::SP; + + // This must be part of a rri or ri operand memory reference. Replace the + // FrameIndex with base register with BasePtr. Add an offset to the + // displacement field. + MI.getOperand(i).ChangeToRegister(BasePtr, false); + + // Offset is a either 12-bit unsigned or 20-bit signed integer. + // FIXME: handle "too long" displacements. + int Offset = + getFrameIndexOffset(MF, FrameIndex) + MI.getOperand(i+1).getImm(); + + // Check whether displacement is too long to fit into 12 bit zext field. + MI.setDesc(TII.get(MI.getOpcode())); + + MI.getOperand(i+1).ChangeToImmediate(Offset); } unsigned ZPURegisterInfo:: diff --git a/lib/Target/ZPU/ZPURegisterInfo.h b/lib/Target/ZPU/ZPURegisterInfo.h index 072790c129..bdd2622e8f 100644 --- a/lib/Target/ZPU/ZPURegisterInfo.h +++ b/lib/Target/ZPU/ZPURegisterInfo.h @@ -26,6 +26,7 @@ class ZPURegisterInfo : public ZPUGenRegisterInfo { public: ZPURegisterInfo(const TargetInstrInfo &tii); + const TargetInstrInfo &TII; virtual ~ZPURegisterInfo(); /// getRegisterNumbering - Given the enum value for some register, e.g. -- 2.11.4.GIT