From 76f816e399e5bd280141023315c2d9c25a970aa0 Mon Sep 17 00:00:00 2001 From: =?utf8?q?=C3=98yvind=20Harboe?= Date: Fri, 19 Nov 2010 00:17:48 +0100 Subject: [PATCH] zpu: wip eke out some simple instructions for load/store/add Added r0, r1, r2, r3 that I intend to convert to stack slots in a pass immediately after register allocation. int b; int c; void foo(void) { c = 1234 + b; } => clang -ccc-host-triple zpu-none-none test.c -S im 1234 %r0 load b %r1 add %r0 %r1 %r0 storereg %r0 c --- lib/Target/ZPU/ZPU.td | 12 ++++++++ lib/Target/ZPU/ZPUInstrInfo.td | 16 ++++++++++- lib/Target/ZPU/ZPURegisterInfo.td | 11 +++++-- lib/Target/ZPU/ZPUSubtarget.cpp | 24 ++++++++++++++++ lib/Target/ZPU/ZPUSubtarget.h | 57 +++++++++++++++++++++++++++++++++++++ lib/Target/ZPU/ZPUTargetMachine.cpp | 1 + lib/Target/ZPU/ZPUTargetMachine.h | 5 +++- 7 files changed, 122 insertions(+), 4 deletions(-) create mode 100644 lib/Target/ZPU/ZPUSubtarget.cpp create mode 100644 lib/Target/ZPU/ZPUSubtarget.h diff --git a/lib/Target/ZPU/ZPU.td b/lib/Target/ZPU/ZPU.td index aeee98ef65..69d9041f76 100644 --- a/lib/Target/ZPU/ZPU.td +++ b/lib/Target/ZPU/ZPU.td @@ -26,6 +26,18 @@ include "ZPUCallingConv.td" def ZPUInstrInfo : InstrInfo; +def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true", + "Enable 'byte/half swap' instructions.">; + +class Proc Features> + : Processor; + +def FeatureZPU1 : SubtargetFeature<"zpu11", "ZPUArchVersion", "ZPU1", + "ZPU ISA Support">; + +def : Proc<"zpu1", [FeatureZPU1]>; + + def ZPU : Target { let InstructionSet = ZPUInstrInfo; } diff --git a/lib/Target/ZPU/ZPUInstrInfo.td b/lib/Target/ZPU/ZPUInstrInfo.td index 03fc27491d..a66cd6d595 100644 --- a/lib/Target/ZPU/ZPUInstrInfo.td +++ b/lib/Target/ZPU/ZPUInstrInfo.td @@ -32,10 +32,24 @@ def ZPUWrapper: SDNode<"ZPUISD::Wrapper", SDTIntUnaryOp>; def IM : ZPUIm <(outs CPURegs:$dst), (ins i32imm:$a), - "im $a", + "im $a $dst", [(set CPURegs:$dst, imm:$a)]>; +def ADD : ZPUIm <(outs CPURegs:$dst), (ins CPURegs:$a, CPURegs:$b), + "add $dst $a $b", + [(set CPURegs:$dst, (add CPURegs:$a, CPURegs:$b))]>; // First operands, in the DAG the addressing modes def ZPUSTORE : ZPUIm <(outs), (ins memdst:$dst, i32imm:$a), "store $a $dst", [(store imm:$a, tglobaladdr:$dst)]>; + +// First operands, in the DAG the addressing modes +def ZPUSTOREREG : ZPUIm <(outs), (ins memdst:$dst, CPURegs:$a), + "storereg $a $dst", + [(store CPURegs:$a, tglobaladdr:$dst)]>; + + +def ZPULOAD : ZPUIm <(outs CPURegs:$dst), (ins memdst:$src), + "load $src $dst", + [(set CPURegs:$dst, (load tglobaladdr:$src))]>; + \ No newline at end of file diff --git a/lib/Target/ZPU/ZPURegisterInfo.td b/lib/Target/ZPU/ZPURegisterInfo.td index 05ec50e46f..9b2ceb6ff7 100644 --- a/lib/Target/ZPU/ZPURegisterInfo.td +++ b/lib/Target/ZPU/ZPURegisterInfo.td @@ -26,8 +26,14 @@ let Namespace = "ZPU" in { // General Purpose Registers def PC : ZPUReg<"pc">, DwarfRegNum<[0]>; def SP : ZPUReg<"sp">, DwarfRegNum<[1]>; - def FP : ZPUReg<"fp">, DwarfRegNum<[2]>; - def RETVAL : ZPUReg<"retval">, DwarfRegNum<[3]>; + def FP : ZPUReg<"fp">, DwarfRegNum<[2]>; // Frame pointer + def RETVAL : ZPUReg<"retval">, DwarfRegNum<[3]>; // return value + // These are just a few registers to satisfy the register allocator. + // We'll convert them to stack slots immediately after register allocation + def R0 : ZPUReg<"r0">, DwarfRegNum<[4]>; + def R1 : ZPUReg<"r1">, DwarfRegNum<[5]>; + def R2 : ZPUReg<"r2">, DwarfRegNum<[6]>; + def R3 : ZPUReg<"r3">, DwarfRegNum<[7]>; } //===----------------------------------------------------------------------===// @@ -37,5 +43,6 @@ let Namespace = "ZPU" in { def CPURegs : RegisterClass<"ZPU", [i32], 32, // Program counter and stack pointer is all there is [PC, SP, + R0, R1, R2, R3, FP, RETVAL ]>; diff --git a/lib/Target/ZPU/ZPUSubtarget.cpp b/lib/Target/ZPU/ZPUSubtarget.cpp new file mode 100644 index 0000000000..4161da3ef7 --- /dev/null +++ b/lib/Target/ZPU/ZPUSubtarget.cpp @@ -0,0 +1,24 @@ +//===- ZPUSubtarget.cpp - ZPU Subtarget Information -----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the ZPU specific subclass of TargetSubtarget. +// +//===----------------------------------------------------------------------===// + +#include "ZPUSubtarget.h" +#include "ZPU.h" +#include "ZPUGenSubtarget.inc" +using namespace llvm; + +ZPUSubtarget::ZPUSubtarget(const std::string &TT, const std::string &FS, + bool little) : + HasSwap(false),ZPUArchVersion(ZPU1) + +{ +} diff --git a/lib/Target/ZPU/ZPUSubtarget.h b/lib/Target/ZPU/ZPUSubtarget.h new file mode 100644 index 0000000000..63e04e26f7 --- /dev/null +++ b/lib/Target/ZPU/ZPUSubtarget.h @@ -0,0 +1,57 @@ +//=====-- ZPUSubtarget.h - Define Subtarget for the ZPU -----*- C++ -*--====// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the ZPU specific subclass of TargetSubtarget. +// +//===----------------------------------------------------------------------===// + +#ifndef ZPUSUBTARGET_H +#define ZPUSUBTARGET_H + +#include "llvm/Target/TargetSubtarget.h" +#include "llvm/Target/TargetMachine.h" + +#include + +namespace llvm { + +class ZPUSubtarget : public TargetSubtarget { + +public: + + +protected: + + InstrItineraryData InstrItins; + +public: + + enum ZPUArchEnum { + ZPU1 + }; + // Mips architecture version + ZPUArchEnum ZPUArchVersion; + + // HasSwap - Byte and half swap instructions. + bool HasSwap; + /// This constructor initializes the data members to match that + /// of the specified triple. + ZPUSubtarget(const std::string &TT, const std::string &FS, bool little); + + /// ParseSubtargetFeatures - Parses features string setting specified + /// subtarget options. Definition of function is auto generated by tblgen. + std::string ParseSubtargetFeatures(const std::string &FS, + const std::string &CPU); + + bool hasSwap() const { return HasSwap; } + +}; +} // End llvm namespace + +#endif diff --git a/lib/Target/ZPU/ZPUTargetMachine.cpp b/lib/Target/ZPU/ZPUTargetMachine.cpp index 5b976abcbf..5e15850bbe 100644 --- a/lib/Target/ZPU/ZPUTargetMachine.cpp +++ b/lib/Target/ZPU/ZPUTargetMachine.cpp @@ -44,6 +44,7 @@ ZPUTargetMachine:: ZPUTargetMachine(const Target &T, const std::string &TT, const std::string &FS, bool isLittle): LLVMTargetMachine(T, TT), + Subtarget(TT, FS, isLittle), DataLayout(std::string("e-p:32:32:32-i8:8:32-i16:16:32-n32")), InstrInfo(*this), FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0), diff --git a/lib/Target/ZPU/ZPUTargetMachine.h b/lib/Target/ZPU/ZPUTargetMachine.h index a8abe6b616..933c8c4737 100644 --- a/lib/Target/ZPU/ZPUTargetMachine.h +++ b/lib/Target/ZPU/ZPUTargetMachine.h @@ -14,6 +14,7 @@ #ifndef ZPUTARGETMACHINE_H #define ZPUTARGETMACHINE_H +#include "ZPUSubtarget.h" #include "ZPUInstrInfo.h" #include "ZPUISelLowering.h" #include "llvm/Target/TargetMachine.h" @@ -28,6 +29,7 @@ namespace llvm { ZPUInstrInfo InstrInfo; TargetFrameInfo FrameInfo; ZPUTargetLowering TLInfo; + ZPUSubtarget Subtarget; public: ZPUTargetMachine(const Target &T, const std::string &TT, const std::string &FS, @@ -39,7 +41,8 @@ namespace llvm { { return &FrameInfo; } virtual const TargetData *getTargetData() const { return &DataLayout;} - + virtual const ZPUSubtarget *getSubtargetImpl() const + { return &Subtarget; } virtual const ZPURegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } -- 2.11.4.GIT