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[mascara-docs.git] / i386 / linux-2.3.21 / drivers / net / sunqe.c
blob45140e386a82a81ab7e9b3194d6d992aa28c7bb4
1 /* sunqe.c: Sparc QuadEthernet 10baseT SBUS card driver.
2 * Once again I am out to prove that every ethernet
3 * controller out there can be most efficiently programmed
4 * if you make it look like a LANCE.
5 *
6 * Copyright (C) 1996, 1999 David S. Miller (davem@redhat.com)
7 */
8
9 static char *version =
10 "sunqe.c:v2.0 9/9/99 David S. Miller (davem@redhat.com)\n";
11
12 #include <linux/module.h>
13
14 #include <linux/kernel.h>
15 #include <linux/sched.h>
16 #include <linux/types.h>
17 #include <linux/fcntl.h>
18 #include <linux/interrupt.h>
19 #include <linux/ptrace.h>
20 #include <linux/ioport.h>
21 #include <linux/in.h>
22 #include <linux/malloc.h>
23 #include <linux/string.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26
27 #include <asm/system.h>
28 #include <asm/bitops.h>
29 #include <asm/io.h>
30 #include <asm/dma.h>
31 #include <linux/errno.h>
32 #include <asm/byteorder.h>
33
34 #include <asm/idprom.h>
35 #include <asm/sbus.h>
36 #include <asm/openprom.h>
37 #include <asm/oplib.h>
38 #include <asm/auxio.h>
39 #include <asm/pgtable.h>
40 #include <asm/irq.h>
41
42 #include <linux/netdevice.h>
43 #include <linux/etherdevice.h>
44 #include <linux/skbuff.h>
45
46 #include "sunqe.h"
47
48 #ifdef MODULE
49 static struct sunqec *root_qec_dev = NULL;
50 #endif
51
52 static void qe_set_multicast(struct net_device *dev);
53
54 #define QEC_RESET_TRIES 200
55
56 static inline int qec_global_reset(struct qe_globreg *gregs)
57 {
58 int tries = QEC_RESET_TRIES;
59
60 gregs->ctrl = GLOB_CTRL_RESET;
61 while(--tries) {
62 if(gregs->ctrl & GLOB_CTRL_RESET) {
63 udelay(20);
64 continue;
65 }
66 break;
67 }
68 if(tries)
69 return 0;
70 printk("QuadEther: AIEEE cannot reset the QEC!\n");
71 return -1;
72 }
73
74 #define MACE_RESET_RETRIES 200
75 #define QE_RESET_RETRIES 200
76
77 static inline int qe_stop(struct sunqe *qep)
78 {
79 struct qe_creg *cregs = qep->qcregs;
80 struct qe_mregs *mregs = qep->mregs;
81 int tries;
82
83 /* Reset the MACE, then the QEC channel. */
84 mregs->bconfig = MREGS_BCONFIG_RESET;
85 tries = MACE_RESET_RETRIES;
86 while(--tries) {
87 if(mregs->bconfig & MREGS_BCONFIG_RESET) {
88 udelay(20);
89 continue;
90 }
91 break;
92 }
93 if(!tries) {
94 printk("QuadEther: AIEEE cannot reset the MACE!\n");
95 return -1;
96 }
97
98 cregs->ctrl = CREG_CTRL_RESET;
99 tries = QE_RESET_RETRIES;
100 while(--tries) {
101 if(cregs->ctrl & CREG_CTRL_RESET) {
102 udelay(20);
103 continue;
104 }
105 break;
106 }
107 if(!tries) {
108 printk("QuadEther: Cannot reset QE channel!\n");
109 return -1;
110 }
111 return 0;
112 }
113
114 static void qe_init_rings(struct sunqe *qep)
115 {
116 struct qe_init_block *qb = qep->qe_block;
117 struct sunqe_buffers *qbufs = qep->buffers;
118 __u32 qbufs_dvma = qep->buffers_dvma;
119 int i;
120
121 qep->rx_new = qep->rx_old = qep->tx_new = qep->tx_old = 0;
122 memset(qb, 0, sizeof(struct qe_init_block));
123 memset(qbufs, 0, sizeof(struct sunqe_buffers));
124 for(i = 0; i < RX_RING_SIZE; i++) {
125 qb->qe_rxd[i].rx_addr = qbufs_dvma + qebuf_offset(rx_buf, i);
126 qb->qe_rxd[i].rx_flags =
127 (RXD_OWN | ((RXD_PKT_SZ) & RXD_LENGTH));
128 }
129 }
130
131 static int qe_init(struct sunqe *qep, int from_irq)
132 {
133 struct sunqec *qecp = qep->parent;
134 struct qe_creg *cregs = qep->qcregs;
135 struct qe_mregs *mregs = qep->mregs;
136 struct qe_globreg *gregs = qecp->gregs;
137 unsigned char *e = &qep->dev->dev_addr[0];
138 volatile unsigned char garbage;
139 int i;
140
141 /* Shut it up. */
142 if(qe_stop(qep))
143 return -EAGAIN;
144
145 /* Setup initial rx/tx init block pointers. */
146 cregs->rxds = qep->qblock_dvma + qib_offset(qe_rxd, 0);
147 cregs->txds = qep->qblock_dvma + qib_offset(qe_txd, 0);
148
149 /* Enable/mask the various irq's. */
150 cregs->rimask = 0;
151 cregs->timask = 1;
152
153 cregs->qmask = 0;
154 cregs->mmask = CREG_MMASK_RXCOLL;
155
156 /* Setup the FIFO pointers into QEC local memory. */
157 cregs->rxwbufptr = cregs->rxrbufptr = qep->channel * gregs->msize;
158 cregs->txwbufptr = cregs->txrbufptr = cregs->rxrbufptr + gregs->rsize;
159
160 /* Clear the channel collision counter. */
161 cregs->ccnt = 0;
162
163 /* For 10baseT, inter frame space nor throttle seems to be necessary. */
164 cregs->pipg = 0;
165
166 /* Now dork with the AMD MACE. */
167 mregs->phyconfig = MREGS_PHYCONFIG_AUTO;
168 mregs->txfcntl = MREGS_TXFCNTL_AUTOPAD; /* Save us some tx work. */
169 mregs->rxfcntl = 0;
170
171 /* The QEC dma's the rx'd packets from local memory out to main memory,
172 * and therefore it interrupts when the packet reception is "complete".
173 * So don't listen for the MACE talking about it.
174 */
175 mregs->imask = (MREGS_IMASK_COLL | MREGS_IMASK_RXIRQ);
176
177 mregs->bconfig = (MREGS_BCONFIG_BSWAP | MREGS_BCONFIG_64TS);
178 mregs->fconfig = (MREGS_FCONFIG_TXF16 | MREGS_FCONFIG_RXF32 |
179 MREGS_FCONFIG_RFWU | MREGS_FCONFIG_TFWU);
180
181 /* Only usable interface on QuadEther is twisted pair. */
182 mregs->plsconfig = (MREGS_PLSCONFIG_TP);
183
184 /* Tell MACE we are changing the ether address. */
185 mregs->iaconfig = (MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_PARESET);
186 while ((mregs->iaconfig & MREGS_IACONFIG_ACHNGE) != 0)
187 barrier();
188 mregs->ethaddr = e[0];
189 mregs->ethaddr = e[1];
190 mregs->ethaddr = e[2];
191 mregs->ethaddr = e[3];
192 mregs->ethaddr = e[4];
193 mregs->ethaddr = e[5];
194
195 /* Clear out the address filter. */
196 mregs->iaconfig = (MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET);
197 while ((mregs->iaconfig & MREGS_IACONFIG_ACHNGE) != 0)
198 barrier();
199 for(i = 0; i < 8; i++)
200 mregs->filter = 0;
201
202 /* Address changes are now complete. */
203 mregs->iaconfig = 0;
204
205 qe_init_rings(qep);
206
207 /* Wait a little bit for the link to come up... */
208 mdelay(5);
209 if(!(mregs->phyconfig & MREGS_PHYCONFIG_LTESTDIS)) {
210 int tries = 50;
211
212 while (tries--) {
213 mdelay(5);
214 barrier();
215 if((mregs->phyconfig & MREGS_PHYCONFIG_LSTAT) != 0)
216 break;
217 }
218 if (tries == 0)
219 printk("%s: Warning, link state is down.\n", qep->dev->name);
220 }
221
222 /* Missed packet counter is cleared on a read. */
223 garbage = mregs->mpcnt;
224
225 /* Reload multicast information, this will enable the receiver
226 * and transmitter. But set the base mconfig value right now.
227 */
228 qe_set_multicast(qep->dev);
229
230 /* QEC should now start to show interrupts. */
231 return 0;
232 }
233
234 /* Grrr, certain error conditions completely lock up the AMD MACE,
235 * so when we get these we _must_ reset the chip.
236 */
237 static int qe_is_bolixed(struct sunqe *qep, unsigned int qe_status)
238 {
239 struct net_device *dev = qep->dev;
240 int mace_hwbug_workaround = 0;
241
242 if(qe_status & CREG_STAT_EDEFER) {
243 printk("%s: Excessive transmit defers.\n", dev->name);
244 qep->net_stats.tx_errors++;
245 }
246
247 if(qe_status & CREG_STAT_CLOSS) {
248 printk("%s: Carrier lost, link down?\n", dev->name);
249 qep->net_stats.tx_errors++;
250 qep->net_stats.tx_carrier_errors++;
251 }
252
253 if(qe_status & CREG_STAT_ERETRIES) {
254 printk("%s: Excessive transmit retries (more than 16).\n", dev->name);
255 qep->net_stats.tx_errors++;
256 mace_hwbug_workaround = 1;
257 }
258
259 if(qe_status & CREG_STAT_LCOLL) {
260 printk("%s: Late transmit collision.\n", dev->name);
261 qep->net_stats.tx_errors++;
262 qep->net_stats.collisions++;
263 mace_hwbug_workaround = 1;
264 }
265
266 if(qe_status & CREG_STAT_FUFLOW) {
267 printk("%s: Transmit fifo underflow, driver bug.\n", dev->name);
268 qep->net_stats.tx_errors++;
269 mace_hwbug_workaround = 1;
270 }
271
272 if(qe_status & CREG_STAT_JERROR) {
273 printk("%s: Jabber error.\n", dev->name);
274 }
275
276 if(qe_status & CREG_STAT_BERROR) {
277 printk("%s: Babble error.\n", dev->name);
278 }
279
280 if(qe_status & CREG_STAT_CCOFLOW) {
281 qep->net_stats.tx_errors += 256;
282 qep->net_stats.collisions += 256;
283 }
284
285 if(qe_status & CREG_STAT_TXDERROR) {
286 printk("%s: Transmit descriptor is bogus, driver bug.\n", dev->name);
287 qep->net_stats.tx_errors++;
288 qep->net_stats.tx_aborted_errors++;
289 mace_hwbug_workaround = 1;
290 }
291
292 if(qe_status & CREG_STAT_TXLERR) {
293 printk("%s: Transmit late error.\n", dev->name);
294 qep->net_stats.tx_errors++;
295 mace_hwbug_workaround = 1;
296 }
297
298 if(qe_status & CREG_STAT_TXPERR) {
299 printk("%s: Transmit DMA parity error.\n", dev->name);
300 qep->net_stats.tx_errors++;
301 qep->net_stats.tx_aborted_errors++;
302 mace_hwbug_workaround = 1;
303 }
304
305 if(qe_status & CREG_STAT_TXSERR) {
306 printk("%s: Transmit DMA sbus error ack.\n", dev->name);
307 qep->net_stats.tx_errors++;
308 qep->net_stats.tx_aborted_errors++;
309 mace_hwbug_workaround = 1;
310 }
311
312 if(qe_status & CREG_STAT_RCCOFLOW) {
313 qep->net_stats.rx_errors += 256;
314 qep->net_stats.collisions += 256;
315 }
316
317 if(qe_status & CREG_STAT_RUOFLOW) {
318 qep->net_stats.rx_errors += 256;
319 qep->net_stats.rx_over_errors += 256;
320 }
321
322 if(qe_status & CREG_STAT_MCOFLOW) {
323 qep->net_stats.rx_errors += 256;
324 qep->net_stats.rx_missed_errors += 256;
325 }
326
327 if(qe_status & CREG_STAT_RXFOFLOW) {
328 printk("%s: Receive fifo overflow.\n", dev->name);
329 qep->net_stats.rx_errors++;
330 qep->net_stats.rx_over_errors++;
331 }
332
333 if(qe_status & CREG_STAT_RLCOLL) {
334 printk("%s: Late receive collision.\n", dev->name);
335 qep->net_stats.rx_errors++;
336 qep->net_stats.collisions++;
337 }
338
339 if(qe_status & CREG_STAT_FCOFLOW) {
340 qep->net_stats.rx_errors += 256;
341 qep->net_stats.rx_frame_errors += 256;
342 }
343
344 if(qe_status & CREG_STAT_CECOFLOW) {
345 qep->net_stats.rx_errors += 256;
346 qep->net_stats.rx_crc_errors += 256;
347 }
348
349 if(qe_status & CREG_STAT_RXDROP) {
350 printk("%s: Receive packet dropped.\n", dev->name);
351 qep->net_stats.rx_errors++;
352 qep->net_stats.rx_dropped++;
353 qep->net_stats.rx_missed_errors++;
354 }
355
356 if(qe_status & CREG_STAT_RXSMALL) {
357 printk("%s: Receive buffer too small, driver bug.\n", dev->name);
358 qep->net_stats.rx_errors++;
359 qep->net_stats.rx_length_errors++;
360 }
361
362 if(qe_status & CREG_STAT_RXLERR) {
363 printk("%s: Receive late error.\n", dev->name);
364 qep->net_stats.rx_errors++;
365 mace_hwbug_workaround = 1;
366 }
367
368 if(qe_status & CREG_STAT_RXPERR) {
369 printk("%s: Receive DMA parity error.\n", dev->name);
370 qep->net_stats.rx_errors++;
371 qep->net_stats.rx_missed_errors++;
372 mace_hwbug_workaround = 1;
373 }
374
375 if(qe_status & CREG_STAT_RXSERR) {
376 printk("%s: Receive DMA sbus error ack.\n", dev->name);
377 qep->net_stats.rx_errors++;
378 qep->net_stats.rx_missed_errors++;
379 mace_hwbug_workaround = 1;
380 }
381
382 if(mace_hwbug_workaround)
383 qe_init(qep, 1);
384 return mace_hwbug_workaround;
385 }
386
387 /* Per-QE receive interrupt service routine. Just like on the happy meal
388 * we receive directly into skb's with a small packet copy water mark.
389 */
390 static void qe_rx(struct sunqe *qep)
391 {
392 struct qe_rxd *rxbase = &qep->qe_block->qe_rxd[0];
393 struct qe_rxd *this;
394 struct sunqe_buffers *qbufs = qep->buffers;
395 __u32 qbufs_dvma = qep->buffers_dvma;
396 int elem = qep->rx_new, drops = 0;
397 unsigned int flags;
398
399 this = &rxbase[elem];
400 while(!((flags = this->rx_flags) & RXD_OWN)) {
401 struct sk_buff *skb;
402 unsigned char *this_qbuf =
403 &qbufs->rx_buf[elem & (RX_RING_SIZE - 1)][0];
404 __u32 this_qbuf_dvma = qbufs_dvma +
405 qebuf_offset(rx_buf, (elem & (RX_RING_SIZE - 1)));
406 struct qe_rxd *end_rxd =
407 &rxbase[(elem+RX_RING_SIZE)&(RX_RING_MAXSIZE-1)];
408 int len = (flags & RXD_LENGTH) - 4; /* QE adds ether FCS size to len */
409
410 /* Check for errors. */
411 if(len < ETH_ZLEN) {
412 qep->net_stats.rx_errors++;
413 qep->net_stats.rx_length_errors++;
414 qep->net_stats.rx_dropped++;
415 } else {
416 skb = dev_alloc_skb(len + 2);
417 if(skb == 0) {
418 drops++;
419 qep->net_stats.rx_dropped++;
420 } else {
421 skb->dev = qep->dev;
422 skb_reserve(skb, 2);
423 skb_put(skb, len);
424 eth_copy_and_sum(skb, (unsigned char *)this_qbuf,
425 len, 0);
426 skb->protocol = eth_type_trans(skb, qep->dev);
427 netif_rx(skb);
428 qep->net_stats.rx_packets++;
429 qep->net_stats.rx_bytes+=len;
430 }
431 }
432 end_rxd->rx_addr = this_qbuf_dvma;
433 end_rxd->rx_flags = (RXD_OWN | ((RXD_PKT_SZ) & RXD_LENGTH));
434
435 elem = NEXT_RX(elem);
436 this = &rxbase[elem];
437 }
438 qep->rx_new = elem;
439 if(drops)
440 printk("%s: Memory squeeze, deferring packet.\n", qep->dev->name);
441 }
442
443 /* Interrupts for all QE's get filtered out via the QEC master controller,
444 * so we just run through each qe and check to see who is signaling
445 * and thus needs to be serviced.
446 */
447 static void qec_interrupt(int irq, void *dev_id, struct pt_regs *regs)
448 {
449 struct sunqec *qecp = (struct sunqec *) dev_id;
450 unsigned int qec_status;
451 int channel = 0;
452
453 /* Latch the status now. */
454 qec_status = qecp->gregs->stat;
455 while(channel < 4) {
456 if(qec_status & 0xf) {
457 struct sunqe *qep = qecp->qes[channel];
458 struct net_device *dev = qep->dev;
459 unsigned int qe_status;
460
461 dev->interrupt = 1;
462
463 qe_status = qep->qcregs->stat;
464 if(qe_status & CREG_STAT_ERRORS)
465 if(qe_is_bolixed(qep, qe_status))
466 goto next;
467
468 if(qe_status & CREG_STAT_RXIRQ)
469 qe_rx(qep);
470 next:
471 dev->interrupt = 0;
472 }
473 qec_status >>= 4;
474 channel++;
475 }
476 }
477
478 static int qe_open(struct net_device *dev)
479 {
480 struct sunqe *qep = (struct sunqe *) dev->priv;
481 int res;
482
483 qep->mconfig = (MREGS_MCONFIG_TXENAB |
484 MREGS_MCONFIG_RXENAB |
485 MREGS_MCONFIG_MBAENAB);
486 res = qe_init(qep, 0);
487 if(!res)
488 MOD_INC_USE_COUNT;
489
490 return res;
491 }
492
493 static int qe_close(struct net_device *dev)
494 {
495 struct sunqe *qep = (struct sunqe *) dev->priv;
496
497 qe_stop(qep);
498 MOD_DEC_USE_COUNT;
499 return 0;
500 }
501
502 /* Reclaim TX'd frames from the ring. */
503 static void qe_tx_reclaim(struct sunqe *qep)
504 {
505 struct qe_txd *txbase = &qep->qe_block->qe_txd[0];
506 struct net_device *dev = qep->dev;
507 int elem = qep->tx_old;
508
509 while(elem != qep->tx_new) {
510 unsigned int flags = txbase[elem].tx_flags;
511
512 if (flags & TXD_OWN)
513 break;
514 qep->net_stats.tx_packets++;
515 qep->net_stats.tx_bytes+=(flags & TXD_LENGTH);
516 elem = NEXT_TX(elem);
517 }
518 qep->tx_old = elem;
519
520 if(dev->tbusy && (TX_BUFFS_AVAIL(qep) > 0)) {
521 dev->tbusy = 0;
522 mark_bh(NET_BH);
523 }
524 }
525
526 /* Get a packet queued to go onto the wire. */
527 static int qe_start_xmit(struct sk_buff *skb, struct net_device *dev)
528 {
529 struct sunqe *qep = (struct sunqe *) dev->priv;
530 struct sunqe_buffers *qbufs = qep->buffers;
531 __u32 txbuf_dvma, qbufs_dvma = qep->buffers_dvma;
532 unsigned char *txbuf;
533 int len, entry;
534
535 qe_tx_reclaim(qep);
536
537 if(test_and_set_bit(0, (void *) &dev->tbusy) != 0) {
538 long tickssofar = jiffies - dev->trans_start;
539
540 if (tickssofar >= 40) {
541 printk("%s: transmit timed out, resetting\n", dev->name);
542 qe_init(qep, 1);
543 dev->tbusy = 0;
544 dev->trans_start = jiffies;
545 }
546 return 1;
547 }
548
549 if(!TX_BUFFS_AVAIL(qep))
550 return 1;
551
552 len = skb->len;
553 entry = qep->tx_new;
554
555 txbuf = &qbufs->tx_buf[entry & (TX_RING_SIZE - 1)][0];
556 txbuf_dvma = qbufs_dvma +
557 qebuf_offset(tx_buf, (entry & (TX_RING_SIZE - 1)));
558
559 /* Avoid a race... */
560 qep->qe_block->qe_txd[entry].tx_flags = TXD_UPDATE;
561
562 memcpy(txbuf, skb->data, len);
563
564 qep->qe_block->qe_txd[entry].tx_addr = txbuf_dvma;
565 qep->qe_block->qe_txd[entry].tx_flags =
566 (TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH));
567 qep->tx_new = NEXT_TX(entry);
568
569 /* Get it going. */
570 dev->trans_start = jiffies;
571 qep->qcregs->ctrl = CREG_CTRL_TWAKEUP;
572
573 dev_kfree_skb(skb);
574
575 if(TX_BUFFS_AVAIL(qep))
576 dev->tbusy = 0;
577
578 return 0;
579 }
580
581 static struct net_device_stats *qe_get_stats(struct net_device *dev)
582 {
583 struct sunqe *qep = (struct sunqe *) dev->priv;
584
585 return &qep->net_stats;
586 }
587
588 #define CRC_POLYNOMIAL_BE 0x04c11db7UL /* Ethernet CRC, big endian */
589 #define CRC_POLYNOMIAL_LE 0xedb88320UL /* Ethernet CRC, little endian */
590
591 static void qe_set_multicast(struct net_device *dev)
592 {
593 struct sunqe *qep = (struct sunqe *) dev->priv;
594 struct dev_mc_list *dmi = dev->mc_list;
595 unsigned char new_mconfig = qep->mconfig;
596 char *addrs;
597 int i, j, bit, byte;
598 u32 crc, poly = CRC_POLYNOMIAL_LE;
599
600 /* Lock out others. */
601 set_bit(0, (void *) &dev->tbusy);
602
603 if((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
604 qep->mregs->iaconfig = MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET;
605 while ((qep->mregs->iaconfig & MREGS_IACONFIG_ACHNGE) != 0)
606 barrier();
607 for(i = 0; i < 8; i++)
608 qep->mregs->filter = 0xff;
609 qep->mregs->iaconfig = 0;
610 } else if(dev->flags & IFF_PROMISC) {
611 new_mconfig |= MREGS_MCONFIG_PROMISC;
612 } else {
613 u16 hash_table[4];
614 unsigned char *hbytes = (unsigned char *) &hash_table[0];
615
616 for(i = 0; i < 4; i++)
617 hash_table[i] = 0;
618
619 for(i = 0; i < dev->mc_count; i++) {
620 addrs = dmi->dmi_addr;
621 dmi = dmi->next;
622
623 if(!(*addrs & 1))
624 continue;
625
626 crc = 0xffffffffU;
627 for(byte = 0; byte < 6; byte++) {
628 for(bit = *addrs++, j = 0; j < 8; j++, bit >>= 1) {
629 int test;
630
631 test = ((bit ^ crc) & 0x01);
632 crc >>= 1;
633 if(test)
634 crc = crc ^ poly;
635 }
636 }
637 crc >>= 26;
638 hash_table[crc >> 4] |= 1 << (crc & 0xf);
639 }
640 /* Program the qe with the new filter value. */
641 qep->mregs->iaconfig = MREGS_IACONFIG_ACHNGE | MREGS_IACONFIG_LARESET;
642 while ((qep->mregs->iaconfig & MREGS_IACONFIG_ACHNGE) != 0)
643 barrier();
644 for(i = 0; i < 8; i++)
645 qep->mregs->filter = *hbytes++;
646 qep->mregs->iaconfig = 0;
647 }
648
649 /* Any change of the logical address filter, the physical address,
650 * or enabling/disabling promiscuous mode causes the MACE to disable
651 * the receiver. So we must re-enable them here or else the MACE
652 * refuses to listen to anything on the network. Sheesh, took
653 * me a day or two to find this bug.
654 */
655 qep->mconfig = new_mconfig;
656 qep->mregs->mconfig = qep->mconfig;
657
658 /* Let us get going again. */
659 dev->tbusy = 0;
660 }
661
662 /* This is only called once at boot time for each card probed. */
663 static inline void qec_init_once(struct sunqec *qecp, struct linux_sbus_device *qsdev)
664 {
665 unsigned char bsizes = qecp->qec_bursts;
666
667 #ifdef __sparc_v9__
668 if (bsizes & DMA_BURST64) {
669 qecp->gregs->ctrl = GLOB_CTRL_B64;
670 } else
671 #endif
672 if(bsizes & DMA_BURST32) {
673 qecp->gregs->ctrl = GLOB_CTRL_B32;
674 } else {
675 qecp->gregs->ctrl = GLOB_CTRL_B16;
676 }
677
678 /* Packetsize only used in 100baseT BigMAC configurations,
679 * set it to zero just to be on the safe side.
680 */
681 qecp->gregs->psize = 0;
682
683 /* Set the local memsize register, divided up to one piece per QE channel. */
684 qecp->gregs->msize = (qsdev->reg_addrs[1].reg_size >> 2);
685
686 /* Divide up the local QEC memory amongst the 4 QE receiver and
687 * transmitter FIFOs. Basically it is (total / 2 / num_channels).
688 */
689 qecp->gregs->rsize = qecp->gregs->tsize =
690 (qsdev->reg_addrs[1].reg_size >> 2) >> 1;
691
692 }
693
694 /* Four QE's per QEC card. */
695 static inline int qec_ether_init(struct net_device *dev, struct linux_sbus_device *sdev)
696 {
697 static unsigned version_printed = 0;
698 struct net_device *qe_devs[4];
699 struct sunqe *qeps[4];
700 struct linux_sbus_device *qesdevs[4];
701 struct sunqec *qecp;
702 struct linux_prom_ranges qranges[8];
703 unsigned char bsizes, bsizes_more, num_qranges;
704 int i, j, res = ENOMEM;
705
706 dev = init_etherdev(0, sizeof(struct sunqe));
707 qe_devs[0] = dev;
708 qeps[0] = (struct sunqe *) dev->priv;
709 qeps[0]->channel = 0;
710 for(j = 0; j < 6; j++)
711 qe_devs[0]->dev_addr[j] = idprom->id_ethaddr[j];
712
713 if(version_printed++ == 0)
714 printk(version);
715
716 qe_devs[1] = qe_devs[2] = qe_devs[3] = NULL;
717 for(i = 1; i < 4; i++) {
718 qe_devs[i] = init_etherdev(0, sizeof(struct sunqe));
719 if(qe_devs[i] == NULL || qe_devs[i]->priv == NULL)
720 goto qec_free_devs;
721 qeps[i] = (struct sunqe *) qe_devs[i]->priv;
722 for(j = 0; j < 6; j++)
723 qe_devs[i]->dev_addr[j] = idprom->id_ethaddr[j];
724 qeps[i]->channel = i;
725 }
726 qecp = kmalloc(sizeof(struct sunqec), GFP_KERNEL);
727 if(qecp == NULL)
728 goto qec_free_devs;
729 qecp->qec_sbus_dev = sdev;
730
731 for(i = 0; i < 4; i++) {
732 qecp->qes[i] = qeps[i];
733 qeps[i]->dev = qe_devs[i];
734 qeps[i]->parent = qecp;
735 }
736
737 /* Link in channel 0. */
738 i = prom_getintdefault(sdev->child->prom_node, "channel#", -1);
739 if(i == -1) { res=ENODEV; goto qec_free_devs; }
740 qesdevs[i] = sdev->child;
741 qe_devs[i]->base_addr = (long) qesdevs[i];
742
743 /* Link in channel 1. */
744 i = prom_getintdefault(sdev->child->next->prom_node, "channel#", -1);
745 if(i == -1) { res=ENODEV; goto qec_free_devs; }
746 qesdevs[i] = sdev->child->next;
747 qe_devs[i]->base_addr = (long) qesdevs[i];
748
749 /* Link in channel 2. */
750 i = prom_getintdefault(sdev->child->next->next->prom_node, "channel#", -1);
751 if(i == -1) { res=ENODEV; goto qec_free_devs; }
752 qesdevs[i] = sdev->child->next->next;
753 qe_devs[i]->base_addr = (long) qesdevs[i];
754
755 /* Link in channel 3. */
756 i = prom_getintdefault(sdev->child->next->next->next->prom_node, "channel#", -1);
757 if(i == -1) { res=ENODEV; goto qec_free_devs; }
758 qesdevs[i] = sdev->child->next->next->next;
759 qe_devs[i]->base_addr = (long) qesdevs[i];
760
761 for(i = 0; i < 4; i++)
762 qeps[i]->qe_sbusdev = qesdevs[i];
763
764 /* This is a bit of fun, get QEC ranges. */
765 i = prom_getproperty(sdev->prom_node, "ranges",
766 (char *) &qranges[0], sizeof(qranges));
767 num_qranges = (i / sizeof(struct linux_prom_ranges));
768
769 /* Now, apply all the ranges, QEC ranges then the SBUS ones for each QE. */
770 if (sdev->ranges_applied == 0) {
771 for(i = 0; i < 4; i++) {
772 for(j = 0; j < 2; j++) {
773 int k;
774
775 for(k = 0; k < num_qranges; k++)
776 if(qesdevs[i]->reg_addrs[j].which_io ==
777 qranges[k].ot_child_space)
778 break;
779 if(k >= num_qranges)
780 printk("QuadEther: Aieee, bogus QEC range for "
781 "space %08x\n",qesdevs[i]->reg_addrs[j].which_io);
782 qesdevs[i]->reg_addrs[j].which_io = qranges[k].ot_parent_space;
783 qesdevs[i]->reg_addrs[j].phys_addr += qranges[k].ot_parent_base;
784 }
785
786 prom_apply_sbus_ranges(qesdevs[i]->my_bus, &qesdevs[i]->reg_addrs[0],
787 2, qesdevs[i]);
788 }
789 prom_apply_sbus_ranges(sdev->my_bus, &sdev->reg_addrs[0],
790 sdev->num_registers, sdev);
791 }
792
793 /* Now map in the registers, QEC globals first. */
794 qecp->gregs = sparc_alloc_io(sdev->reg_addrs[0].phys_addr, 0,
795 sizeof(struct qe_globreg),
796 "QEC Global Registers",
797 sdev->reg_addrs[0].which_io, 0);
798 if(!qecp->gregs) {
799 printk("QuadEther: Cannot map QEC global registers.\n");
800 res = ENODEV;
801 goto qec_free_devs;
802 }
803
804 /* Make sure the QEC is in MACE mode. */
805 if((qecp->gregs->ctrl & 0xf0000000) != GLOB_CTRL_MMODE) {
806 printk("QuadEther: AIEEE, QEC is not in MACE mode!\n");
807 res = ENODEV;
808 goto qec_free_devs;
809 }
810
811 /* Reset the QEC. */
812 if(qec_global_reset(qecp->gregs)) {
813 res = ENODEV;
814 goto qec_free_devs;
815 }
816
817 /* Find and set the burst sizes for the QEC, since it does
818 * the actual dma for all 4 channels.
819 */
820 bsizes = prom_getintdefault(sdev->prom_node, "burst-sizes", 0xff);
821 bsizes &= 0xff;
822 bsizes_more = prom_getintdefault(sdev->my_bus->prom_node, "burst-sizes", 0xff);
823
824 if(bsizes_more != 0xff)
825 bsizes &= bsizes_more;
826 if(bsizes == 0xff || (bsizes & DMA_BURST16) == 0 ||
827 (bsizes & DMA_BURST32)==0)
828 bsizes = (DMA_BURST32 - 1);
829
830 qecp->qec_bursts = bsizes;
831
832 /* Perform one time QEC initialization, we never touch the QEC
833 * globals again after this.
834 */
835 qec_init_once(qecp, sdev);
836
837 for(i = 0; i < 4; i++) {
838 /* Map in QEC per-channel control registers. */
839 qeps[i]->qcregs = sparc_alloc_io(qesdevs[i]->reg_addrs[0].phys_addr, 0,
840 sizeof(struct qe_creg),
841 "QEC Per-Channel Registers",
842 qesdevs[i]->reg_addrs[0].which_io, 0);
843 if(!qeps[i]->qcregs) {
844 printk("QuadEther: Cannot map QE %d's channel registers.\n", i);
845 res = ENODEV;
846 goto qec_free_devs;
847 }
848
849 /* Map in per-channel AMD MACE registers. */
850 qeps[i]->mregs = sparc_alloc_io(qesdevs[i]->reg_addrs[1].phys_addr, 0,
851 sizeof(struct qe_mregs),
852 "QE MACE Registers",
853 qesdevs[i]->reg_addrs[1].which_io, 0);
854 if(!qeps[i]->mregs) {
855 printk("QuadEther: Cannot map QE %d's MACE registers.\n", i);
856 res = ENODEV;
857 goto qec_free_devs;
858 }
859
860 qeps[i]->qe_block = (struct qe_init_block *)
861 sparc_dvma_malloc(PAGE_SIZE, "QE Init Block",
862 &qeps[i]->qblock_dvma);
863
864 qeps[i]->buffers = (struct sunqe_buffers *)
865 sparc_dvma_malloc(sizeof(struct sunqe_buffers),
866 "QE RX/TX Buffers",
867 &qeps[i]->buffers_dvma);
868
869 /* Stop this QE. */
870 qe_stop(qeps[i]);
871 }
872
873 for(i = 0; i < 4; i++) {
874 qe_devs[i]->open = qe_open;
875 qe_devs[i]->stop = qe_close;
876 qe_devs[i]->hard_start_xmit = qe_start_xmit;
877 qe_devs[i]->get_stats = qe_get_stats;
878 qe_devs[i]->set_multicast_list = qe_set_multicast;
879 qe_devs[i]->irq = sdev->irqs[0];
880 qe_devs[i]->dma = 0;
881 ether_setup(qe_devs[i]);
882 }
883
884 /* QEC receives interrupts from each QE, then it sends the actual
885 * IRQ to the cpu itself. Since QEC is the single point of
886 * interrupt for all QE channels we register the IRQ handler
887 * for it now.
888 */
889 if(request_irq(sdev->irqs[0], &qec_interrupt,
890 SA_SHIRQ, "QuadEther", (void *) qecp)) {
891 printk("QuadEther: Can't register QEC master irq handler.\n");
892 res = EAGAIN;
893 goto qec_free_devs;
894 }
895
896 /* Report the QE channels. */
897 for(i = 0; i < 4; i++) {
898 printk("%s: QuadEthernet channel[%d] ", qe_devs[i]->name, i);
899 for(j = 0; j < 6; j++)
900 printk ("%2.2x%c",
901 qe_devs[i]->dev_addr[j],
902 j == 5 ? ' ': ':');
903 printk("\n");
904 }
905
906 #ifdef MODULE
907 /* We are home free at this point, link the qe's into
908 * the master list for later module unloading.
909 */
910 for(i = 0; i < 4; i++)
911 qe_devs[i]->ifindex = dev_new_index();
912 qecp->next_module = root_qec_dev;
913 root_qec_dev = qecp;
914 #endif
915
916 return 0;
917
918 qec_free_devs:
919 for(i = 0; i < 4; i++) {
920 if(qe_devs[i]) {
921 if(qe_devs[i]->priv)
922 kfree(qe_devs[i]->priv);
923 kfree(qe_devs[i]);
924 }
925 }
926 return res;
927 }
928
929 int __init qec_probe(struct net_device *dev)
930 {
931 struct linux_sbus *bus;
932 struct linux_sbus_device *sdev = 0;
933 static int called = 0;
934 int cards = 0, v;
935
936 if(called)
937 return ENODEV;
938 called++;
939
940 for_each_sbus(bus) {
941 for_each_sbusdev(sdev, bus) {
942 if(cards) dev = NULL;
943
944 /* QEC can be parent of either QuadEthernet or BigMAC
945 * children.
946 */
947 if(!strcmp(sdev->prom_name, "qec") && sdev->child &&
948 !strcmp(sdev->child->prom_name, "qe") &&
949 sdev->child->next &&
950 !strcmp(sdev->child->next->prom_name, "qe") &&
951 sdev->child->next->next &&
952 !strcmp(sdev->child->next->next->prom_name, "qe") &&
953 sdev->child->next->next->next &&
954 !strcmp(sdev->child->next->next->next->prom_name, "qe")) {
955 cards++;
956 if((v = qec_ether_init(dev, sdev)))
957 return v;
958 }
959 }
960 }
961 if(!cards)
962 return ENODEV;
963 return 0;
964 }
965
966 #ifdef MODULE
967
968 int
969 init_module(void)
970 {
971 root_qec_dev = NULL;
972 return qec_probe(NULL);
973 }
974
975 void
976 cleanup_module(void)
977 {
978 struct sunqec *next_qec;
979 int i;
980
981 /* No need to check MOD_IN_USE, as sys_delete_module() checks. */
982 while (root_qec_dev) {
983 next_qec = root_qec_dev->next_module;
984
985 /* Release all four QE channels, then the QEC itself. */
986 for(i = 0; i < 4; i++) {
987 unregister_netdev(root_qec_dev->qes[i]->dev);
988 sparc_free_io(root_qec_dev->qes[i]->qcregs, sizeof(struct qe_creg));
989 sparc_free_io(root_qec_dev->qes[i]->mregs, sizeof(struct qe_mregs));
990 kfree(root_qec_dev->qes[i]->dev);
991 }
992 free_irq(root_qec_dev->qec_sbus_dev->irqs[0], (void *)root_qec_dev);
993 sparc_free_io(root_qec_dev->gregs, sizeof(struct qe_globreg));
994 kfree(root_qec_dev);
995 root_qec_dev = next_qec;
996 }
997 }
998
999 #endif /* MODULE */