i386/linux-2.3.21/include/asm-alpha/cache.h

   1 /*
   2  * include/asm-alpha/cache.h
   3  */
   4 #ifndef __ARCH_ALPHA_CACHE_H
   5 #define __ARCH_ALPHA_CACHE_H
   6
   7 /* Bytes per L1 (data) cache line.  Both EV4 and EV5 are write-through,
   8    read-allocate, direct-mapped, physical. */
   9 #define L1_CACHE_BYTES     32
  10 #define L1_CACHE_ALIGN(x)  (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
  11 #define SMP_CACHE_BYTES    L1_CACHE_BYTES
  12
  13 #define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
  14
  15 #endif