i386/linux-2.3.21/include/asm-m68k/dvma.h

   1 /* $Id: dvma.h,v 1.4 1999/03/27 20:23:41 tsbogend Exp $
   2  * include/asm-m68k/dma.h
   3  *
   4  * Copyright 1995 (C) David S. Miller (davem@caip.rutgers.edu)
   5  *
   6  * Hacked to fit Sun3x needs by Thomas Bogendoerfer
   7  */
   8
   9 #ifndef __M68K_DVMA_H
  10 #define __M68K_DVMA_H
  11
  12 #ifdef CONFIG_SUN3
  13 /* sun3 dvma page support */
  14
  15 /* memory and pmegs reserved for dvma */
  16 #define DVMA_PMEG_START 10
  17 #define DVMA_PMEG_END 16
  18 #define DVMA_START 0xff00000
  19 #define DVMA_END 0xffe0000
  20 #define DVMA_SIZE (DVMA_END-DVMA_START)
  21
  22 /* virt <-> phys conversions */
  23 #define sun3_dvma_vtop(x) ((unsigned long)(x) & 0xffffff)
  24 #define sun3_dvma_ptov(x) ((unsigned long)(x) | 0xf000000)
  25
  26 void *sun3_dvma_malloc(int len);
  27 #else /* Sun3x */
  28
  29 /* Structure to describe the current status of DMA registers on the Sparc */
  30 struct sparc_dma_registers {
  31   __volatile__ unsigned long cond_reg;  /* DMA condition register */
  32   __volatile__ unsigned long st_addr;   /* Start address of this transfer */
  33   __volatile__ unsigned long  cnt;      /* How many bytes to transfer */
  34   __volatile__ unsigned long dma_test;  /* DMA test register */
  35 };
  36
  37 /* DVMA chip revisions */
  38 enum dvma_rev {
  39         dvmarev0,
  40         dvmaesc1,
  41         dvmarev1,
  42         dvmarev2,
  43         dvmarev3,
  44         dvmarevplus,
  45         dvmahme
  46 };
  47
  48 #define DMA_HASCOUNT(rev)  ((rev)==dvmaesc1)
  49
  50 /* Linux DMA information structure, filled during probe. */
  51 struct Linux_SBus_DMA {
  52         struct Linux_SBus_DMA *next;
  53         struct linux_sbus_device *SBus_dev;
  54         struct sparc_dma_registers *regs;
  55
  56         /* Status, misc info */
  57         int node;                /* Prom node for this DMA device */
  58         int running;             /* Are we doing DMA now? */
  59         int allocated;           /* Are we "owned" by anyone yet? */
  60
  61         /* Transfer information. */
  62         unsigned long addr;      /* Start address of current transfer */
  63         int nbytes;              /* Size of current transfer */
  64         int realbytes;           /* For splitting up large transfers, etc. */
  65
  66         /* DMA revision */
  67         enum dvma_rev revision;
  68 };
  69
  70 extern struct Linux_SBus_DMA *dma_chain;
  71
  72 /* Broken hardware... */
  73 #define DMA_ISBROKEN(dma)    ((dma)->revision == dvmarev1)
  74 #define DMA_ISESC1(dma)      ((dma)->revision == dvmaesc1)
  75
  76 /* Fields in the cond_reg register */
  77 /* First, the version identification bits */
  78 #define DMA_DEVICE_ID    0xf0000000        /* Device identification bits */
  79 #define DMA_VERS0        0x00000000        /* Sunray DMA version */
  80 #define DMA_ESCV1        0x40000000        /* DMA ESC Version 1 */
  81 #define DMA_VERS1        0x80000000        /* DMA rev 1 */
  82 #define DMA_VERS2        0xa0000000        /* DMA rev 2 */
  83 #define DMA_VERHME       0xb0000000        /* DMA hme gate array */
  84 #define DMA_VERSPLUS     0x90000000        /* DMA rev 1 PLUS */
  85
  86 #define DMA_HNDL_INTR    0x00000001        /* An IRQ needs to be handled */
  87 #define DMA_HNDL_ERROR   0x00000002        /* We need to take an error */
  88 #define DMA_FIFO_ISDRAIN 0x0000000c        /* The DMA FIFO is draining */
  89 #define DMA_INT_ENAB     0x00000010        /* Turn on interrupts */
  90 #define DMA_FIFO_INV     0x00000020        /* Invalidate the FIFO */
  91 #define DMA_ACC_SZ_ERR   0x00000040        /* The access size was bad */
  92 #define DMA_FIFO_STDRAIN 0x00000040        /* DMA_VERS1 Drain the FIFO */
  93 #define DMA_RST_SCSI     0x00000080        /* Reset the SCSI controller */
  94 #define DMA_RST_ENET     DMA_RST_SCSI      /* Reset the ENET controller */
  95 #define DMA_ST_WRITE     0x00000100        /* write from device to memory */
  96 #define DMA_ENABLE       0x00000200        /* Fire up DMA, handle requests */
  97 #define DMA_PEND_READ    0x00000400        /* DMA_VERS1/0/PLUS Pending Read */
  98 #define DMA_ESC_BURST    0x00000800        /* 1=16byte 0=32byte */
  99 #define DMA_READ_AHEAD   0x00001800        /* DMA read ahead partial longword */
 100 #define DMA_DSBL_RD_DRN  0x00001000        /* No EC drain on slave reads */
 101 #define DMA_BCNT_ENAB    0x00002000        /* If on, use the byte counter */
 102 #define DMA_TERM_CNTR    0x00004000        /* Terminal counter */
 103 #define DMA_CSR_DISAB    0x00010000        /* No FIFO drains during csr */
 104 #define DMA_SCSI_DISAB   0x00020000        /* No FIFO drains during reg */
 105 #define DMA_DSBL_WR_INV  0x00020000        /* No EC inval. on slave writes */
 106 #define DMA_ADD_ENABLE   0x00040000        /* Special ESC DVMA optimization */
 107 #define DMA_E_BURST8     0x00040000        /* ENET: SBUS r/w burst size */
 108 #define DMA_BRST_SZ      0x000c0000        /* SCSI: SBUS r/w burst size */
 109 #define DMA_BRST64       0x00080000        /* SCSI: 64byte bursts (HME on UltraSparc only) */
 110 #define DMA_BRST32       0x00040000        /* SCSI: 32byte bursts */
 111 #define DMA_BRST16       0x00000000        /* SCSI: 16byte bursts */
 112 #define DMA_BRST0        0x00080000        /* SCSI: no bursts (non-HME gate arrays) */
 113 #define DMA_ADDR_DISAB   0x00100000        /* No FIFO drains during addr */
 114 #define DMA_2CLKS        0x00200000        /* Each transfer = 2 clock ticks */
 115 #define DMA_3CLKS        0x00400000        /* Each transfer = 3 clock ticks */
 116 #define DMA_EN_ENETAUI   DMA_3CLKS         /* Put lance into AUI-cable mode */
 117 #define DMA_CNTR_DISAB   0x00800000        /* No IRQ when DMA_TERM_CNTR set */
 118 #define DMA_AUTO_NADDR   0x01000000        /* Use "auto nxt addr" feature */
 119 #define DMA_SCSI_ON      0x02000000        /* Enable SCSI dma */
 120 #define DMA_PARITY_OFF   0x02000000        /* HME: disable parity checking */
 121 #define DMA_LOADED_ADDR  0x04000000        /* Address has been loaded */
 122 #define DMA_LOADED_NADDR 0x08000000        /* Next address has been loaded */
 123
 124 /* Values describing the burst-size property from the PROM */
 125 #define DMA_BURST1       0x01
 126 #define DMA_BURST2       0x02
 127 #define DMA_BURST4       0x04
 128 #define DMA_BURST8       0x08
 129 #define DMA_BURST16      0x10
 130 #define DMA_BURST32      0x20
 131 #define DMA_BURST64      0x40
 132 #define DMA_BURSTBITS    0x7f
 133
 134 /* Determine highest possible final transfer address given a base */
 135 #define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
 136
 137 /* Yes, I hack a lot of elisp in my spare time... */
 138 #define DMA_ERROR_P(regs)  ((((regs)->cond_reg) & DMA_HNDL_ERROR))
 139 #define DMA_IRQ_P(regs)    ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
 140 #define DMA_WRITE_P(regs)  ((((regs)->cond_reg) & DMA_ST_WRITE))
 141 #define DMA_OFF(regs)      ((((regs)->cond_reg) &= (~DMA_ENABLE)))
 142 #define DMA_INTSOFF(regs)  ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
 143 #define DMA_INTSON(regs)   ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
 144 #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
 145 #define DMA_SETSTART(regs, addr)  ((((regs)->st_addr) = (char *) addr))
 146 #define DMA_BEGINDMA_W(regs) \
 147         ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
 148 #define DMA_BEGINDMA_R(regs) \
 149         ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
 150
 151 /* For certain DMA chips, we need to disable ints upon irq entry
 152  * and turn them back on when we are done.  So in any ESP interrupt
 153  * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
 154  * when leaving the handler.  You have been warned...
 155  */
 156 #define DMA_IRQ_ENTRY(dma, dregs) do { \
 157         if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
 158    } while (0)
 159
 160 #define DMA_IRQ_EXIT(dma, dregs) do { \
 161         if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
 162    } while(0)
 163
 164 /* Reset the friggin' thing... */
 165 #define DMA_RESET(dma) do { \
 166         struct sparc_dma_registers *regs = dma->regs;                      \
 167         /* Let the current FIFO drain itself */                            \
 168         sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN));                         \
 169         /* Reset the logic */                                              \
 170         regs->cond_reg |= (DMA_RST_SCSI);     /* assert */                 \
 171         __delay(400);                         /* let the bits set ;) */    \
 172         regs->cond_reg &= ~(DMA_RST_SCSI);    /* de-assert */              \
 173         sparc_dma_enable_interrupts(regs);    /* Re-enable interrupts */   \
 174         /* Enable FAST transfers if available */                           \
 175         if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS;            \
 176         dma->running = 0;                                                  \
 177 } while(0)
 178
 179 extern unsigned long dvma_alloc (unsigned long, unsigned long);
 180 extern void dvma_free (unsigned long, unsigned long);
 181 #endif /* !CONFIG_SUN3 */
 182 #endif /* !(__M68K_DVMA_H) */