i386/linux-2.3.21/include/asm-sparc/irq.h

   1 /* $Id: irq.h,v 1.27 1999/08/14 03:52:02 anton Exp $
   2  * irq.h: IRQ registers on the Sparc.
   3  *
   4  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
   5  */
   6
   7 #ifndef _SPARC_IRQ_H
   8 #define _SPARC_IRQ_H
   9
  10 #include <linux/linkage.h>
  11 #include <linux/threads.h>     /* For NR_CPUS */
  12
  13 #include <asm/system.h>     /* For SUN4M_NCPUS */
  14 #include <asm/btfixup.h>
  15
  16 #define __irq_ino(irq) irq
  17 #define __irq_pil(irq) irq
  18 BTFIXUPDEF_CALL(char *, __irq_itoa, unsigned int)
  19 #define __irq_itoa(irq) BTFIXUP_CALL(__irq_itoa)(irq)
  20
  21 #define NR_IRQS    15
  22
  23 /* IRQ handler dispatch entry and exit. */
  24 #ifdef __SMP__
  25 extern unsigned int local_irq_count[NR_CPUS];
  26 #define irq_enter(cpu, irq)                     \
  27 do {    hardirq_enter(cpu);                     \
  28         spin_unlock_wait(&global_irq_lock);     \
  29         } while(0)
  30 #define irq_exit(cpu, irq)      hardirq_exit(cpu)
  31 #else
  32 extern unsigned int local_irq_count;
  33 #define irq_enter(cpu, irq)     (local_irq_count++)
  34 #define irq_exit(cpu, irq)      (local_irq_count--)
  35 #endif
  36
  37 /* Dave Redman (djhr@tadpole.co.uk)
  38  * changed these to function pointers.. it saves cycles and will allow
  39  * the irq dependencies to be split into different files at a later date
  40  * sun4c_irq.c, sun4m_irq.c etc so we could reduce the kernel size.
  41  * Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  42  * Changed these to btfixup entities... It saves cycles :)
  43  */
  44 BTFIXUPDEF_CALL(void, disable_irq, unsigned int)
  45 BTFIXUPDEF_CALL(void, enable_irq, unsigned int)
  46 BTFIXUPDEF_CALL(void, disable_pil_irq, unsigned int)
  47 BTFIXUPDEF_CALL(void, enable_pil_irq, unsigned int)
  48 BTFIXUPDEF_CALL(void, clear_clock_irq, void)
  49 BTFIXUPDEF_CALL(void, clear_profile_irq, int)
  50 BTFIXUPDEF_CALL(void, load_profile_irq, int, unsigned int)
  51
  52 #define disable_irq(irq) BTFIXUP_CALL(disable_irq)(irq)
  53 #define enable_irq(irq) BTFIXUP_CALL(enable_irq)(irq)
  54 #define disable_pil_irq(irq) BTFIXUP_CALL(disable_pil_irq)(irq)
  55 #define enable_pil_irq(irq) BTFIXUP_CALL(enable_pil_irq)(irq)
  56 #define clear_clock_irq() BTFIXUP_CALL(clear_clock_irq)()
  57 #define clear_profile_irq(cpu) BTFIXUP_CALL(clear_profile_irq)(cpu)
  58 #define load_profile_irq(cpu,limit) BTFIXUP_CALL(load_profile_irq)(cpu,limit)
  59
  60 extern void (*init_timers)(void (*lvl10_irq)(int, void *, struct pt_regs *));
  61 extern void claim_ticker14(void (*irq_handler)(int, void *, struct pt_regs *),
  62                            int irq,
  63                            unsigned int timeout);
  64
  65 #ifdef __SMP__
  66 BTFIXUPDEF_CALL(void, set_cpu_int, int, int)
  67 BTFIXUPDEF_CALL(void, clear_cpu_int, int, int)
  68 BTFIXUPDEF_CALL(void, set_irq_udt, int)
  69
  70 #define set_cpu_int(cpu,level) BTFIXUP_CALL(set_cpu_int)(cpu,level)
  71 #define clear_cpu_int(cpu,level) BTFIXUP_CALL(clear_cpu_int)(cpu,level)
  72 #define set_irq_udt(cpu) BTFIXUP_CALL(set_irq_udt)(cpu)
  73 #endif
  74
  75 extern int request_fast_irq(unsigned int irq, void (*handler)(int, void *, struct pt_regs *), unsigned long flags, __const__ char *devname);
  76
  77 /* On the sun4m, just like the timers, we have both per-cpu and master
  78  * interrupt registers.
  79  */
  80
  81 /* These registers are used for sending/receiving irqs from/to
  82  * different cpu's.
  83  */
  84 struct sun4m_intreg_percpu {
  85         unsigned int tbt;        /* Interrupts still pending for this cpu. */
  86
  87         /* These next two registers are WRITE-ONLY and are only
  88          * "on bit" sensitive, "off bits" written have NO affect.
  89          */
  90         unsigned int clear;  /* Clear this cpus irqs here. */
  91         unsigned int set;    /* Set this cpus irqs here. */
  92         unsigned char space[PAGE_SIZE - 12];
  93 };
  94
  95 /*
  96  * djhr
  97  * Actually the clear and set fields in this struct are misleading..
  98  * according to the SLAVIO manual (and the same applies for the SEC)
  99  * the clear field clears bits in the mask which will ENABLE that IRQ
 100  * the set field sets bits in the mask to DISABLE the IRQ.
 101  *
 102  * Also the undirected_xx address in the SLAVIO is defined as
 103  * RESERVED and write only..
 104  *
 105  * DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
 106  *             sun4m machines, for MP the layout makes more sense.
 107  */
 108 struct sun4m_intregs {
 109         struct sun4m_intreg_percpu cpu_intregs[SUN4M_NCPUS];
 110         unsigned int tbt;                /* IRQ's that are still pending. */
 111         unsigned int irqs;               /* Master IRQ bits. */
 112
 113         /* Again, like the above, two these registers are WRITE-ONLY. */
 114         unsigned int clear;              /* Clear master IRQ's by setting bits here. */
 115         unsigned int set;                /* Set master IRQ's by setting bits here. */
 116
 117         /* This register is both READ and WRITE. */
 118         unsigned int undirected_target;  /* Which cpu gets undirected irqs. */
 119 };
 120
 121 extern struct sun4m_intregs *sun4m_interrupts;
 122
 123 /*
 124  * Bit field defines for the interrupt registers on various
 125  * Sparc machines.
 126  */
 127
 128 /* The sun4c interrupt register. */
 129 #define SUN4C_INT_ENABLE  0x01     /* Allow interrupts. */
 130 #define SUN4C_INT_E14     0x80     /* Enable level 14 IRQ. */
 131 #define SUN4C_INT_E10     0x20     /* Enable level 10 IRQ. */
 132 #define SUN4C_INT_E8      0x10     /* Enable level 8 IRQ. */
 133 #define SUN4C_INT_E6      0x08     /* Enable level 6 IRQ. */
 134 #define SUN4C_INT_E4      0x04     /* Enable level 4 IRQ. */
 135 #define SUN4C_INT_E1      0x02     /* Enable level 1 IRQ. */
 136
 137 /* Dave Redman (djhr@tadpole.co.uk)
 138  * The sun4m interrupt registers.
 139  */
 140 #define SUN4M_INT_ENABLE        0x80000000
 141 #define SUN4M_INT_E14           0x00000080
 142 #define SUN4M_INT_E10           0x00080000
 143
 144 #define SUN4M_HARD_INT(x)       (0x000000001 << (x))
 145 #define SUN4M_SOFT_INT(x)       (0x000010000 << (x))
 146
 147 #define SUN4M_INT_MASKALL       0x80000000        /* mask all interrupts */
 148 #define SUN4M_INT_MODULE_ERR    0x40000000        /* module error */
 149 #define SUN4M_INT_M2S_WRITE     0x20000000        /* write buffer error */
 150 #define SUN4M_INT_ECC           0x10000000        /* ecc memory error */
 151 #define SUN4M_INT_FLOPPY        0x00400000        /* floppy disk */
 152 #define SUN4M_INT_MODULE        0x00200000        /* module interrupt */
 153 #define SUN4M_INT_VIDEO         0x00100000        /* onboard video */
 154 #define SUN4M_INT_REALTIME      0x00080000        /* system timer */
 155 #define SUN4M_INT_SCSI          0x00040000        /* onboard scsi */
 156 #define SUN4M_INT_AUDIO         0x00020000        /* audio/isdn */
 157 #define SUN4M_INT_ETHERNET      0x00010000        /* onboard ethernet */
 158 #define SUN4M_INT_SERIAL        0x00008000        /* serial ports */
 159 #define SUN4M_INT_KBDMS         0x00004000        /* keyboard/mouse */
 160 #define SUN4M_INT_SBUSBITS      0x00003F80        /* sbus int bits */
 161
 162 #define SUN4M_INT_SBUS(x)       (1 << (x+7))
 163 #define SUN4M_INT_VME(x)        (1 << (x))
 164
 165 #endif