i386/linux/linux-2.3.21/include/asm-ppc/softirq.h

   1 #ifndef __ASM_SOFTIRQ_H
   2 #define __ASM_SOFTIRQ_H
   3
   4 #include <asm/atomic.h>
   5 #include <asm/hardirq.h>
   6
   7 #define get_active_bhs()        (bh_mask & bh_active)
   8 #define clear_active_bhs(x)     atomic_clear_mask((x),&bh_active)
   9
  10 extern unsigned int ppc_local_bh_count[NR_CPUS];
  11
  12 extern inline void init_bh(int nr, void (*routine)(void))
  13 {
  14         bh_base[nr] = routine;
  15         atomic_set(&bh_mask_count[nr], 0);
  16         bh_mask |= 1 << nr;
  17 }
  18
  19 extern inline void remove_bh(int nr)
  20 {
  21         bh_mask &= ~(1 << nr);
  22         wmb();
  23         bh_base[nr] = 0;
  24 }
  25
  26 extern inline void mark_bh(int nr)
  27 {
  28         set_bit(nr, &bh_active);
  29 }
  30
  31 #ifdef __SMP__
  32
  33 /*
  34  * The locking mechanism for base handlers, to prevent re-entrancy,
  35  * is entirely private to an implementation, it should not be
  36  * referenced at all outside of this file.
  37  */
  38 extern atomic_t global_bh_lock;
  39 extern atomic_t global_bh_count;
  40
  41 extern void synchronize_bh(void);
  42
  43 static inline void start_bh_atomic(void)
  44 {
  45         atomic_inc(&global_bh_lock);
  46         synchronize_bh();
  47 }
  48
  49 static inline void end_bh_atomic(void)
  50 {
  51         atomic_dec(&global_bh_lock);
  52 }
  53
  54 /* These are for the IRQs testing the lock */
  55 static inline int softirq_trylock(int cpu)
  56 {
  57         if (ppc_local_bh_count[cpu] == 0) {
  58                 ppc_local_bh_count[cpu] = 1;
  59                 if (!test_and_set_bit(0,&global_bh_count)) {
  60                         mb();
  61                         if (atomic_read(&global_bh_lock) == 0)
  62                                 return 1;
  63                         clear_bit(0,&global_bh_count);
  64                 }
  65                 ppc_local_bh_count[cpu] = 0;
  66                 mb();
  67         }
  68         return 0;
  69 }
  70
  71 static inline void softirq_endlock(int cpu)
  72 {
  73         mb();
  74         ppc_local_bh_count[cpu]--;
  75         clear_bit(0,&global_bh_count);
  76 }
  77
  78 #else
  79
  80 extern inline void start_bh_atomic(void)
  81 {
  82         ppc_local_bh_count[smp_processor_id()]++;
  83         barrier();
  84 }
  85
  86 extern inline void end_bh_atomic(void)
  87 {
  88         barrier();
  89         ppc_local_bh_count[smp_processor_id()]--;
  90 }
  91
  92 /* These are for the irq's testing the lock */
  93 #define softirq_trylock(cpu)    (ppc_local_bh_count[cpu] ? 0 : (ppc_local_bh_count[cpu]=1))
  94 #define softirq_endlock(cpu)    (ppc_local_bh_count[cpu] = 0)
  95 #define synchronize_bh()        barrier()
  96
  97 #endif  /* SMP */
  98
  99 #define local_bh_disable()      (ppc_local_bh_count[smp_processor_id()]++)
 100 #define local_bh_enable()       (ppc_local_bh_count[smp_processor_id()]--)
 101
 102 /*
 103  * These use a mask count to correctly handle
 104  * nested disable/enable calls
 105  */
 106 extern inline void disable_bh(int nr)
 107 {
 108         bh_mask &= ~(1 << nr);
 109         atomic_inc(&bh_mask_count[nr]);
 110         synchronize_bh();
 111 }
 112
 113 extern inline void enable_bh(int nr)
 114 {
 115         if (atomic_dec_and_test(&bh_mask_count[nr]))
 116                 bh_mask |= 1 << nr;
 117 }
 118
 119 #endif  /* __ASM_SOFTIRQ_H */