i386/linux/linux-2.3.21/drivers/atm/horizon.h

   1 /*
   2   Madge Horizon ATM Adapter driver.
   3   Copyright (C) 1995-1999  Madge Networks Ltd.
   4
   5   This program is free software; you can redistribute it and/or modify
   6   it under the terms of the GNU General Public License as published by
   7   the Free Software Foundation; either version 2 of the License, or
   8   (at your option) any later version.
   9
  10   This program is distributed in the hope that it will be useful,
  11   but WITHOUT ANY WARRANTY; without even the implied warranty of
  12   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13   GNU General Public License for more details.
  14
  15   You should have received a copy of the GNU General Public License
  16   along with this program; if not, write to the Free Software
  17   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18
  19   The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian
  20   system and in the file COPYING in the Linux kernel source.
  21 */
  22
  23 /*
  24   IMPORTANT NOTE: Madge Networks no longer makes the adapters
  25   supported by this driver and makes no commitment to maintain it.
  26 */
  27
  28 /* too many macros - change to inline functions */
  29
  30 #ifndef DRIVER_ATM_HORIZON_H
  31 #define DRIVER_ATM_HORIZON_H
  32
  33 #include <linux/config.h>
  34
  35 #include <linux/version.h>
  36
  37
  38 #ifdef CONFIG_ATM_HORIZON_DEBUG
  39 #define DEBUG_HORIZON
  40 #endif
  41
  42 #define DEV_LABEL                         "hrz"
  43
  44 #ifndef PCI_VENDOR_ID_MADGE
  45 #define PCI_VENDOR_ID_MADGE               0x10B6
  46 #endif
  47 #ifndef PCI_DEVICE_ID_MADGE_HORIZON
  48 #define PCI_DEVICE_ID_MADGE_HORIZON       0x1000
  49 #endif
  50
  51 // diagnostic output
  52
  53 #define PRINTK(severity,format,args...) \
  54   printk(severity DEV_LABEL ": " format "\n" , ## args)
  55
  56 #ifdef DEBUG_HORIZON
  57
  58 #define DBG_ERR  0x0001
  59 #define DBG_WARN 0x0002
  60 #define DBG_INFO 0x0004
  61 #define DBG_VCC  0x0008
  62 #define DBG_QOS  0x0010
  63 #define DBG_TX   0x0020
  64 #define DBG_RX   0x0040
  65 #define DBG_SKB  0x0080
  66 #define DBG_IRQ  0x0100
  67 #define DBG_FLOW 0x0200
  68 #define DBG_BUS  0x0400
  69 #define DBG_REGS 0x0800
  70 #define DBG_DATA 0x1000
  71 #define DBG_MASK 0x1fff
  72
  73 /* the ## prevents the annoying double expansion of the macro arguments */
  74 /* KERN_INFO is used since KERN_DEBUG often does not make it to the console */
  75 #define PRINTDB(bits,format,args...) \
  76   ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format , ## args) : 1 )
  77 #define PRINTDM(bits,format,args...) \
  78   ( (debug & (bits)) ? printk (format , ## args) : 1 )
  79 #define PRINTDE(bits,format,args...) \
  80   ( (debug & (bits)) ? printk (format "\n" , ## args) : 1 )
  81 #define PRINTD(bits,format,args...) \
  82   ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format "\n" , ## args) : 1 )
  83
  84 #else
  85
  86 #define PRINTD(bits,format,args...)
  87 #define PRINTDB(bits,format,args...)
  88 #define PRINTDM(bits,format,args...)
  89 #define PRINTDE(bits,format,args...)
  90
  91 #endif
  92
  93 #define PRINTDD(sec,fmt,args...)
  94 #define PRINTDDB(sec,fmt,args...)
  95 #define PRINTDDM(sec,fmt,args...)
  96 #define PRINTDDE(sec,fmt,args...)
  97
  98 // fixed constants
  99
 100 #define SPARE_BUFFER_POOL_SIZE            MAX_VCS
 101 #define HRZ_MAX_VPI                       4
 102 #define MIN_PCI_LATENCY                   48 // 24 IS TOO SMALL
 103
 104 /*  Horizon specific bits */
 105 /*  Register offsets */
 106
 107 #define HRZ_IO_EXTENT                     0x80
 108
 109 #define DATA_PORT_OFF                     0x00
 110 #define TX_CHANNEL_PORT_OFF               0x04
 111 #define TX_DESCRIPTOR_PORT_OFF            0x08
 112 #define MEMORY_PORT_OFF                   0x0C
 113 #define MEM_WR_ADDR_REG_OFF               0x14
 114 #define MEM_RD_ADDR_REG_OFF               0x18
 115 #define CONTROL_0_REG                     0x1C
 116 #define INT_SOURCE_REG_OFF                0x20
 117 #define INT_ENABLE_REG_OFF                0x24
 118 #define MASTER_RX_ADDR_REG_OFF            0x28
 119 #define MASTER_RX_COUNT_REG_OFF           0x2C
 120 #define MASTER_TX_ADDR_REG_OFF            0x30
 121 #define MASTER_TX_COUNT_REG_OFF           0x34
 122 #define TX_DESCRIPTOR_REG_OFF             0x38
 123 #define TX_CHANNEL_CONFIG_COMMAND_OFF     0x40
 124 #define TX_CHANNEL_CONFIG_DATA_OFF        0x44
 125 #define TX_FREE_BUFFER_COUNT_OFF          0x48
 126 #define RX_FREE_BUFFER_COUNT_OFF          0x4C
 127 #define TX_CONFIG_OFF                     0x50
 128 #define TX_STATUS_OFF                     0x54
 129 #define RX_CONFIG_OFF                     0x58
 130 #define RX_LINE_CONFIG_OFF                0x5C
 131 #define RX_QUEUE_RD_PTR_OFF               0x60
 132 #define RX_QUEUE_WR_PTR_OFF               0x64
 133 #define MAX_AAL5_CELL_COUNT_OFF           0x68
 134 #define RX_CHANNEL_PORT_OFF               0x6C
 135 #define TX_CELL_COUNT_OFF                 0x70
 136 #define RX_CELL_COUNT_OFF                 0x74
 137 #define HEC_ERROR_COUNT_OFF               0x78
 138 #define UNASSIGNED_CELL_COUNT_OFF         0x7C
 139
 140 /*  Register bit definitions */
 141
 142 /* Control 0 register */
 143
 144 #define SEEPROM_DO                        0x00000001
 145 #define SEEPROM_DI                        0x00000002
 146 #define SEEPROM_SK                        0x00000004
 147 #define SEEPROM_CS                        0x00000008
 148 #define DEBUG_BIT_0                       0x00000010
 149 #define DEBUG_BIT_1                       0x00000020
 150 #define DEBUG_BIT_2                       0x00000040
 151 //      RESERVED                          0x00000080
 152 #define DEBUG_BIT_0_OE                    0x00000100
 153 #define DEBUG_BIT_1_OE                    0x00000200
 154 #define DEBUG_BIT_2_OE                    0x00000400
 155 //      RESERVED                          0x00000800
 156 #define DEBUG_BIT_0_STATE                 0x00001000
 157 #define DEBUG_BIT_1_STATE                 0x00002000
 158 #define DEBUG_BIT_2_STATE                 0x00004000
 159 //      RESERVED                          0x00008000
 160 #define GENERAL_BIT_0                     0x00010000
 161 #define GENERAL_BIT_1                     0x00020000
 162 #define GENERAL_BIT_2                     0x00040000
 163 #define GENERAL_BIT_3                     0x00080000
 164 #define RESET_HORIZON                     0x00100000
 165 #define RESET_ATM                         0x00200000
 166 #define RESET_RX                          0x00400000
 167 #define RESET_TX                          0x00800000
 168 #define RESET_HOST                        0x01000000
 169 //      RESERVED                          0x02000000
 170 #define TARGET_RETRY_DISABLE              0x04000000
 171 #define ATM_LAYER_SELECT                  0x08000000
 172 #define ATM_LAYER_STATUS                  0x10000000
 173 //      RESERVED                          0xE0000000
 174
 175 /* Interrupt source and enable registers */
 176
 177 #define RX_DATA_AV                        0x00000001
 178 #define RX_DISABLED                       0x00000002
 179 #define TIMING_MARKER                     0x00000004
 180 #define FORCED                            0x00000008
 181 #define RX_BUS_MASTER_COMPLETE            0x00000010
 182 #define TX_BUS_MASTER_COMPLETE            0x00000020
 183 #define ABR_TX_CELL_COUNT_INT             0x00000040
 184 #define DEBUG_INT                         0x00000080
 185 //      RESERVED                          0xFFFFFF00
 186
 187 /* PIO and Bus Mastering */
 188
 189 #define MAX_PIO_COUNT                     0x000000ff // 255 - make tunable?
 190 // 8188 is a hard limit for bus mastering
 191 #define MAX_TRANSFER_COUNT                0x00001ffc // 8188
 192 #define MASTER_TX_AUTO_APPEND_DESC        0x80000000
 193
 194 /* TX channel config command port */
 195
 196 #define PCR_TIMER_ACCESS                      0x0000
 197 #define SCR_TIMER_ACCESS                      0x0001
 198 #define BUCKET_CAPACITY_ACCESS                0x0002
 199 #define BUCKET_FULLNESS_ACCESS                0x0003
 200 #define RATE_TYPE_ACCESS                      0x0004
 201 //      UNUSED                                0x00F8
 202 #define TX_CHANNEL_CONFIG_MULT                0x0100
 203 //      UNUSED                                0xF800
 204 #define BUCKET_MAX_SIZE                       0x003f
 205
 206 /* TX channel config data port */
 207
 208 #define CLOCK_SELECT_SHIFT                    4
 209 #define CLOCK_DISABLE                         0x00ff
 210
 211 #define IDLE_RATE_TYPE                       0x0
 212 #define ABR_RATE_TYPE                        0x1
 213 #define VBR_RATE_TYPE                        0x2
 214 #define CBR_RATE_TYPE                        0x3
 215
 216 /* TX config register */
 217
 218 #define DRVR_DRVRBAR_ENABLE                   0x0001
 219 #define TXCLK_MUX_SELECT_RCLK                 0x0002
 220 #define TRANSMIT_TIMING_MARKER                0x0004
 221 #define LOOPBACK_TIMING_MARKER                0x0008
 222 #define TX_TEST_MODE_16MHz                    0x0000
 223 #define TX_TEST_MODE_8MHz                     0x0010
 224 #define TX_TEST_MODE_5_33MHz                  0x0020
 225 #define TX_TEST_MODE_4MHz                     0x0030
 226 #define TX_TEST_MODE_3_2MHz                   0x0040
 227 #define TX_TEST_MODE_2_66MHz                  0x0050
 228 #define TX_TEST_MODE_2_29MHz                  0x0060
 229 #define TX_NORMAL_OPERATION                   0x0070
 230 #define ABR_ROUND_ROBIN                       0x0080
 231
 232 /* TX status register */
 233
 234 #define IDLE_CHANNELS_MASK                    0x00FF
 235 #define ABR_CELL_COUNT_REACHED_MULT           0x0100
 236 #define ABR_CELL_COUNT_REACHED_MASK           0xFF
 237
 238 /* RX config register */
 239
 240 #define NON_USER_CELLS_IN_ONE_CHANNEL         0x0008
 241 #define RX_ENABLE                             0x0010
 242 #define IGNORE_UNUSED_VPI_VCI_BITS_SET        0x0000
 243 #define NON_USER_UNUSED_VPI_VCI_BITS_SET      0x0020
 244 #define DISCARD_UNUSED_VPI_VCI_BITS_SET       0x0040
 245
 246 /* RX line config register */
 247
 248 #define SIGNAL_LOSS                           0x0001
 249 #define FREQUENCY_DETECT_ERROR                0x0002
 250 #define LOCK_DETECT_ERROR                     0x0004
 251 #define SELECT_INTERNAL_LOOPBACK              0x0008
 252 #define LOCK_DETECT_ENABLE                    0x0010
 253 #define FREQUENCY_DETECT_ENABLE               0x0020
 254 #define USER_FRAQ                             0x0040
 255 #define GXTALOUT_SELECT_DIV4                  0x0080
 256 #define GXTALOUT_SELECT_NO_GATING             0x0100
 257 #define TIMING_MARKER_RECEIVED                0x0200
 258
 259 /* RX channel port */
 260
 261 #define RX_CHANNEL_MASK                       0x03FF
 262 // UNUSED                                     0x3C00
 263 #define FLUSH_CHANNEL                         0x4000
 264 #define RX_CHANNEL_UPDATE_IN_PROGRESS         0x8000
 265
 266 /* Receive queue entry */
 267
 268 #define RX_Q_ENTRY_LENGTH_MASK            0x0000FFFF
 269 #define RX_Q_ENTRY_CHANNEL_SHIFT          16
 270 #define SIMONS_DODGEY_MARKER              0x08000000
 271 #define RX_CONGESTION_EXPERIENCED         0x10000000
 272 #define RX_CRC_10_OK                      0x20000000
 273 #define RX_CRC_32_OK                      0x40000000
 274 #define RX_COMPLETE_FRAME                 0x80000000
 275
 276 /*  Offsets and constants for use with the buffer memory         */
 277
 278 /* Buffer pointers and channel types */
 279
 280 #define BUFFER_PTR_MASK                   0x0000FFFF
 281 #define RX_INT_THRESHOLD_MULT             0x00010000
 282 #define RX_INT_THRESHOLD_MASK             0x07FF
 283 #define INT_EVERY_N_CELLS                 0x08000000
 284 #define CONGESTION_EXPERIENCED            0x10000000
 285 #define FIRST_CELL_OF_AAL5_FRAME          0x20000000
 286 #define CHANNEL_TYPE_AAL5                 0x00000000
 287 #define CHANNEL_TYPE_RAW_CELLS            0x40000000
 288 #define CHANNEL_TYPE_AAL3_4               0x80000000
 289
 290 /* Buffer status stuff */
 291
 292 #define BUFF_STATUS_MASK                  0x00030000
 293 #define BUFF_STATUS_EMPTY                 0x00000000
 294 #define BUFF_STATUS_CELL_AV               0x00010000
 295 #define BUFF_STATUS_LAST_CELL_AV          0x00020000
 296
 297 /* Transmit channel stuff */
 298
 299 /* Receive channel stuff */
 300
 301 #define RX_CHANNEL_DISABLED               0x00000000
 302 #define RX_CHANNEL_IDLE                   0x00000001
 303
 304 /*  General things */
 305
 306 #define INITIAL_CRC                       0xFFFFFFFF
 307
 308 // A Horizon u32, a byte! Really nasty. Horizon pointers are (32 bit)
 309 // word addresses and so standard C pointer operations break (as they
 310 // assume byte addresses); so we pretend that Horizon words (and word
 311 // pointers) are bytes (and byte pointers) for the purposes of having
 312 // a memory map that works.
 313
 314 typedef u8 HDW;
 315
 316 typedef struct cell_buf {
 317   HDW payload[12];
 318   HDW next;
 319   HDW cell_count;               // AAL5 rx bufs
 320   HDW res;
 321   union {
 322     HDW partial_crc;            // AAL5 rx bufs
 323     HDW cell_header;            // RAW     bufs
 324   } u;
 325 } cell_buf;
 326
 327 typedef struct tx_ch_desc {
 328   HDW rd_buf_type;
 329   HDW wr_buf_type;
 330   HDW partial_crc;
 331   HDW cell_header;
 332 } tx_ch_desc;
 333
 334 typedef struct rx_ch_desc {
 335   HDW wr_buf_type;
 336   HDW rd_buf_type;
 337 } rx_ch_desc;
 338
 339 typedef struct rx_q_entry {
 340   HDW entry;
 341 } rx_q_entry;
 342
 343 #define TX_CHANS 8
 344 #define RX_CHANS 1024
 345 #define RX_QS 1024
 346 #define MAX_VCS RX_CHANS
 347
 348 /* Horizon buffer memory map */
 349
 350 // TX Channel Descriptors         2
 351 // TX Initial Buffers             8 // TX_CHANS
 352 #define BUFN1_SIZE              118 // (126 - TX_CHANS)
 353 //      RX/TX Start/End Buffers   4
 354 #define BUFN2_SIZE              124
 355 //      RX Queue Entries         64
 356 #define BUFN3_SIZE              192
 357 //      RX Channel Descriptors  128
 358 #define BUFN4_SIZE             1408
 359 //      TOTAL cell_buff chunks 2048
 360
 361 //    cell_buf             bufs[2048];
 362 //    HDW                  dws[32768];
 363
 364 typedef struct MEMMAP {
 365   tx_ch_desc  tx_descs[TX_CHANS];     //  8 *    4 =    32 , 0x0020
 366   cell_buf    inittxbufs[TX_CHANS];   // these are really
 367   cell_buf    bufn1[BUFN1_SIZE];      // part of this pool
 368   cell_buf    txfreebufstart;
 369   cell_buf    txfreebufend;
 370   cell_buf    rxfreebufstart;
 371   cell_buf    rxfreebufend;           // 8+118+1+1+1+1+124 = 254
 372   cell_buf    bufn2[BUFN2_SIZE];      // 16 *  254 =  4064 , 0x1000
 373   rx_q_entry  rx_q_entries[RX_QS];    //  1 * 1024 =  1024 , 0x1400
 374   cell_buf    bufn3[BUFN3_SIZE];      // 16 *  192 =  3072 , 0x2000
 375   rx_ch_desc  rx_descs[MAX_VCS];      //  2 * 1024 =  2048 , 0x2800
 376   cell_buf    bufn4[BUFN4_SIZE];      // 16 * 1408 = 22528 , 0x8000
 377 } MEMMAP;
 378
 379 #define memmap ((MEMMAP *)0)
 380
 381 /* end horizon specific bits */
 382
 383 typedef enum {
 384   aal0,
 385   aal34,
 386   aal5
 387 } hrz_aal;
 388
 389 typedef enum {
 390   tx_busy,
 391   rx_busy,
 392   ultra
 393 } hrz_flags;
 394
 395 // a single struct pointed to by atm_vcc->dev_data
 396
 397 typedef struct {
 398   unsigned int        tx_rate;
 399   unsigned int        rx_rate;
 400   u16                 channel;
 401   u16                 tx_xbr_bits;
 402   u16                 tx_pcr_bits;
 403 #if 0
 404   u16                 tx_scr_bits;
 405   u16                 tx_bucket_bits;
 406 #endif
 407   hrz_aal             aal;
 408 } hrz_vcc;
 409
 410 struct hrz_dev {
 411
 412   u32                 iobase;
 413   u32 *               membase;
 414
 415   struct sk_buff *    rx_skb;     // skb being RXed
 416   unsigned int        rx_bytes;   // bytes remaining to RX within region
 417   void *              rx_addr;    // addr to send bytes to (for PIO)
 418   unsigned int        rx_channel; // channel that the skb is going out on
 419
 420   struct sk_buff *    tx_skb;     // skb being TXed
 421   unsigned int        tx_bytes;   // bytes remaining to TX within region
 422   void *              tx_addr;    // addr to send bytes from (for PIO)
 423   struct iovec *      tx_iovec;   // remaining regions
 424   unsigned int        tx_regions; // number of remaining regions
 425
 426   spinlock_t          mem_lock;
 427 #if LINUX_VERSION_CODE >= 0x20303
 428   wait_queue_head_t   tx_queue;
 429 #else
 430   struct wait_queue * tx_queue;
 431 #endif
 432
 433   u8                  irq;
 434   u8                  flags;
 435   u8                  tx_last;
 436   u8                  tx_idle;
 437
 438   rx_q_entry *        rx_q_reset;
 439   rx_q_entry *        rx_q_entry;
 440   rx_q_entry *        rx_q_wrap;
 441
 442   struct atm_dev *    atm_dev;
 443
 444   u32                 last_vc;
 445
 446   int                 noof_spare_buffers;
 447   u16                 spare_buffers[SPARE_BUFFER_POOL_SIZE];
 448
 449   u16                 tx_channel_record[TX_CHANS];
 450
 451   // this is what we follow when we get incoming data
 452   u32              txer[MAX_VCS/32];
 453   struct atm_vcc * rxer[MAX_VCS];
 454
 455   // cell rate allocation
 456   spinlock_t       rate_lock;
 457   unsigned int     rx_avail;
 458   unsigned int     tx_avail;
 459
 460   // dev stats
 461   unsigned long    tx_cell_count;
 462   unsigned long    rx_cell_count;
 463   unsigned long    hec_error_count;
 464   unsigned long    unassigned_cell_count;
 465
 466   struct pci_dev * pci_dev;
 467   struct hrz_dev * prev;
 468 };
 469
 470 typedef struct hrz_dev hrz_dev;
 471
 472 /* macros for use later */
 473
 474 #define BUF_PTR(cbptr) ((cbptr) - (cell_buf *) 0)
 475
 476 #define INTERESTING_INTERRUPTS \
 477   (RX_DATA_AV | RX_DISABLED | TX_BUS_MASTER_COMPLETE | RX_BUS_MASTER_COMPLETE)
 478
 479 // 190 cells by default (192 TX buffers - 2 elbow room, see docs)
 480 #define TX_AAL5_LIMIT (190*ATM_CELL_PAYLOAD-ATM_AAL5_TRAILER) // 9112
 481
 482 // Have enough RX buffers (unless we allow other buffer splits)
 483 #define RX_AAL5_LIMIT ATM_MAX_AAL5_PDU
 484
 485 /* multi-statement macro protector */
 486 #define DW(x) do{ x } while(0)
 487
 488 #define HRZ_DEV(atm_dev) ((hrz_dev *) (atm_dev)->dev_data)
 489 #define HRZ_VCC(atm_vcc) ((hrz_vcc *) (atm_vcc)->dev_data)
 490
 491 /* Turn the LEDs on and off                                                 */
 492 // The LEDs bits are upside down in that setting the bit in the debug
 493 // register will turn the appropriate LED off.
 494
 495 #define YELLOW_LED    DEBUG_BIT_0
 496 #define GREEN_LED     DEBUG_BIT_1
 497 #define YELLOW_LED_OE DEBUG_BIT_0_OE
 498 #define GREEN_LED_OE  DEBUG_BIT_1_OE
 499
 500 #define GREEN_LED_OFF(dev)                      \
 501   wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | GREEN_LED)
 502 #define GREEN_LED_ON(dev)                       \
 503   wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ GREEN_LED)
 504 #define YELLOW_LED_OFF(dev)                     \
 505   wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | YELLOW_LED)
 506 #define YELLOW_LED_ON(dev)                      \
 507   wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ YELLOW_LED)
 508
 509 typedef enum {
 510   round_up,
 511   round_down,
 512   round_nearest
 513 } rounding;
 514
 515 #endif /* DRIVER_ATM_HORIZON_H */