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* added 0.99 linux version
[mascara-docs.git] / i386 / linux / linux-2.3.21 / drivers / net / de4x5.c
blobcd7d1c43c003ab3e57a80cc6e6d2074835ddf8e9
1 /* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
2 ethernet driver for Linux.
3
4 Copyright 1994, 1995 Digital Equipment Corporation.
5
6 Testing resources for this driver have been made available
7 in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
8
9 The author may be reached at davies@maniac.ultranet.com.
10
11 This program is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published by the
13 Free Software Foundation; either version 2 of the License, or (at your
14 option) any later version.
15
16 THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27 You should have received a copy of the GNU General Public License along
28 with this program; if not, write to the Free Software Foundation, Inc.,
29 675 Mass Ave, Cambridge, MA 02139, USA.
30
31 Originally, this driver was written for the Digital Equipment
32 Corporation series of EtherWORKS ethernet cards:
33
34 DE425 TP/COAX EISA
35 DE434 TP PCI
36 DE435 TP/COAX/AUI PCI
37 DE450 TP/COAX/AUI PCI
38 DE500 10/100 PCI Fasternet
39
40 but it will now attempt to support all cards which conform to the
41 Digital Semiconductor SROM Specification. The driver currently
42 recognises the following chips:
43
44 DC21040 (no SROM)
45 DC21041[A]
46 DC21140[A]
47 DC21142
48 DC21143
49
50 So far the driver is known to work with the following cards:
51
52 KINGSTON
53 Linksys
54 ZNYX342
55 SMC8432
56 SMC9332 (w/new SROM)
57 ZNYX31[45]
58 ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
59
60 The driver has been tested on a relatively busy network using the DE425,
61 DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
62 16M of data to a DECstation 5000/200 as follows:
63
64 TCP UDP
65 TX RX TX RX
66 DE425 1030k 997k 1170k 1128k
67 DE434 1063k 995k 1170k 1125k
68 DE435 1063k 995k 1170k 1125k
69 DE500 1063k 998k 1170k 1125k in 10Mb/s mode
70
71 All values are typical (in kBytes/sec) from a sample of 4 for each
72 measurement. Their error is +/-20k on a quiet (private) network and also
73 depend on what load the CPU has.
74
75 =========================================================================
76 This driver has been written substantially from scratch, although its
77 inheritance of style and stack interface from 'ewrk3.c' and in turn from
78 Donald Becker's 'lance.c' should be obvious. With the module autoload of
79 every usable DECchip board, I pinched Donald's 'next_module' field to
80 link my modules together.
81
82 Upto 15 EISA cards can be supported under this driver, limited primarily
83 by the available IRQ lines. I have checked different configurations of
84 multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
85 problem yet (provided you have at least depca.c v0.38) ...
86
87 PCI support has been added to allow the driver to work with the DE434,
88 DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
89 to the differences in the EISA and PCI CSR address offsets from the base
90 address.
91
92 The ability to load this driver as a loadable module has been included
93 and used extensively during the driver development (to save those long
94 reboot sequences). Loadable module support under PCI and EISA has been
95 achieved by letting the driver autoprobe as if it were compiled into the
96 kernel. Do make sure you're not sharing interrupts with anything that
97 cannot accommodate interrupt sharing!
98
99 To utilise this ability, you have to do 8 things:
100
101 0) have a copy of the loadable modules code installed on your system.
102 1) copy de4x5.c from the /linux/drivers/net directory to your favourite
103 temporary directory.
104 2) for fixed autoprobes (not recommended), edit the source code near
105 line 5594 to reflect the I/O address you're using, or assign these when
106 loading by:
107
108 insmod de4x5 io=0xghh where g = bus number
109 hh = device number
110
111 NB: autoprobing for modules is now supported by default. You may just
112 use:
113
114 insmod de4x5
115
116 to load all available boards. For a specific board, still use
117 the 'io=?' above.
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
119 that the correct bits are compiled (see end of source code).
120 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
121 kernel with the de4x5 configuration turned off and reboot.
122 5) insmod de4x5 [io=0xghh]
123 6) run the net startup bits for your new eth?? interface(s) manually
124 (usually /etc/rc.inet[12] at boot time).
125 7) enjoy!
126
127 To unload a module, turn off the associated interface(s)
128 'ifconfig eth?? down' then 'rmmod de4x5'.
129
130 Automedia detection is included so that in principal you can disconnect
131 from, e.g. TP, reconnect to BNC and things will still work (after a
132 pause whilst the driver figures out where its media went). My tests
133 using ping showed that it appears to work....
134
135 By default, the driver will now autodetect any DECchip based card.
136 Should you have a need to restrict the driver to DIGITAL only cards, you
137 can compile with a DEC_ONLY define, or if loading as a module, use the
138 'dec_only=1' parameter.
139
140 I've changed the timing routines to use the kernel timer and scheduling
141 functions so that the hangs and other assorted problems that occurred
142 while autosensing the media should be gone. A bonus for the DC21040
143 auto media sense algorithm is that it can now use one that is more in
144 line with the rest (the DC21040 chip doesn't have a hardware timer).
145 The downside is the 1 'jiffies' (10ms) resolution.
146
147 IEEE 802.3u MII interface code has been added in anticipation that some
148 products may use it in the future.
149
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
153
154 I have removed the buffer copies needed for receive on Intels. I cannot
155 remove them for Alphas since the Tulip hardware only does longword
156 aligned DMA transfers and the Alphas get alignment traps with non
157 longword aligned data copies (which makes them really slow). No comment.
158
159 I have added SROM decoding routines to make this driver work with any
160 card that supports the Digital Semiconductor SROM spec. This will help
161 all cards running the dc2114x series chips in particular. Cards using
162 the dc2104x chips should run correctly with the basic driver. I'm in
163 debt to <mjacob@feral.com> for the testing and feedback that helped get
164 this feature working. So far we have tested KINGSTON, SMC8432, SMC9332
165 (with the latest SROM complying with the SROM spec V3: their first was
166 broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315
167 (quad 21041 MAC) cards also appear to work despite their incorrectly
168 wired IRQs.
169
170 I have added a temporary fix for interrupt problems when some SCSI cards
171 share the same interrupt as the DECchip based cards. The problem occurs
172 because the SCSI card wants to grab the interrupt as a fast interrupt
173 (runs the service routine with interrupts turned off) vs. this card
174 which really needs to run the service routine with interrupts turned on.
175 This driver will now add the interrupt service routine as a fast
176 interrupt if it is bounced from the slow interrupt. THIS IS NOT A
177 RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time
178 until people sort out their compatibility issues and the kernel
179 interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST
180 INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181 run on the same interrupt. PCMCIA/CardBus is another can of worms...
182
183 Finally, I think I have really fixed the module loading problem with
184 more than one DECchip based card. As a side effect, I don't mess with
185 the device structure any more which means that if more than 1 card in
186 2.0.x is installed (4 in 2.1.x), the user will have to edit
187 linux/drivers/net/Space.c to make room for them. Hence, module loading
188 is the preferred way to use this driver, since it doesn't have this
189 limitation.
190
191 Where SROM media detection is used and full duplex is specified in the
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
193 time OR during a module load (insmod de4x5 args='eth??:fdx' [see
194 below]). This is because there is no way to automatically detect full
195 duplex links except through autonegotiation. When I include the
196 autonegotiation feature in the SROM autoconf code, this detection will
197 occur automatically for that case.
198
199 Command line arguments are now allowed, similar to passing arguments
200 through LILO. This will allow a per adapter board set up of full duplex
201 and media. The only lexical constraints are: the board name (dev->name)
202 appears in the list before its parameters. The list of parameters ends
203 either at the end of the parameter list or with another board name. The
204 following parameters are allowed:
205
206 fdx for full duplex
207 autosense to set the media/speed; with the following
208 sub-parameters:
209 TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
210
211 Case sensitivity is important for the sub-parameters. They *must* be
212 upper case. Examples:
213
214 insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
215
216 For a compiled in driver, at or above line 548, place e.g.
217 #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
218
219 Yes, I know full duplex isn't permissible on BNC or AUI; they're just
220 examples. By default, full duplex is turned off and AUTO is the default
221 autosense setting. In reality, I expect only the full duplex option to
222 be used. Note the use of single quotes in the two examples above and the
223 lack of commas to separate items. ALSO, you must get the requested media
224 correct in relation to what the adapter SROM says it has. There's no way
225 to determine this in advance other than by trial and error and common
226 sense, e.g. call a BNC connectored port 'BNC', not '10Mb'.
227
228 Changed the bus probing. EISA used to be done first, followed by PCI.
229 Most people probably don't even know what a de425 is today and the EISA
230 probe has messed up some SCSI cards in the past, so now PCI is always
231 probed first followed by EISA if a) the architecture allows EISA and
232 either b) there have been no PCI cards detected or c) an EISA probe is
233 forced by the user. To force a probe include "force_eisa" in your
234 insmod "args" line; for built-in kernels either change the driver to do
235 this automatically or include #define DE4X5_FORCE_EISA on or before
236 line 1040 in the driver.
237
238 TO DO:
239 ------
240
241 Revision History
242 ----------------
243
244 Version Date Description
245
246 0.1 17-Nov-94 Initial writing. ALPHA code release.
247 0.2 13-Jan-95 Added PCI support for DE435's.
248 0.21 19-Jan-95 Added auto media detection.
249 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>.
250 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
251 Add request/release_region code.
252 Add loadable modules support for PCI.
253 Clean up loadable modules support.
254 0.23 28-Feb-95 Added DC21041 and DC21140 support.
255 Fix missed frame counter value and initialisation.
256 Fixed EISA probe.
257 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
258 Change TX_BUFFS_AVAIL macro.
259 Change media autodetection to allow manual setting.
260 Completed DE500 (DC21140) support.
261 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
262 0.242 10-May-95 Minor changes.
263 0.30 12-Jun-95 Timer fix for DC21140.
264 Portability changes.
265 Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
266 Add DE500 semi automatic autosense.
267 Add Link Fail interrupt TP failure detection.
268 Add timer based link change detection.
269 Plugged a memory leak in de4x5_queue_pkt().
270 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
271 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
272 suggestion by <heiko@colossus.escape.de>.
273 0.33 8-Aug-95 Add shared interrupt support (not released yet).
274 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
275 Fix de4x5_interrupt().
276 Fix dc21140_autoconf() mess.
277 No shared interrupt support.
278 0.332 11-Sep-95 Added MII management interface routines.
279 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
280 Add kernel timer code (h/w is too flaky).
281 Add MII based PHY autosense.
282 Add new multicasting code.
283 Add new autosense algorithms for media/mode
284 selection using kernel scheduling/timing.
285 Re-formatted.
286 Made changes suggested by <jeff@router.patch.net>:
287 Change driver to detect all DECchip based cards
288 with DEC_ONLY restriction a special case.
289 Changed driver to autoprobe as a module. No irq
290 checking is done now - assume BIOS is good!
291 Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
292 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
293 only <niles@axp745gsfc.nasa.gov>
294 Fix for multiple PCI cards reported by <jos@xos.nl>
295 Duh, put the SA_SHIRQ flag into request_interrupt().
296 Fix SMC ethernet address in enet_det[].
297 Print chip name instead of "UNKNOWN" during boot.
298 0.42 26-Apr-96 Fix MII write TA bit error.
299 Fix bug in dc21040 and dc21041 autosense code.
300 Remove buffer copies on receive for Intels.
301 Change sk_buff handling during media disconnects to
302 eliminate DUP packets.
303 Add dynamic TX thresholding.
304 Change all chips to use perfect multicast filtering.
305 Fix alloc_device() bug <jari@markkus2.fimr.fi>
306 0.43 21-Jun-96 Fix unconnected media TX retry bug.
307 Add Accton to the list of broken cards.
308 Fix TX under-run bug for non DC21140 chips.
309 Fix boot command probe bug in alloc_device() as
310 reported by <koen.gadeyne@barco.com> and
311 <orava@nether.tky.hut.fi>.
312 Add cache locks to prevent a race condition as
313 reported by <csd@microplex.com> and
314 <baba@beckman.uiuc.edu>.
315 Upgraded alloc_device() code.
316 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
317 with <csd@microplex.com>
318 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
319 Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
320 and <michael@compurex.com>.
321 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
322 with a loopback packet.
323 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
324 by <bhat@mundook.cs.mu.OZ.AU>
325 0.45 8-Dec-96 Include endian functions for PPC use, from work
326 by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
327 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
328 suggestion from <mjacob@feral.com>.
329 0.5 30-Jan-97 Added SROM decoding functions.
330 Updated debug flags.
331 Fix sleep/wakeup calls for PCI cards, bug reported
332 by <cross@gweep.lkg.dec.com>.
333 Added multi-MAC, one SROM feature from discussion
334 with <mjacob@feral.com>.
335 Added full module autoprobe capability.
336 Added attempt to use an SMC9332 with broken SROM.
337 Added fix for ZYNX multi-mac cards that didn't
338 get their IRQs wired correctly.
339 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
340 <paubert@iram.es>
341 Fix init_connection() to remove extra device reset.
342 Fix MAC/PHY reset ordering in dc21140m_autoconf().
343 Fix initialisation problem with lp->timeout in
344 typeX_infoblock() from <paubert@iram.es>.
345 Fix MII PHY reset problem from work done by
346 <paubert@iram.es>.
347 0.52 26-Apr-97 Some changes may not credit the right people -
348 a disk crash meant I lost some mail.
349 Change RX interrupt routine to drop rather than
350 defer packets to avoid hang reported by
351 <g.thomas@opengroup.org>.
352 Fix srom_exec() to return for COMPACT and type 1
353 infoblocks.
354 Added DC21142 and DC21143 functions.
355 Added byte counters from <phil@tazenda.demon.co.uk>
356 Added SA_INTERRUPT temporary fix from
357 <mjacob@feral.com>.
358 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
359 module load: bug reported by
360 <Piete.Brooks@cl.cam.ac.uk>
361 Fix multi-MAC, one SROM, to work with 2114x chips:
362 bug reported by <cmetz@inner.net>.
363 Make above search independent of BIOS device scan
364 direction.
365 Completed DC2114[23] autosense functions.
366 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
367 <robin@intercore.com
368 Fix type1_infoblock() bug introduced in 0.53, from
369 problem reports by
370 <parmee@postecss.ncrfran.france.ncr.com> and
371 <jo@ice.dillingen.baynet.de>.
372 Added argument list to set up each board from either
373 a module's command line or a compiled in #define.
374 Added generic MII PHY functionality to deal with
375 newer PHY chips.
376 Fix the mess in 2.1.67.
377 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
378 <redhat@cococo.net>.
379 Fix bug in pci_probe() for 64 bit systems reported
380 by <belliott@accessone.com>.
381 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
382 0.534 24-Jan-98 Fix last (?) endian bug from <geert@linux-m68k.org>
383 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
384 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure.
385 **Incompatible with 2.0.x from here.**
386 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP
387 from <lma@varesearch.com>
388 Add TP, AUI and BNC cases to 21140m_autoconf() for
389 case where a 21140 under SROM control uses, e.g. AUI
390 from problem report by <delchini@lpnp09.in2p3.fr>
391 Add MII parallel detection to 2114x_autoconf() for
392 case where no autonegotiation partner exists from
393 problem report by <mlapsley@ndirect.co.uk>.
394 Add ability to force connection type directly even
395 when using SROM control from problem report by
396 <earl@exis.net>.
397 Updated the PCI interface to conform with the latest
398 version. I hope nothing is broken...
399 Add TX done interrupt modification from suggestion
400 by <Austin.Donnelly@cl.cam.ac.uk>.
401 Fix is_anc_capable() bug reported by
402 <Austin.Donnelly@cl.cam.ac.uk>.
403 Fix type[13]_infoblock() bug: during MII search, PHY
404 lp->rst not run because lp->ibn not initialised -
405 from report & fix by <paubert@iram.es>.
406 Fix probe bug with EISA & PCI cards present from
407 report by <eirik@netcom.com>.
408 0.541 24-Aug-98 Fix compiler problems associated with i386-string
409 ops from multiple bug reports and temporary fix
410 from <paubert@iram.es>.
411 Fix pci_probe() to correctly emulate the old
412 pcibios_find_class() function.
413 Add an_exception() for old ZYNX346 and fix compile
414 warning on PPC & SPARC, from <ecd@skynet.be>.
415 Fix lastPCI to correctly work with compiled in
416 kernels and modules from bug report by
417 <Zlatko.Calusic@CARNet.hr> et al.
418 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages
419 when media is unconnected.
420 Change dev->interrupt to lp->interrupt to ensure
421 alignment for Alpha's and avoid their unaligned
422 access traps. This flag is merely for log messages:
423 should do something more definitive though...
424 0.543 30-Dec-98 Add SMP spin locking.
425 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using
426 a 21143 by <mmporter@home.com>.
427 Change PCI/EISA bus probing order.
428
429 =========================================================================
430 */
431
432 static const char *version = "de4x5.c:V0.544 1999/5/8 davies@maniac.ultranet.com\n";
433
434 #include <linux/config.h>
435 #include <linux/module.h>
436
437 #include <linux/kernel.h>
438 #include <linux/sched.h>
439 #include <linux/string.h>
440 #include <linux/interrupt.h>
441 #include <linux/ptrace.h>
442 #include <linux/errno.h>
443 #include <linux/ioport.h>
444 #include <linux/malloc.h>
445 #include <linux/pci.h>
446 #include <linux/delay.h>
447 #include <linux/init.h>
448 #include <linux/version.h>
449 #include <linux/spinlock.h>
450
451 #include <asm/bitops.h>
452 #include <asm/io.h>
453 #include <asm/dma.h>
454 #include <asm/byteorder.h>
455 #include <asm/unaligned.h>
456 #include <asm/uaccess.h>
457
458 #include <linux/netdevice.h>
459 #include <linux/etherdevice.h>
460 #include <linux/skbuff.h>
461
462 #include <linux/time.h>
463 #include <linux/types.h>
464 #include <linux/unistd.h>
465 #include <linux/ctype.h>
466
467 #include "de4x5.h"
468
469 #define c_char const char
470 #define TWIDDLE(a) (u_short)le16_to_cpu(get_unaligned((u_short *)(a)))
471
472 /*
473 ** MII Information
474 */
475 struct phy_table {
476 int reset; /* Hard reset required? */
477 int id; /* IEEE OUI */
478 int ta; /* One cycle TA time - 802.3u is confusing here */
479 struct { /* Non autonegotiation (parallel) speed det. */
480 int reg;
481 int mask;
482 int value;
483 } spd;
484 };
485
486 struct mii_phy {
487 int reset; /* Hard reset required? */
488 int id; /* IEEE OUI */
489 int ta; /* One cycle TA time */
490 struct { /* Non autonegotiation (parallel) speed det. */
491 int reg;
492 int mask;
493 int value;
494 } spd;
495 int addr; /* MII address for the PHY */
496 u_char *gep; /* Start of GEP sequence block in SROM */
497 u_char *rst; /* Start of reset sequence in SROM */
498 u_int mc; /* Media Capabilities */
499 u_int ana; /* NWay Advertisement */
500 u_int fdx; /* Full DupleX capabilites for each media */
501 u_int ttm; /* Transmit Threshold Mode for each media */
502 u_int mci; /* 21142 MII Connector Interrupt info */
503 };
504
505 #define DE4X5_MAX_PHY 8 /* Allow upto 8 attached PHY devices per board */
506
507 struct sia_phy {
508 u_char mc; /* Media Code */
509 u_char ext; /* csr13-15 valid when set */
510 int csr13; /* SIA Connectivity Register */
511 int csr14; /* SIA TX/RX Register */
512 int csr15; /* SIA General Register */
513 int gepc; /* SIA GEP Control Information */
514 int gep; /* SIA GEP Data */
515 };
516
517 /*
518 ** Define the know universe of PHY devices that can be
519 ** recognised by this driver.
520 */
521 static struct phy_table phy_info[] = {
522 {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}}, /* National TX */
523 {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */
524 {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */
525 {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */
526 {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}} /* Level One LTX970 */
527 };
528
529 /*
530 ** These GENERIC values assumes that the PHY devices follow 802.3u and
531 ** allow parallel detection to set the link partner ability register.
532 ** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
533 */
534 #define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */
535 #define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */
536 #define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
537
538 /*
539 ** Define special SROM detection cases
540 */
541 static c_char enet_det[][ETH_ALEN] = {
542 {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
543 {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
544 };
545
546 #define SMC 1
547 #define ACCTON 2
548
549 /*
550 ** SROM Repair definitions. If a broken SROM is detected a card may
551 ** use this information to help figure out what to do. This is a
552 ** "stab in the dark" and so far for SMC9332's only.
553 */
554 static c_char srom_repair_info[][100] = {
555 {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */
556 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
557 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
558 0x00,0x18,}
559 };
560
561
562 #ifdef DE4X5_DEBUG
563 static int de4x5_debug = DE4X5_DEBUG;
564 #else
565 /*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
566 static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
567 #endif
568
569 /*
570 ** Allow per adapter set up. For modules this is simply a command line
571 ** parameter, e.g.:
572 ** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
573 **
574 ** For a compiled in driver, place e.g.
575 ** #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
576 ** here
577 */
578 #ifdef DE4X5_PARM
579 static char *args = DE4X5_PARM;
580 #else
581 static char *args = NULL;
582 #endif
583
584 struct parameters {
585 int fdx;
586 int autosense;
587 };
588
589 #define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */
590
591 #define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */
592
593 /*
594 ** Ethernet PROM defines
595 */
596 #define PROBE_LENGTH 32
597 #define ETH_PROM_SIG 0xAA5500FFUL
598
599 /*
600 ** Ethernet Info
601 */
602 #define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */
603 #define IEEE802_3_SZ 1518 /* Packet + CRC */
604 #define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */
605 #define MAX_DAT_SZ 1500 /* Maximum ethernet data length */
606 #define MIN_DAT_SZ 1 /* Minimum ethernet data length */
607 #define PKT_HDR_LEN 14 /* Addresses and data length info */
608 #define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
609 #define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */
610
611
612 #define CRC_POLYNOMIAL_BE 0x04c11db7UL /* Ethernet CRC, big endian */
613 #define CRC_POLYNOMIAL_LE 0xedb88320UL /* Ethernet CRC, little endian */
614
615 /*
616 ** EISA bus defines
617 */
618 #define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
619 #define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */
620
621 #define MAX_EISA_SLOTS 16
622 #define EISA_SLOT_INC 0x1000
623 #define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
624
625 #define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
626 #define DE4X5_NAME_LENGTH 8
627
628 /*
629 ** Ethernet PROM defines for DC21040
630 */
631 #define PROBE_LENGTH 32
632 #define ETH_PROM_SIG 0xAA5500FFUL
633
634 /*
635 ** PCI Bus defines
636 */
637 #define PCI_MAX_BUS_NUM 8
638 #define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */
639 #define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */
640 #define NO_MORE_PCI -2 /* PCI bus search all done */
641
642 /*
643 ** Memory Alignment. Each descriptor is 4 longwords long. To force a
644 ** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
645 ** DESC_ALIGN. ALIGN aligns the start address of the private memory area
646 ** and hence the RX descriptor ring's first entry.
647 */
648 #define ALIGN4 ((u_long)4 - 1) /* 1 longword align */
649 #define ALIGN8 ((u_long)8 - 1) /* 2 longword align */
650 #define ALIGN16 ((u_long)16 - 1) /* 4 longword align */
651 #define ALIGN32 ((u_long)32 - 1) /* 8 longword align */
652 #define ALIGN64 ((u_long)64 - 1) /* 16 longword align */
653 #define ALIGN128 ((u_long)128 - 1) /* 32 longword align */
654
655 #define ALIGN ALIGN32 /* Keep the DC21040 happy... */
656 #define CACHE_ALIGN CAL_16LONG
657 #define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */
658 /*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */
659 #define DESC_ALIGN
660
661 #ifndef DEC_ONLY /* See README.de4x5 for using this */
662 static int dec_only = 0;
663 #else
664 static int dec_only = 1;
665 #endif
666
667 /*
668 ** DE4X5 IRQ ENABLE/DISABLE
669 */
670 #define ENABLE_IRQs { \
671 imr |= lp->irq_en;\
672 outl(imr, DE4X5_IMR); /* Enable the IRQs */\
673 }
674
675 #define DISABLE_IRQs {\
676 imr = inl(DE4X5_IMR);\
677 imr &= ~lp->irq_en;\
678 outl(imr, DE4X5_IMR); /* Disable the IRQs */\
679 }
680
681 #define UNMASK_IRQs {\
682 imr |= lp->irq_mask;\
683 outl(imr, DE4X5_IMR); /* Unmask the IRQs */\
684 }
685
686 #define MASK_IRQs {\
687 imr = inl(DE4X5_IMR);\
688 imr &= ~lp->irq_mask;\
689 outl(imr, DE4X5_IMR); /* Mask the IRQs */\
690 }
691
692 /*
693 ** DE4X5 START/STOP
694 */
695 #define START_DE4X5 {\
696 omr = inl(DE4X5_OMR);\
697 omr |= OMR_ST | OMR_SR;\
698 outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
699 }
700
701 #define STOP_DE4X5 {\
702 omr = inl(DE4X5_OMR);\
703 omr &= ~(OMR_ST|OMR_SR);\
704 outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
705 }
706
707 /*
708 ** DE4X5 SIA RESET
709 */
710 #define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */
711
712 /*
713 ** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
714 */
715 #define DE4X5_AUTOSENSE_MS 250
716
717 /*
718 ** SROM Structure
719 */
720 struct de4x5_srom {
721 char sub_vendor_id[2];
722 char sub_system_id[2];
723 char reserved[12];
724 char id_block_crc;
725 char reserved2;
726 char version;
727 char num_controllers;
728 char ieee_addr[6];
729 char info[100];
730 short chksum;
731 };
732 #define SUB_VENDOR_ID 0x500a
733
734 /*
735 ** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
736 ** and have sizes of both a power of 2 and a multiple of 4.
737 ** A size of 256 bytes for each buffer could be chosen because over 90% of
738 ** all packets in our network are <256 bytes long and 64 longword alignment
739 ** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
740 ** descriptors are needed for machines with an ALPHA CPU.
741 */
742 #define NUM_RX_DESC 8 /* Number of RX descriptors */
743 #define NUM_TX_DESC 32 /* Number of TX descriptors */
744 #define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */
745 /* Multiple of 4 for DC21040 */
746 /* Allows 512 byte alignment */
747 struct de4x5_desc {
748 volatile s32 status;
749 u32 des1;
750 u32 buf;
751 u32 next;
752 DESC_ALIGN
753 };
754
755 /*
756 ** The DE4X5 private structure
757 */
758 #define DE4X5_PKT_STAT_SZ 16
759 #define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you
760 increase DE4X5_PKT_STAT_SZ */
761
762 struct de4x5_private {
763 char adapter_name[80]; /* Adapter name */
764 u_long interrupt; /* Aligned ISR flag */
765 struct de4x5_desc rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
766 struct de4x5_desc tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
767 struct sk_buff *tx_skb[NUM_TX_DESC]; /* TX skb for freeing when sent */
768 struct sk_buff *rx_skb[NUM_RX_DESC]; /* RX skb's */
769 int rx_new, rx_old; /* RX descriptor ring pointers */
770 int tx_new, tx_old; /* TX descriptor ring pointers */
771 char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */
772 char frame[64]; /* Min sized packet for loopback*/
773 spinlock_t lock; /* Adapter specific spinlock */
774 struct net_device_stats stats; /* Public stats */
775 struct {
776 u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */
777 u_int unicast;
778 u_int multicast;
779 u_int broadcast;
780 u_int excessive_collisions;
781 u_int tx_underruns;
782 u_int excessive_underruns;
783 u_int rx_runt_frames;
784 u_int rx_collision;
785 u_int rx_dribble;
786 u_int rx_overflow;
787 } pktStats;
788 char rxRingSize;
789 char txRingSize;
790 int bus; /* EISA or PCI */
791 int bus_num; /* PCI Bus number */
792 int device; /* Device number on PCI bus */
793 int state; /* Adapter OPENED or CLOSED */
794 int chipset; /* DC21040, DC21041 or DC21140 */
795 s32 irq_mask; /* Interrupt Mask (Enable) bits */
796 s32 irq_en; /* Summary interrupt bits */
797 int media; /* Media (eg TP), mode (eg 100B)*/
798 int c_media; /* Remember the last media conn */
799 int fdx; /* media full duplex flag */
800 int linkOK; /* Link is OK */
801 int autosense; /* Allow/disallow autosensing */
802 int tx_enable; /* Enable descriptor polling */
803 int setup_f; /* Setup frame filtering type */
804 int local_state; /* State within a 'media' state */
805 struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */
806 struct sia_phy sia; /* SIA PHY Information */
807 int active; /* Index to active PHY device */
808 int mii_cnt; /* Number of attached PHY's */
809 int timeout; /* Scheduling counter */
810 struct timer_list timer; /* Timer info for kernel */
811 int tmp; /* Temporary global per card */
812 struct {
813 void *priv; /* Original kmalloc'd mem addr */
814 void *buf; /* Original kmalloc'd mem addr */
815 u_long lock; /* Lock the cache accesses */
816 s32 csr0; /* Saved Bus Mode Register */
817 s32 csr6; /* Saved Operating Mode Reg. */
818 s32 csr7; /* Saved IRQ Mask Register */
819 s32 gep; /* Saved General Purpose Reg. */
820 s32 gepc; /* Control info for GEP */
821 s32 csr13; /* Saved SIA Connectivity Reg. */
822 s32 csr14; /* Saved SIA TX/RX Register */
823 s32 csr15; /* Saved SIA General Register */
824 int save_cnt; /* Flag if state already saved */
825 struct sk_buff *skb; /* Save the (re-ordered) skb's */
826 } cache;
827 struct de4x5_srom srom; /* A copy of the SROM */
828 struct net_device *next_module; /* Link to the next module */
829 int rx_ovf; /* Check for 'RX overflow' tag */
830 int useSROM; /* For non-DEC card use SROM */
831 int useMII; /* Infoblock using the MII */
832 int asBitValid; /* Autosense bits in GEP? */
833 int asPolarity; /* 0 => asserted high */
834 int asBit; /* Autosense bit number in GEP */
835 int defMedium; /* SROM default medium */
836 int tcount; /* Last infoblock number */
837 int infoblock_init; /* Initialised this infoblock? */
838 int infoleaf_offset; /* SROM infoleaf for controller */
839 s32 infoblock_csr6; /* csr6 value in SROM infoblock */
840 int infoblock_media; /* infoblock media */
841 int (*infoleaf_fn)(struct net_device *); /* Pointer to infoleaf function */
842 u_char *rst; /* Pointer to Type 5 reset info */
843 u_char ibn; /* Infoblock number */
844 struct parameters params; /* Command line/ #defined params */
845 };
846
847 /*
848 ** Kludge to get around the fact that the CSR addresses have different
849 ** offsets in the PCI and EISA boards. Also note that the ethernet address
850 ** PROM is accessed differently.
851 */
852 static struct bus_type {
853 int bus;
854 int bus_num;
855 int device;
856 int chipset;
857 struct de4x5_srom srom;
858 int autosense;
859 int useSROM;
860 } bus;
861
862 /*
863 ** To get around certain poxy cards that don't provide an SROM
864 ** for the second and more DECchip, I have to key off the first
865 ** chip's address. I'll assume there's not a bad SROM iff:
866 **
867 ** o the chipset is the same
868 ** o the bus number is the same and > 0
869 ** o the sum of all the returned hw address bytes is 0 or 0x5fa
870 **
871 ** Also have to save the irq for those cards whose hardware designers
872 ** can't follow the PCI to PCI Bridge Architecture spec.
873 */
874 static struct {
875 int chipset;
876 int bus;
877 int irq;
878 u_char addr[ETH_ALEN];
879 } last = {0,};
880
881 /*
882 ** The transmit ring full condition is described by the tx_old and tx_new
883 ** pointers by:
884 ** tx_old = tx_new Empty ring
885 ** tx_old = tx_new+1 Full ring
886 ** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition)
887 */
888 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
889 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
890 lp->tx_old -lp->tx_new-1)
891
892 #define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
893
894 /*
895 ** Public Functions
896 */
897 static int de4x5_open(struct net_device *dev);
898 static int de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev);
899 static void de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs);
900 static int de4x5_close(struct net_device *dev);
901 static struct net_device_stats *de4x5_get_stats(struct net_device *dev);
902 static void de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len);
903 static void set_multicast_list(struct net_device *dev);
904 static int de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
905
906 /*
907 ** Private functions
908 */
909 static int de4x5_hw_init(struct net_device *dev, u_long iobase);
910 static int de4x5_init(struct net_device *dev);
911 static int de4x5_sw_reset(struct net_device *dev);
912 static int de4x5_rx(struct net_device *dev);
913 static int de4x5_tx(struct net_device *dev);
914 static int de4x5_ast(struct net_device *dev);
915 static int de4x5_txur(struct net_device *dev);
916 static int de4x5_rx_ovfc(struct net_device *dev);
917
918 static int autoconf_media(struct net_device *dev);
919 static void create_packet(struct net_device *dev, char *frame, int len);
920 static void de4x5_us_delay(u32 usec);
921 static void de4x5_ms_delay(u32 msec);
922 static void load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb);
923 static int dc21040_autoconf(struct net_device *dev);
924 static int dc21041_autoconf(struct net_device *dev);
925 static int dc21140m_autoconf(struct net_device *dev);
926 static int dc2114x_autoconf(struct net_device *dev);
927 static int srom_autoconf(struct net_device *dev);
928 static int de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *));
929 static int dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int));
930 static int test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
931 static int test_for_100Mb(struct net_device *dev, int msec);
932 static int wait_for_link(struct net_device *dev);
933 static int test_mii_reg(struct net_device *dev, int reg, int mask, int pol, long msec);
934 static int is_spd_100(struct net_device *dev);
935 static int is_100_up(struct net_device *dev);
936 static int is_10_up(struct net_device *dev);
937 static int is_anc_capable(struct net_device *dev);
938 static int ping_media(struct net_device *dev, int msec);
939 static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len);
940 static void de4x5_free_rx_buffs(struct net_device *dev);
941 static void de4x5_free_tx_buffs(struct net_device *dev);
942 static void de4x5_save_skbs(struct net_device *dev);
943 static void de4x5_rst_desc_ring(struct net_device *dev);
944 static void de4x5_cache_state(struct net_device *dev, int flag);
945 static void de4x5_put_cache(struct net_device *dev, struct sk_buff *skb);
946 static void de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb);
947 static struct sk_buff *de4x5_get_cache(struct net_device *dev);
948 static void de4x5_setup_intr(struct net_device *dev);
949 static void de4x5_init_connection(struct net_device *dev);
950 static int de4x5_reset_phy(struct net_device *dev);
951 static void reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr);
952 static int test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec);
953 static int test_tp(struct net_device *dev, s32 msec);
954 static int EISA_signature(char *name, s32 eisa_id);
955 static int PCI_signature(char *name, struct bus_type *lp);
956 static void DevicePresent(u_long iobase);
957 static void enet_addr_rst(u_long aprom_addr);
958 static int de4x5_bad_srom(struct bus_type *lp);
959 static short srom_rd(u_long address, u_char offset);
960 static void srom_latch(u_int command, u_long address);
961 static void srom_command(u_int command, u_long address);
962 static void srom_address(u_int command, u_long address, u_char offset);
963 static short srom_data(u_int command, u_long address);
964 /*static void srom_busy(u_int command, u_long address);*/
965 static void sendto_srom(u_int command, u_long addr);
966 static int getfrom_srom(u_long addr);
967 static int srom_map_media(struct net_device *dev);
968 static int srom_infoleaf_info(struct net_device *dev);
969 static void srom_init(struct net_device *dev);
970 static void srom_exec(struct net_device *dev, u_char *p);
971 static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
972 static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
973 static int mii_rdata(u_long ioaddr);
974 static void mii_wdata(int data, int len, u_long ioaddr);
975 static void mii_ta(u_long rw, u_long ioaddr);
976 static int mii_swap(int data, int len);
977 static void mii_address(u_char addr, u_long ioaddr);
978 static void sendto_mii(u32 command, int data, u_long ioaddr);
979 static int getfrom_mii(u32 command, u_long ioaddr);
980 static int mii_get_oui(u_char phyaddr, u_long ioaddr);
981 static int mii_get_phy(struct net_device *dev);
982 static void SetMulticastFilter(struct net_device *dev);
983 static int get_hw_addr(struct net_device *dev);
984 static void srom_repair(struct net_device *dev, int card);
985 static int test_bad_enet(struct net_device *dev, int status);
986 static int an_exception(struct bus_type *lp);
987 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
988 static void eisa_probe(struct net_device *dev, u_long iobase);
989 #endif
990 static void pci_probe(struct net_device *dev, u_long iobase);
991 static void srom_search(struct pci_dev *pdev);
992 static char *build_setup_frame(struct net_device *dev, int mode);
993 static void disable_ast(struct net_device *dev);
994 static void enable_ast(struct net_device *dev, u32 time_out);
995 static long de4x5_switch_mac_port(struct net_device *dev);
996 static int gep_rd(struct net_device *dev);
997 static void gep_wr(s32 data, struct net_device *dev);
998 static void timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec);
999 static void yawn(struct net_device *dev, int state);
1000 static void link_modules(struct net_device *dev, struct net_device *tmp);
1001 static void de4x5_parse_params(struct net_device *dev);
1002 static void de4x5_dbg_open(struct net_device *dev);
1003 static void de4x5_dbg_mii(struct net_device *dev, int k);
1004 static void de4x5_dbg_media(struct net_device *dev);
1005 static void de4x5_dbg_srom(struct de4x5_srom *p);
1006 static void de4x5_dbg_rx(struct sk_buff *skb, int len);
1007 static int de4x5_strncmp(char *a, char *b, int n);
1008 static int dc21041_infoleaf(struct net_device *dev);
1009 static int dc21140_infoleaf(struct net_device *dev);
1010 static int dc21142_infoleaf(struct net_device *dev);
1011 static int dc21143_infoleaf(struct net_device *dev);
1012 static int type0_infoblock(struct net_device *dev, u_char count, u_char *p);
1013 static int type1_infoblock(struct net_device *dev, u_char count, u_char *p);
1014 static int type2_infoblock(struct net_device *dev, u_char count, u_char *p);
1015 static int type3_infoblock(struct net_device *dev, u_char count, u_char *p);
1016 static int type4_infoblock(struct net_device *dev, u_char count, u_char *p);
1017 static int type5_infoblock(struct net_device *dev, u_char count, u_char *p);
1018 static int compact_infoblock(struct net_device *dev, u_char count, u_char *p);
1019
1020 #ifdef MODULE
1021 int init_module(void);
1022 void cleanup_module(void);
1023 static struct net_device *unlink_modules(struct net_device *p);
1024 static struct net_device *insert_device(struct net_device *dev, u_long iobase,
1025 int (*init)(struct net_device *));
1026 static int count_adapters(void);
1027 static int loading_module = 1;
1028 MODULE_PARM(de4x5_debug, "i");
1029 MODULE_PARM(dec_only, "i");
1030 MODULE_PARM(args, "s");
1031 # else
1032 static int loading_module = 0;
1033 #endif /* MODULE */
1034
1035 static char name[DE4X5_NAME_LENGTH + 1];
1036 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
1037 static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
1038 static int lastEISA = 0;
1039 # ifdef DE4X5_FORCE_EISA /* Force an EISA bus probe or not */
1040 static int forceEISA = 1;
1041 # else
1042 static int forceEISA = 0;
1043 # endif
1044 #endif
1045 static int num_de4x5s = 0;
1046 static int cfrv = 0, useSROM = 0;
1047 static int lastPCI = -1;
1048 static struct net_device *lastModule = NULL;
1049 static struct pci_dev *pdev = NULL;
1050
1051 /*
1052 ** List the SROM infoleaf functions and chipsets
1053 */
1054 struct InfoLeaf {
1055 int chipset;
1056 int (*fn)(struct net_device *);
1057 };
1058 static struct InfoLeaf infoleaf_array[] = {
1059 {DC21041, dc21041_infoleaf},
1060 {DC21140, dc21140_infoleaf},
1061 {DC21142, dc21142_infoleaf},
1062 {DC21143, dc21143_infoleaf}
1063 };
1064 #define INFOLEAF_SIZE (sizeof(infoleaf_array)/(sizeof(int)+sizeof(int *)))
1065
1066 /*
1067 ** List the SROM info block functions
1068 */
1069 static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = {
1070 type0_infoblock,
1071 type1_infoblock,
1072 type2_infoblock,
1073 type3_infoblock,
1074 type4_infoblock,
1075 type5_infoblock,
1076 compact_infoblock
1077 };
1078
1079 #define COMPACT (sizeof(dc_infoblock)/sizeof(int *) - 1)
1080
1081 /*
1082 ** Miscellaneous defines...
1083 */
1084 #define RESET_DE4X5 {\
1085 int i;\
1086 i=inl(DE4X5_BMR);\
1087 de4x5_ms_delay(1);\
1088 outl(i | BMR_SWR, DE4X5_BMR);\
1089 de4x5_ms_delay(1);\
1090 outl(i, DE4X5_BMR);\
1091 de4x5_ms_delay(1);\
1092 for (i=0;i<5;i++) {inl(DE4X5_BMR); de4x5_ms_delay(1);}\
1093 de4x5_ms_delay(1);\
1094 }
1095
1096 #define PHY_HARD_RESET {\
1097 outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\
1098 mdelay(1); /* Assert for 1ms */\
1099 outl(0x00, DE4X5_GEP);\
1100 mdelay(2); /* Wait for 2ms */\
1101 }
1102
1103 \f
1104 /*
1105 ** Autoprobing in modules is allowed here. See the top of the file for
1106 ** more info.
1107 */
1108 int __init
1109 de4x5_probe(struct net_device *dev)
1110 {
1111 u_long iobase = dev->base_addr;
1112
1113 pci_probe(dev, iobase);
1114 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
1115 if ((lastPCI == NO_MORE_PCI) && ((num_de4x5s == 0) || forceEISA)) {
1116 eisa_probe(dev, iobase);
1117 }
1118 #endif
1119
1120 return (dev->priv ? 0 : -ENODEV);
1121 }
1122
1123 static int __init
1124 de4x5_hw_init(struct net_device *dev, u_long iobase)
1125 {
1126 struct bus_type *lp = &bus;
1127 int i, status=0;
1128 char *tmp;
1129
1130 /* Ensure we're not sleeping */
1131 if (lp->bus == EISA) {
1132 outb(WAKEUP, PCI_CFPM);
1133 } else {
1134 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
1135 PCI_CFDA_PSM, WAKEUP);
1136 }
1137 de4x5_ms_delay(10);
1138
1139 RESET_DE4X5;
1140
1141 if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1142 return -ENXIO; /* Hardware could not reset */
1143 }
1144
1145 /*
1146 ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1147 */
1148 useSROM = FALSE;
1149 if (lp->bus == PCI) {
1150 PCI_signature(name, lp);
1151 } else {
1152 EISA_signature(name, EISA_ID0);
1153 }
1154
1155 if (*name == '\0') { /* Not found a board signature */
1156 return -ENXIO;
1157 }
1158
1159 dev->base_addr = iobase;
1160 if (lp->bus == EISA) {
1161 printk("%s: %s at 0x%04lx (EISA slot %ld)",
1162 dev->name, name, iobase, ((iobase>>12)&0x0f));
1163 } else { /* PCI port address */
1164 printk("%s: %s at 0x%04lx (PCI bus %d, device %d)", dev->name, name,
1165 iobase, lp->bus_num, lp->device);
1166 }
1167
1168 printk(", h/w address ");
1169 status = get_hw_addr(dev);
1170 for (i = 0; i < ETH_ALEN - 1; i++) { /* get the ethernet addr. */
1171 printk("%2.2x:", dev->dev_addr[i]);
1172 }
1173 printk("%2.2x,\n", dev->dev_addr[i]);
1174
1175 if (status != 0) {
1176 printk(" which has an Ethernet PROM CRC error.\n");
1177 return -ENXIO;
1178 } else {
1179 struct de4x5_private *lp;
1180
1181 /*
1182 ** Reserve a section of kernel memory for the adapter
1183 ** private area and the TX/RX descriptor rings.
1184 */
1185 dev->priv = (void *) kmalloc(sizeof(struct de4x5_private) + ALIGN,
1186 GFP_KERNEL);
1187 if (dev->priv == NULL) {
1188 return -ENOMEM;
1189 }
1190
1191 /*
1192 ** Align to a longword boundary
1193 */
1194 tmp = dev->priv;
1195 dev->priv = (void *)(((u_long)dev->priv + ALIGN) & ~ALIGN);
1196 lp = (struct de4x5_private *)dev->priv;
1197 memset(dev->priv, 0, sizeof(struct de4x5_private));
1198 lp->bus = bus.bus;
1199 lp->bus_num = bus.bus_num;
1200 lp->device = bus.device;
1201 lp->chipset = bus.chipset;
1202 lp->cache.priv = tmp;
1203 lp->cache.gepc = GEP_INIT;
1204 lp->asBit = GEP_SLNK;
1205 lp->asPolarity = GEP_SLNK;
1206 lp->asBitValid = TRUE;
1207 lp->timeout = -1;
1208 lp->useSROM = useSROM;
1209 memcpy((char *)&lp->srom,(char *)&bus.srom,sizeof(struct de4x5_srom));
1210 lp->lock = (spinlock_t) SPIN_LOCK_UNLOCKED;
1211 de4x5_parse_params(dev);
1212
1213 /*
1214 ** Choose correct autosensing in case someone messed up
1215 */
1216 lp->autosense = lp->params.autosense;
1217 if (lp->chipset != DC21140) {
1218 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1219 lp->params.autosense = TP;
1220 }
1221 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1222 lp->params.autosense = BNC;
1223 }
1224 }
1225 lp->fdx = lp->params.fdx;
1226 sprintf(lp->adapter_name,"%s (%s)", name, dev->name);
1227
1228 /*
1229 ** Set up the RX descriptor ring (Intels)
1230 ** Allocate contiguous receive buffers, long word aligned (Alphas)
1231 */
1232 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
1233 for (i=0; i<NUM_RX_DESC; i++) {
1234 lp->rx_ring[i].status = 0;
1235 lp->rx_ring[i].des1 = RX_BUFF_SZ;
1236 lp->rx_ring[i].buf = 0;
1237 lp->rx_ring[i].next = 0;
1238 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1239 }
1240
1241 #else
1242 if ((tmp = (void *)kmalloc(RX_BUFF_SZ * NUM_RX_DESC + ALIGN,
1243 GFP_KERNEL)) == NULL) {
1244 kfree(lp->cache.priv);
1245 lp->cache.priv = NULL;
1246 return -ENOMEM;
1247 }
1248
1249 lp->cache.buf = tmp;
1250 tmp = (char *)(((u_long) tmp + ALIGN) & ~ALIGN);
1251 for (i=0; i<NUM_RX_DESC; i++) {
1252 lp->rx_ring[i].status = 0;
1253 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1254 lp->rx_ring[i].buf = cpu_to_le32(virt_to_bus(tmp+i*RX_BUFF_SZ));
1255 lp->rx_ring[i].next = 0;
1256 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1257 }
1258 #endif
1259
1260 barrier();
1261
1262 request_region(iobase, (lp->bus == PCI ? DE4X5_PCI_TOTAL_SIZE :
1263 DE4X5_EISA_TOTAL_SIZE),
1264 lp->adapter_name);
1265
1266 lp->rxRingSize = NUM_RX_DESC;
1267 lp->txRingSize = NUM_TX_DESC;
1268
1269 /* Write the end of list marker to the descriptor lists */
1270 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1271 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1272
1273 /* Tell the adapter where the TX/RX rings are located. */
1274 outl(virt_to_bus(lp->rx_ring), DE4X5_RRBA);
1275 outl(virt_to_bus(lp->tx_ring), DE4X5_TRBA);
1276
1277 /* Initialise the IRQ mask and Enable/Disable */
1278 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1279 lp->irq_en = IMR_NIM | IMR_AIM;
1280
1281 /* Create a loopback packet frame for later media probing */
1282 create_packet(dev, lp->frame, sizeof(lp->frame));
1283
1284 /* Check if the RX overflow bug needs testing for */
1285 i = cfrv & 0x000000fe;
1286 if ((lp->chipset == DC21140) && (i == 0x20)) {
1287 lp->rx_ovf = 1;
1288 }
1289
1290 /* Initialise the SROM pointers if possible */
1291 if (lp->useSROM) {
1292 lp->state = INITIALISED;
1293 if (srom_infoleaf_info(dev)) {
1294 return -ENXIO;
1295 }
1296 srom_init(dev);
1297 }
1298
1299 lp->state = CLOSED;
1300
1301 /*
1302 ** Check for an MII interface
1303 */
1304 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1305 mii_get_phy(dev);
1306 }
1307
1308 #ifndef __sparc_v9__
1309 printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
1310 #else
1311 printk(" and requires IRQ%x (provided by %s).\n", dev->irq,
1312 #endif
1313 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1314 }
1315
1316 if (de4x5_debug & DEBUG_VERSION) {
1317 printk(version);
1318 }
1319
1320 /* The DE4X5-specific entries in the device structure. */
1321 dev->open = &de4x5_open;
1322 dev->hard_start_xmit = &de4x5_queue_pkt;
1323 dev->stop = &de4x5_close;
1324 dev->get_stats = &de4x5_get_stats;
1325 dev->set_multicast_list = &set_multicast_list;
1326 dev->do_ioctl = &de4x5_ioctl;
1327
1328 dev->mem_start = 0;
1329
1330 /* Fill in the generic fields of the device structure. */
1331 ether_setup(dev);
1332
1333 /* Let the adapter sleep to save power */
1334 yawn(dev, SLEEP);
1335
1336 return status;
1337 }
1338
1339 \f
1340 static int
1341 de4x5_open(struct net_device *dev)
1342 {
1343 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1344 u_long iobase = dev->base_addr;
1345 int i, status = 0;
1346 s32 omr;
1347
1348 /* Allocate the RX buffers */
1349 for (i=0; i<lp->rxRingSize; i++) {
1350 if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1351 de4x5_free_rx_buffs(dev);
1352 return -EAGAIN;
1353 }
1354 }
1355
1356 /*
1357 ** Wake up the adapter
1358 */
1359 yawn(dev, WAKEUP);
1360
1361 /*
1362 ** Re-initialize the DE4X5...
1363 */
1364 status = de4x5_init(dev);
1365 lp->lock = (spinlock_t) SPIN_LOCK_UNLOCKED;
1366 lp->state = OPEN;
1367 de4x5_dbg_open(dev);
1368
1369 if (request_irq(dev->irq, (void *)de4x5_interrupt, SA_SHIRQ,
1370 lp->adapter_name, dev)) {
1371 printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1372 if (request_irq(dev->irq, de4x5_interrupt, SA_INTERRUPT | SA_SHIRQ,
1373 lp->adapter_name, dev)) {
1374 printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1375 disable_ast(dev);
1376 de4x5_free_rx_buffs(dev);
1377 de4x5_free_tx_buffs(dev);
1378 yawn(dev, SLEEP);
1379 lp->state = CLOSED;
1380 return -EAGAIN;
1381 } else {
1382 printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1383 printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1384 }
1385 }
1386
1387 dev->tbusy = 0;
1388 dev->start = 1;
1389 lp->interrupt = UNMASK_INTERRUPTS;
1390 dev->trans_start = jiffies;
1391
1392 START_DE4X5;
1393
1394 de4x5_setup_intr(dev);
1395
1396 if (de4x5_debug & DEBUG_OPEN) {
1397 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
1398 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
1399 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
1400 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
1401 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1402 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1403 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1404 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1405 }
1406
1407 MOD_INC_USE_COUNT;
1408
1409 return status;
1410 }
1411
1412 /*
1413 ** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1414 ** DC21140 requires using perfect filtering mode for that chip. Since I can't
1415 ** see why I'd want > 14 multicast addresses, I have changed all chips to use
1416 ** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1417 ** to be data corruption problems if it is larger (UDP errors seen from a
1418 ** ttcp source).
1419 */
1420 static int
1421 de4x5_init(struct net_device *dev)
1422 {
1423 /* Lock out other processes whilst setting up the hardware */
1424 test_and_set_bit(0, (void *)&dev->tbusy);
1425
1426 de4x5_sw_reset(dev);
1427
1428 /* Autoconfigure the connected port */
1429 autoconf_media(dev);
1430
1431 return 0;
1432 }
1433
1434 static int
1435 de4x5_sw_reset(struct net_device *dev)
1436 {
1437 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1438 u_long iobase = dev->base_addr;
1439 int i, j, status = 0;
1440 s32 bmr, omr;
1441
1442 /* Select the MII or SRL port now and RESET the MAC */
1443 if (!lp->useSROM) {
1444 if (lp->phy[lp->active].id != 0) {
1445 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1446 } else {
1447 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1448 }
1449 de4x5_switch_mac_port(dev);
1450 }
1451
1452 /*
1453 ** Set the programmable burst length to 8 longwords for all the DC21140
1454 ** Fasternet chips and 4 longwords for all others: DMA errors result
1455 ** without these values. Cache align 16 long.
1456 */
1457 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | CACHE_ALIGN;
1458 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1459 outl(bmr, DE4X5_BMR);
1460
1461 omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */
1462 if (lp->chipset == DC21140) {
1463 omr |= (OMR_SDP | OMR_SB);
1464 }
1465 lp->setup_f = PERFECT;
1466 outl(virt_to_bus(lp->rx_ring), DE4X5_RRBA);
1467 outl(virt_to_bus(lp->tx_ring), DE4X5_TRBA);
1468
1469 lp->rx_new = lp->rx_old = 0;
1470 lp->tx_new = lp->tx_old = 0;
1471
1472 for (i = 0; i < lp->rxRingSize; i++) {
1473 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1474 }
1475
1476 for (i = 0; i < lp->txRingSize; i++) {
1477 lp->tx_ring[i].status = cpu_to_le32(0);
1478 }
1479
1480 barrier();
1481
1482 /* Build the setup frame depending on filtering mode */
1483 SetMulticastFilter(dev);
1484
1485 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, NULL);
1486 outl(omr|OMR_ST, DE4X5_OMR);
1487
1488 /* Poll for setup frame completion (adapter interrupts are disabled now) */
1489 sti(); /* Ensure timer interrupts */
1490 for (j=0, i=0;(i<500) && (j==0);i++) { /* Upto 500ms delay */
1491 mdelay(1);
1492 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1493 }
1494 outl(omr, DE4X5_OMR); /* Stop everything! */
1495
1496 if (j == 0) {
1497 printk("%s: Setup frame timed out, status %08x\n", dev->name,
1498 inl(DE4X5_STS));
1499 status = -EIO;
1500 }
1501
1502 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1503 lp->tx_old = lp->tx_new;
1504
1505 return status;
1506 }
1507
1508 /*
1509 ** Writes a socket buffer address to the next available transmit descriptor.
1510 */
1511 static int
1512 de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1513 {
1514 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1515 u_long iobase = dev->base_addr;
1516 int status = 0;
1517 u_long flags = 0;
1518
1519 test_and_set_bit(0, (void*)&dev->tbusy); /* Stop send re-tries */
1520 if (lp->tx_enable == NO) { /* Cannot send for now */
1521 return -1;
1522 }
1523
1524 /*
1525 ** Clean out the TX ring asynchronously to interrupts - sometimes the
1526 ** interrupts are lost by delayed descriptor status updates relative to
1527 ** the irq assertion, especially with a busy PCI bus.
1528 */
1529 spin_lock_irqsave(&lp->lock, flags);
1530 de4x5_tx(dev);
1531 spin_unlock_irqrestore(&lp->lock, flags);
1532
1533 /* Test if cache is already locked - requeue skb if so */
1534 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1535 return -1;
1536
1537 /* Transmit descriptor ring full or stale skb */
1538 if (dev->tbusy || lp->tx_skb[lp->tx_new]) {
1539 if (lp->interrupt) {
1540 de4x5_putb_cache(dev, skb); /* Requeue the buffer */
1541 } else {
1542 de4x5_put_cache(dev, skb);
1543 }
1544 if (de4x5_debug & DEBUG_TX) {
1545 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%ld\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), dev->tbusy, inl(DE4X5_IMR), inl(DE4X5_OMR), (lp->tx_skb[lp->tx_new] ? "YES" : "NO"));
1546 }
1547 } else if (skb->len > 0) {
1548 /* If we already have stuff queued locally, use that first */
1549 if (lp->cache.skb && !lp->interrupt) {
1550 de4x5_put_cache(dev, skb);
1551 skb = de4x5_get_cache(dev);
1552 }
1553
1554 while (skb && !dev->tbusy && !lp->tx_skb[lp->tx_new]) {
1555 spin_lock_irqsave(&lp->lock, flags);
1556 test_and_set_bit(0, (void*)&dev->tbusy);
1557 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1558 lp->stats.tx_bytes += skb->len;
1559 outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
1560
1561 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1562 dev->trans_start = jiffies;
1563
1564 if (TX_BUFFS_AVAIL) {
1565 dev->tbusy = 0; /* Another pkt may be queued */
1566 }
1567 skb = de4x5_get_cache(dev);
1568 spin_unlock_irqrestore(&lp->lock, flags);
1569 }
1570 if (skb) de4x5_putb_cache(dev, skb);
1571 }
1572
1573 lp->cache.lock = 0;
1574
1575 return status;
1576 }
1577
1578 /*
1579 ** The DE4X5 interrupt handler.
1580 **
1581 ** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1582 ** so that the asserted interrupt always has some real data to work with -
1583 ** if these I/O accesses are ever changed to memory accesses, ensure the
1584 ** STS write is read immediately to complete the transaction if the adapter
1585 ** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1586 ** is high and descriptor status bits cannot be set before the associated
1587 ** interrupt is asserted and this routine entered.
1588 */
1589 static void
1590 de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1591 {
1592 struct net_device *dev = (struct net_device *)dev_id;
1593 struct de4x5_private *lp;
1594 s32 imr, omr, sts, limit;
1595 u_long iobase;
1596
1597 if (dev == NULL) {
1598 printk ("de4x5_interrupt(): irq %d for unknown device.\n", irq);
1599 return;
1600 }
1601 lp = (struct de4x5_private *)dev->priv;
1602 spin_lock(&lp->lock);
1603 iobase = dev->base_addr;
1604
1605 DISABLE_IRQs; /* Ensure non re-entrancy */
1606
1607 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1608 printk("%s: Re-entering the interrupt handler.\n", dev->name);
1609
1610 synchronize_irq();
1611
1612 for (limit=0; limit<8; limit++) {
1613 sts = inl(DE4X5_STS); /* Read IRQ status */
1614 outl(sts, DE4X5_STS); /* Reset the board interrupts */
1615
1616 if (!(sts & lp->irq_mask)) break;/* All done */
1617
1618 if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */
1619 de4x5_rx(dev);
1620
1621 if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */
1622 de4x5_tx(dev);
1623
1624 if (sts & STS_LNF) { /* TP Link has failed */
1625 lp->irq_mask &= ~IMR_LFM;
1626 }
1627
1628 if (sts & STS_UNF) { /* Transmit underrun */
1629 de4x5_txur(dev);
1630 }
1631
1632 if (sts & STS_SE) { /* Bus Error */
1633 STOP_DE4X5;
1634 printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1635 dev->name, sts);
1636 return;
1637 }
1638 }
1639
1640 /* Load the TX ring with any locally stored packets */
1641 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1642 while (lp->cache.skb && !dev->tbusy && lp->tx_enable) {
1643 de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1644 }
1645 lp->cache.lock = 0;
1646 }
1647
1648 lp->interrupt = UNMASK_INTERRUPTS;
1649 ENABLE_IRQs;
1650 spin_unlock(&lp->lock);
1651
1652 return;
1653 }
1654
1655 static int
1656 de4x5_rx(struct net_device *dev)
1657 {
1658 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1659 u_long iobase = dev->base_addr;
1660 int entry;
1661 s32 status;
1662
1663 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1664 entry=lp->rx_new) {
1665 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1666
1667 if (lp->rx_ovf) {
1668 if (inl(DE4X5_MFC) & MFC_FOCM) {
1669 de4x5_rx_ovfc(dev);
1670 break;
1671 }
1672 }
1673
1674 if (status & RD_FS) { /* Remember the start of frame */
1675 lp->rx_old = entry;
1676 }
1677
1678 if (status & RD_LS) { /* Valid frame status */
1679 if (lp->tx_enable) lp->linkOK++;
1680 if (status & RD_ES) { /* There was an error. */
1681 lp->stats.rx_errors++; /* Update the error stats. */
1682 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1683 if (status & RD_CE) lp->stats.rx_crc_errors++;
1684 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1685 if (status & RD_TL) lp->stats.rx_length_errors++;
1686 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1687 if (status & RD_CS) lp->pktStats.rx_collision++;
1688 if (status & RD_DB) lp->pktStats.rx_dribble++;
1689 if (status & RD_OF) lp->pktStats.rx_overflow++;
1690 } else { /* A valid frame received */
1691 struct sk_buff *skb;
1692 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1693 >> 16) - 4;
1694
1695 if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1696 printk("%s: Insufficient memory; nuking packet.\n",
1697 dev->name);
1698 lp->stats.rx_dropped++;
1699 } else {
1700 de4x5_dbg_rx(skb, pkt_len);
1701
1702 /* Push up the protocol stack */
1703 skb->protocol=eth_type_trans(skb,dev);
1704 netif_rx(skb);
1705
1706 /* Update stats */
1707 lp->stats.rx_packets++;
1708 lp->stats.rx_bytes += pkt_len;
1709 de4x5_local_stats(dev, skb->data, pkt_len);
1710 }
1711 }
1712
1713 /* Change buffer ownership for this frame, back to the adapter */
1714 for (;lp->rx_old!=entry;lp->rx_old=(++lp->rx_old)%lp->rxRingSize) {
1715 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1716 barrier();
1717 }
1718 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1719 barrier();
1720 }
1721
1722 /*
1723 ** Update entry information
1724 */
1725 lp->rx_new = (++lp->rx_new) % lp->rxRingSize;
1726 }
1727
1728 return 0;
1729 }
1730
1731 /*
1732 ** Buffer sent - check for TX buffer errors.
1733 */
1734 static int
1735 de4x5_tx(struct net_device *dev)
1736 {
1737 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1738 u_long iobase = dev->base_addr;
1739 int entry;
1740 s32 status;
1741
1742 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1743 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1744 if (status < 0) { /* Buffer not sent yet */
1745 break;
1746 } else if (status != 0x7fffffff) { /* Not setup frame */
1747 if (status & TD_ES) { /* An error happened */
1748 lp->stats.tx_errors++;
1749 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1750 if (status & TD_LC) lp->stats.tx_window_errors++;
1751 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1752 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1753 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1754
1755 if (TX_PKT_PENDING) {
1756 outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1757 }
1758 } else { /* Packet sent */
1759 lp->stats.tx_packets++;
1760 if (lp->tx_enable) lp->linkOK++;
1761 }
1762 /* Update the collision counter */
1763 lp->stats.collisions += ((status & TD_EC) ? 16 :
1764 ((status & TD_CC) >> 3));
1765
1766 /* Free the buffer. */
1767 if (lp->tx_skb[entry] != NULL) {
1768 dev_kfree_skb(lp->tx_skb[entry]);
1769 lp->tx_skb[entry] = NULL;
1770 }
1771 }
1772
1773 /* Update all the pointers */
1774 lp->tx_old = (++lp->tx_old) % lp->txRingSize;
1775 }
1776
1777 if (TX_BUFFS_AVAIL && dev->tbusy) { /* Any resources available? */
1778 dev->tbusy = 0; /* Clear TX busy flag */
1779 if (lp->interrupt) mark_bh(NET_BH);
1780 }
1781
1782 return 0;
1783 }
1784
1785 static int
1786 de4x5_ast(struct net_device *dev)
1787 {
1788 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1789 int next_tick = DE4X5_AUTOSENSE_MS;
1790
1791 disable_ast(dev);
1792
1793 if (lp->useSROM) {
1794 next_tick = srom_autoconf(dev);
1795 } else if (lp->chipset == DC21140) {
1796 next_tick = dc21140m_autoconf(dev);
1797 } else if (lp->chipset == DC21041) {
1798 next_tick = dc21041_autoconf(dev);
1799 } else if (lp->chipset == DC21040) {
1800 next_tick = dc21040_autoconf(dev);
1801 }
1802 lp->linkOK = 0;
1803 enable_ast(dev, next_tick);
1804
1805 return 0;
1806 }
1807
1808 static int
1809 de4x5_txur(struct net_device *dev)
1810 {
1811 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1812 u_long iobase = dev->base_addr;
1813 int omr;
1814
1815 omr = inl(DE4X5_OMR);
1816 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1817 omr &= ~(OMR_ST|OMR_SR);
1818 outl(omr, DE4X5_OMR);
1819 while (inl(DE4X5_STS) & STS_TS);
1820 if ((omr & OMR_TR) < OMR_TR) {
1821 omr += 0x4000;
1822 } else {
1823 omr |= OMR_SF;
1824 }
1825 outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1826 }
1827
1828 return 0;
1829 }
1830
1831 static int
1832 de4x5_rx_ovfc(struct net_device *dev)
1833 {
1834 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1835 u_long iobase = dev->base_addr;
1836 int omr;
1837
1838 omr = inl(DE4X5_OMR);
1839 outl(omr & ~OMR_SR, DE4X5_OMR);
1840 while (inl(DE4X5_STS) & STS_RS);
1841
1842 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1843 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1844 lp->rx_new = (++lp->rx_new % lp->rxRingSize);
1845 }
1846
1847 outl(omr, DE4X5_OMR);
1848
1849 return 0;
1850 }
1851
1852 static int
1853 de4x5_close(struct net_device *dev)
1854 {
1855 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1856 u_long iobase = dev->base_addr;
1857 s32 imr, omr;
1858
1859 disable_ast(dev);
1860 dev->start = 0;
1861 dev->tbusy = 1;
1862
1863 if (de4x5_debug & DEBUG_CLOSE) {
1864 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1865 dev->name, inl(DE4X5_STS));
1866 }
1867
1868 /*
1869 ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1870 */
1871 DISABLE_IRQs;
1872 STOP_DE4X5;
1873
1874 /* Free the associated irq */
1875 free_irq(dev->irq, dev);
1876 lp->state = CLOSED;
1877
1878 /* Free any socket buffers */
1879 de4x5_free_rx_buffs(dev);
1880 de4x5_free_tx_buffs(dev);
1881
1882 MOD_DEC_USE_COUNT;
1883
1884 /* Put the adapter to sleep to save power */
1885 yawn(dev, SLEEP);
1886
1887 return 0;
1888 }
1889
1890 static struct net_device_stats *
1891 de4x5_get_stats(struct net_device *dev)
1892 {
1893 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1894 u_long iobase = dev->base_addr;
1895
1896 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1897
1898 return &lp->stats;
1899 }
1900
1901 static void
1902 de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len)
1903 {
1904 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1905 int i;
1906
1907 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1908 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1909 lp->pktStats.bins[i]++;
1910 i = DE4X5_PKT_STAT_SZ;
1911 }
1912 }
1913 if (buf[0] & 0x01) { /* Multicast/Broadcast */
1914 if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) {
1915 lp->pktStats.broadcast++;
1916 } else {
1917 lp->pktStats.multicast++;
1918 }
1919 } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) &&
1920 (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) {
1921 lp->pktStats.unicast++;
1922 }
1923
1924 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1925 if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1926 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1927 }
1928
1929 return;
1930 }
1931
1932 /*
1933 ** Removes the TD_IC flag from previous descriptor to improve TX performance.
1934 ** If the flag is changed on a descriptor that is being read by the hardware,
1935 ** I assume PCI transaction ordering will mean you are either successful or
1936 ** just miss asserting the change to the hardware. Anyway you're messing with
1937 ** a descriptor you don't own, but this shouldn't kill the chip provided
1938 ** the descriptor register is read only to the hardware.
1939 */
1940 static void
1941 load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb)
1942 {
1943 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1944 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1945
1946 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(virt_to_bus(buf));
1947 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1948 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1949 lp->tx_skb[lp->tx_new] = skb;
1950 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1951 barrier();
1952
1953 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1954 barrier();
1955
1956 return;
1957 }
1958
1959 /*
1960 ** Set or clear the multicast filter for this adaptor.
1961 */
1962 static void
1963 set_multicast_list(struct net_device *dev)
1964 {
1965 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1966 u_long iobase = dev->base_addr;
1967
1968 /* First, double check that the adapter is open */
1969 if (lp->state == OPEN) {
1970 if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
1971 u32 omr;
1972 omr = inl(DE4X5_OMR);
1973 omr |= OMR_PR;
1974 outl(omr, DE4X5_OMR);
1975 } else {
1976 SetMulticastFilter(dev);
1977 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1978 SETUP_FRAME_LEN, NULL);
1979
1980 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1981 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
1982 dev->trans_start = jiffies;
1983 }
1984 }
1985
1986 return;
1987 }
1988
1989 /*
1990 ** Calculate the hash code and update the logical address filter
1991 ** from a list of ethernet multicast addresses.
1992 ** Little endian crc one liner from Matt Thomas, DEC.
1993 */
1994 static void
1995 SetMulticastFilter(struct net_device *dev)
1996 {
1997 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1998 struct dev_mc_list *dmi=dev->mc_list;
1999 u_long iobase = dev->base_addr;
2000 int i, j, bit, byte;
2001 u16 hashcode;
2002 u32 omr, crc, poly = CRC_POLYNOMIAL_LE;
2003 char *pa;
2004 unsigned char *addrs;
2005
2006 omr = inl(DE4X5_OMR);
2007 omr &= ~(OMR_PR | OMR_PM);
2008 pa = build_setup_frame(dev, ALL); /* Build the basic frame */
2009
2010 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 14)) {
2011 omr |= OMR_PM; /* Pass all multicasts */
2012 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
2013 for (i=0;i<dev->mc_count;i++) { /* for each address in the list */
2014 addrs=dmi->dmi_addr;
2015 dmi=dmi->next;
2016 if ((*addrs & 0x01) == 1) { /* multicast address? */
2017 crc = 0xffffffff; /* init CRC for each address */
2018 for (byte=0;byte<ETH_ALEN;byte++) {/* for each address byte */
2019 /* process each address bit */
2020 for (bit = *addrs++,j=0;j<8;j++, bit>>=1) {
2021 crc = (crc >> 1) ^ (((crc ^ bit) & 0x01) ? poly : 0);
2022 }
2023 }
2024 hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */
2025
2026 byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
2027 bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
2028
2029 byte <<= 1; /* calc offset into setup frame */
2030 if (byte & 0x02) {
2031 byte -= 1;
2032 }
2033 lp->setup_frame[byte] |= bit;
2034 }
2035 }
2036 } else { /* Perfect filtering */
2037 for (j=0; j<dev->mc_count; j++) {
2038 addrs=dmi->dmi_addr;
2039 dmi=dmi->next;
2040 for (i=0; i<ETH_ALEN; i++) {
2041 *(pa + (i&1)) = *addrs++;
2042 if (i & 0x01) pa += 4;
2043 }
2044 }
2045 }
2046 outl(omr, DE4X5_OMR);
2047
2048 return;
2049 }
2050
2051 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
2052 /*
2053 ** EISA bus I/O device probe. Probe from slot 1 since slot 0 is usually
2054 ** the motherboard. Upto 15 EISA devices are supported.
2055 */
2056 static void __init
2057 eisa_probe(struct net_device *dev, u_long ioaddr)
2058 {
2059 int i, maxSlots, status, device;
2060 u_char irq;
2061 u_short vendor;
2062 u32 cfid;
2063 u_long iobase;
2064 struct bus_type *lp = &bus;
2065 char name[DE4X5_STRLEN];
2066
2067 if (lastEISA == MAX_EISA_SLOTS) return;/* No more EISA devices to search */
2068
2069 lp->bus = EISA;
2070
2071 if (ioaddr == 0) { /* Autoprobing */
2072 iobase = EISA_SLOT_INC; /* Get the first slot address */
2073 i = 1;
2074 maxSlots = MAX_EISA_SLOTS;
2075 } else { /* Probe a specific location */
2076 iobase = ioaddr;
2077 i = (ioaddr >> 12);
2078 maxSlots = i + 1;
2079 }
2080
2081 for (status = -ENODEV; (i<maxSlots) && (dev!=NULL); i++, iobase+=EISA_SLOT_INC) {
2082 if (check_region(iobase, DE4X5_EISA_TOTAL_SIZE)) continue;
2083 if (!EISA_signature(name, EISA_ID)) continue;
2084
2085 cfid = (u32) inl(PCI_CFID);
2086 cfrv = (u_short) inl(PCI_CFRV);
2087 device = (cfid >> 8) & 0x00ffff00;
2088 vendor = (u_short) cfid;
2089
2090 /* Read the EISA Configuration Registers */
2091 irq = inb(EISA_REG0);
2092 irq = de4x5_irq[(irq >> 1) & 0x03];
2093
2094 if (is_DC2114x) {
2095 device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2096 }
2097 lp->chipset = device;
2098
2099 /* Write the PCI Configuration Registers */
2100 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2101 outl(0x00006000, PCI_CFLT);
2102 outl(iobase, PCI_CBIO);
2103
2104 DevicePresent(EISA_APROM);
2105
2106 dev->irq = irq;
2107 if ((status = de4x5_hw_init(dev, iobase)) == 0) {
2108 num_de4x5s++;
2109 if (loading_module) link_modules(lastModule, dev);
2110 lastEISA = i;
2111 return;
2112 }
2113 }
2114
2115 if (ioaddr == 0) lastEISA = i;
2116
2117 return;
2118 }
2119 #endif /* !(__sparc_v9__) && !(__powerpc__) && !defined(__alpha__) */
2120
2121 /*
2122 ** PCI bus I/O device probe
2123 ** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2124 ** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2125 ** enabled by the user first in the set up utility. Hence we just check for
2126 ** enabled features and silently ignore the card if they're not.
2127 **
2128 ** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2129 ** bit. Here, check for I/O accesses and then set BM. If you put the card in
2130 ** a non BM slot, you're on your own (and complain to the PC vendor that your
2131 ** PC doesn't conform to the PCI standard)!
2132 **
2133 ** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x
2134 ** kernels use the V0.535[n] drivers.
2135 */
2136 #define PCI_LAST_DEV 32
2137
2138 static void __init
2139 pci_probe(struct net_device *dev, u_long ioaddr)
2140 {
2141 u_char pb, pbus, dev_num, dnum, timer;
2142 u_short vendor, index, status;
2143 u_int irq = 0, device, class = DE4X5_CLASS_CODE;
2144 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2145 struct bus_type *lp = &bus;
2146
2147 if (lastPCI == NO_MORE_PCI) return;
2148
2149 if (!pcibios_present()) {
2150 lastPCI = NO_MORE_PCI;
2151 return; /* No PCI bus in this machine! */
2152 }
2153
2154 lp->bus = PCI;
2155 lp->bus_num = 0;
2156
2157 if ((ioaddr < 0x1000) && loading_module) {
2158 pbus = (u_short)(ioaddr >> 8);
2159 dnum = (u_short)(ioaddr & 0xff);
2160 } else {
2161 pbus = 0;
2162 dnum = 0;
2163 }
2164
2165 for (index=lastPCI+1;(pdev = pci_find_class(class, pdev))!=NULL;index++) {
2166 dev_num = PCI_SLOT(pdev->devfn);
2167 pb = pdev->bus->number;
2168 if ((pbus || dnum) && ((pbus != pb) || (dnum != dev_num))) continue;
2169
2170 vendor = pdev->vendor;
2171 device = pdev->device << 8;
2172 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2173
2174 /* Search for an SROM on this bus */
2175 if (lp->bus_num != pb) {
2176 lp->bus_num = pb;
2177 srom_search(pdev);
2178 }
2179
2180 /* Get the chip configuration revision register */
2181 pcibios_read_config_dword(pb, pdev->devfn, PCI_REVISION_ID, &cfrv);
2182
2183 /* Set the device number information */
2184 lp->device = dev_num;
2185 lp->bus_num = pb;
2186
2187 /* Set the chipset information */
2188 if (is_DC2114x) {
2189 device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2190 }
2191 lp->chipset = device;
2192
2193 /* Get the board I/O address (64 bits on sparc64) */
2194 iobase = pdev->resource[0].start;
2195
2196 /* Fetch the IRQ to be used */
2197 irq = pdev->irq;
2198 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2199
2200 /* Check if I/O accesses and Bus Mastering are enabled */
2201 pcibios_read_config_word(pb, pdev->devfn, PCI_COMMAND, &status);
2202 #ifdef __powerpc__
2203 if (!(status & PCI_COMMAND_IO)) {
2204 status |= PCI_COMMAND_IO;
2205 pcibios_write_config_word(pb, pdev->devfn, PCI_COMMAND, status);
2206 pcibios_read_config_word(pb, pdev->devfn, PCI_COMMAND, &status);
2207 }
2208 #endif /* __powerpc__ */
2209 if (!(status & PCI_COMMAND_IO)) continue;
2210
2211 if (!(status & PCI_COMMAND_MASTER)) {
2212 status |= PCI_COMMAND_MASTER;
2213 pcibios_write_config_word(pb, pdev->devfn, PCI_COMMAND, status);
2214 pcibios_read_config_word(pb, pdev->devfn, PCI_COMMAND, &status);
2215 }
2216 if (!(status & PCI_COMMAND_MASTER)) continue;
2217
2218 /* Check the latency timer for values >= 0x60 */
2219 pcibios_read_config_byte(pb, pdev->devfn, PCI_LATENCY_TIMER, &timer);
2220 if (timer < 0x60) {
2221 pcibios_write_config_byte(pb, pdev->devfn, PCI_LATENCY_TIMER, 0x60);
2222 }
2223
2224 DevicePresent(DE4X5_APROM);
2225 if (check_region(iobase, DE4X5_PCI_TOTAL_SIZE) == 0) {
2226 dev->irq = irq;
2227 if ((status = de4x5_hw_init(dev, iobase)) == 0) {
2228 num_de4x5s++;
2229 lastPCI = index;
2230 if (loading_module) link_modules(lastModule, dev);
2231 return;
2232 }
2233 } else if (ioaddr != 0) {
2234 printk("%s: region already allocated at 0x%04lx.\n", dev->name,
2235 iobase);
2236 }
2237 }
2238
2239 lastPCI = NO_MORE_PCI;
2240
2241 return;
2242 }
2243
2244 /*
2245 ** This function searches the current bus (which is >0) for a DECchip with an
2246 ** SROM, so that in multiport cards that have one SROM shared between multiple
2247 ** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2248 ** For single port cards this is a time waster...
2249 */
2250 static void __init
2251 srom_search(struct pci_dev *dev)
2252 {
2253 u_char pb;
2254 u_short vendor, status;
2255 u_int irq = 0, device;
2256 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2257 int i, j;
2258 struct bus_type *lp = &bus;
2259
2260 for (; (dev=dev->sibling)!= NULL;) {
2261 pb = dev->bus->number;
2262 vendor = dev->vendor;
2263 device = dev->device << 8;
2264 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2265
2266 /* Get the chip configuration revision register */
2267 pcibios_read_config_dword(pb, dev->devfn, PCI_REVISION_ID, &cfrv);
2268
2269 /* Set the device number information */
2270 lp->device = PCI_SLOT(dev->devfn);
2271 lp->bus_num = pb;
2272
2273 /* Set the chipset information */
2274 if (is_DC2114x) {
2275 device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2276 }
2277 lp->chipset = device;
2278
2279 /* Get the board I/O address (64 bits on sparc64) */
2280 iobase = dev->resource[0].start;
2281
2282 /* Fetch the IRQ to be used */
2283 irq = dev->irq;
2284 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2285
2286 /* Check if I/O accesses are enabled */
2287 pcibios_read_config_word(pb, dev->devfn, PCI_COMMAND, &status);
2288 if (!(status & PCI_COMMAND_IO)) continue;
2289
2290 /* Search for a valid SROM attached to this DECchip */
2291 DevicePresent(DE4X5_APROM);
2292 for (j=0, i=0; i<ETH_ALEN; i++) {
2293 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2294 }
2295 if ((j != 0) && (j != 0x5fa)) {
2296 last.chipset = device;
2297 last.bus = pb;
2298 last.irq = irq;
2299 for (i=0; i<ETH_ALEN; i++) {
2300 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2301 }
2302 return;
2303 }
2304 }
2305
2306 return;
2307 }
2308
2309 static void __init
2310 link_modules(struct net_device *dev, struct net_device *tmp)
2311 {
2312 struct net_device *p=dev;
2313
2314 if (p) {
2315 while (((struct de4x5_private *)(p->priv))->next_module) {
2316 p = ((struct de4x5_private *)(p->priv))->next_module;
2317 }
2318
2319 if (dev != tmp) {
2320 ((struct de4x5_private *)(p->priv))->next_module = tmp;
2321 } else {
2322 ((struct de4x5_private *)(p->priv))->next_module = NULL;
2323 }
2324 }
2325
2326 return;
2327 }
2328
2329 /*
2330 ** Auto configure the media here rather than setting the port at compile
2331 ** time. This routine is called by de4x5_init() and when a loss of media is
2332 ** detected (excessive collisions, loss of carrier, no carrier or link fail
2333 ** [TP] or no recent receive activity) to check whether the user has been
2334 ** sneaky and changed the port on us.
2335 */
2336 static int
2337 autoconf_media(struct net_device *dev)
2338 {
2339 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2340 u_long iobase = dev->base_addr;
2341 int next_tick = DE4X5_AUTOSENSE_MS;
2342
2343 lp->linkOK = 0;
2344 lp->c_media = AUTO; /* Bogus last media */
2345 disable_ast(dev);
2346 inl(DE4X5_MFC); /* Zero the lost frames counter */
2347 lp->media = INIT;
2348 lp->tcount = 0;
2349
2350 if (lp->useSROM) {
2351 next_tick = srom_autoconf(dev);
2352 } else if (lp->chipset == DC21040) {
2353 next_tick = dc21040_autoconf(dev);
2354 } else if (lp->chipset == DC21041) {
2355 next_tick = dc21041_autoconf(dev);
2356 } else if (lp->chipset == DC21140) {
2357 next_tick = dc21140m_autoconf(dev);
2358 }
2359
2360 enable_ast(dev, next_tick);
2361
2362 return (lp->media);
2363 }
2364
2365 /*
2366 ** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2367 ** from BNC as the port has a jumper to set thick or thin wire. When set for
2368 ** BNC, the BNC port will indicate activity if it's not terminated correctly.
2369 ** The only way to test for that is to place a loopback packet onto the
2370 ** network and watch for errors. Since we're messing with the interrupt mask
2371 ** register, disable the board interrupts and do not allow any more packets to
2372 ** be queued to the hardware. Re-enable everything only when the media is
2373 ** found.
2374 ** I may have to "age out" locally queued packets so that the higher layer
2375 ** timeouts don't effectively duplicate packets on the network.
2376 */
2377 static int
2378 dc21040_autoconf(struct net_device *dev)
2379 {
2380 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2381 u_long iobase = dev->base_addr;
2382 int next_tick = DE4X5_AUTOSENSE_MS;
2383 s32 imr;
2384
2385 switch (lp->media) {
2386 case INIT:
2387 DISABLE_IRQs;
2388 lp->tx_enable = NO;
2389 lp->timeout = -1;
2390 de4x5_save_skbs(dev);
2391 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2392 lp->media = TP;
2393 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2394 lp->media = BNC_AUI;
2395 } else if (lp->autosense == EXT_SIA) {
2396 lp->media = EXT_SIA;
2397 } else {
2398 lp->media = NC;
2399 }
2400 lp->local_state = 0;
2401 next_tick = dc21040_autoconf(dev);
2402 break;
2403
2404 case TP:
2405 next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2406 TP_SUSPECT, test_tp);
2407 break;
2408
2409 case TP_SUSPECT:
2410 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2411 break;
2412
2413 case BNC:
2414 case AUI:
2415 case BNC_AUI:
2416 next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2417 BNC_AUI_SUSPECT, ping_media);
2418 break;
2419
2420 case BNC_AUI_SUSPECT:
2421 next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2422 break;
2423
2424 case EXT_SIA:
2425 next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2426 NC, EXT_SIA_SUSPECT, ping_media);
2427 break;
2428
2429 case EXT_SIA_SUSPECT:
2430 next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2431 break;
2432
2433 case NC:
2434 /* default to TP for all */
2435 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2436 if (lp->media != lp->c_media) {
2437 de4x5_dbg_media(dev);
2438 lp->c_media = lp->media;
2439 }
2440 lp->media = INIT;
2441 lp->tx_enable = NO;
2442 break;
2443 }
2444
2445 return next_tick;
2446 }
2447
2448 static int
2449 dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout,
2450 int next_state, int suspect_state,
2451 int (*fn)(struct net_device *, int))
2452 {
2453 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2454 int next_tick = DE4X5_AUTOSENSE_MS;
2455 int linkBad;
2456
2457 switch (lp->local_state) {
2458 case 0:
2459 reset_init_sia(dev, csr13, csr14, csr15);
2460 lp->local_state++;
2461 next_tick = 500;
2462 break;
2463
2464 case 1:
2465 if (!lp->tx_enable) {
2466 linkBad = fn(dev, timeout);
2467 if (linkBad < 0) {
2468 next_tick = linkBad & ~TIMER_CB;
2469 } else {
2470 if (linkBad && (lp->autosense == AUTO)) {
2471 lp->local_state = 0;
2472 lp->media = next_state;
2473 } else {
2474 de4x5_init_connection(dev);
2475 }
2476 }
2477 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2478 lp->media = suspect_state;
2479 next_tick = 3000;
2480 }
2481 break;
2482 }
2483
2484 return next_tick;
2485 }
2486
2487 static int
2488 de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state,
2489 int (*fn)(struct net_device *, int),
2490 int (*asfn)(struct net_device *))
2491 {
2492 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2493 int next_tick = DE4X5_AUTOSENSE_MS;
2494 int linkBad;
2495
2496 switch (lp->local_state) {
2497 case 1:
2498 if (lp->linkOK) {
2499 lp->media = prev_state;
2500 } else {
2501 lp->local_state++;
2502 next_tick = asfn(dev);
2503 }
2504 break;
2505
2506 case 2:
2507 linkBad = fn(dev, timeout);
2508 if (linkBad < 0) {
2509 next_tick = linkBad & ~TIMER_CB;
2510 } else if (!linkBad) {
2511 lp->local_state--;
2512 lp->media = prev_state;
2513 } else {
2514 lp->media = INIT;
2515 lp->tcount++;
2516 }
2517 }
2518
2519 return next_tick;
2520 }
2521
2522 /*
2523 ** Autoconfigure the media when using the DC21041. AUI needs to be tested
2524 ** before BNC, because the BNC port will indicate activity if it's not
2525 ** terminated correctly. The only way to test for that is to place a loopback
2526 ** packet onto the network and watch for errors. Since we're messing with
2527 ** the interrupt mask register, disable the board interrupts and do not allow
2528 ** any more packets to be queued to the hardware. Re-enable everything only
2529 ** when the media is found.
2530 */
2531 static int
2532 dc21041_autoconf(struct net_device *dev)
2533 {
2534 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2535 u_long iobase = dev->base_addr;
2536 s32 sts, irqs, irq_mask, imr, omr;
2537 int next_tick = DE4X5_AUTOSENSE_MS;
2538
2539 switch (lp->media) {
2540 case INIT:
2541 DISABLE_IRQs;
2542 lp->tx_enable = NO;
2543 lp->timeout = -1;
2544 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2545 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2546 lp->media = TP; /* On chip auto negotiation is broken */
2547 } else if (lp->autosense == TP) {
2548 lp->media = TP;
2549 } else if (lp->autosense == BNC) {
2550 lp->media = BNC;
2551 } else if (lp->autosense == AUI) {
2552 lp->media = AUI;
2553 } else {
2554 lp->media = NC;
2555 }
2556 lp->local_state = 0;
2557 next_tick = dc21041_autoconf(dev);
2558 break;
2559
2560 case TP_NW:
2561 if (lp->timeout < 0) {
2562 omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2563 outl(omr | OMR_FDX, DE4X5_OMR);
2564 }
2565 irqs = STS_LNF | STS_LNP;
2566 irq_mask = IMR_LFM | IMR_LPM;
2567 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2568 if (sts < 0) {
2569 next_tick = sts & ~TIMER_CB;
2570 } else {
2571 if (sts & STS_LNP) {
2572 lp->media = ANS;
2573 } else {
2574 lp->media = AUI;
2575 }
2576 next_tick = dc21041_autoconf(dev);
2577 }
2578 break;
2579
2580 case ANS:
2581 if (!lp->tx_enable) {
2582 irqs = STS_LNP;
2583 irq_mask = IMR_LPM;
2584 sts = test_ans(dev, irqs, irq_mask, 3000);
2585 if (sts < 0) {
2586 next_tick = sts & ~TIMER_CB;
2587 } else {
2588 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2589 lp->media = TP;
2590 next_tick = dc21041_autoconf(dev);
2591 } else {
2592 lp->local_state = 1;
2593 de4x5_init_connection(dev);
2594 }
2595 }
2596 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2597 lp->media = ANS_SUSPECT;
2598 next_tick = 3000;
2599 }
2600 break;
2601
2602 case ANS_SUSPECT:
2603 next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2604 break;
2605
2606 case TP:
2607 if (!lp->tx_enable) {
2608 if (lp->timeout < 0) {
2609 omr = inl(DE4X5_OMR); /* Set up half duplex for TP */
2610 outl(omr & ~OMR_FDX, DE4X5_OMR);
2611 }
2612 irqs = STS_LNF | STS_LNP;
2613 irq_mask = IMR_LFM | IMR_LPM;
2614 sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2615 if (sts < 0) {
2616 next_tick = sts & ~TIMER_CB;
2617 } else {
2618 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2619 if (inl(DE4X5_SISR) & SISR_NRA) {
2620 lp->media = AUI; /* Non selected port activity */
2621 } else {
2622 lp->media = BNC;
2623 }
2624 next_tick = dc21041_autoconf(dev);
2625 } else {
2626 lp->local_state = 1;
2627 de4x5_init_connection(dev);
2628 }
2629 }
2630 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2631 lp->media = TP_SUSPECT;
2632 next_tick = 3000;
2633 }
2634 break;
2635
2636 case TP_SUSPECT:
2637 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2638 break;
2639
2640 case AUI:
2641 if (!lp->tx_enable) {
2642 if (lp->timeout < 0) {
2643 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
2644 outl(omr & ~OMR_FDX, DE4X5_OMR);
2645 }
2646 irqs = 0;
2647 irq_mask = 0;
2648 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2649 if (sts < 0) {
2650 next_tick = sts & ~TIMER_CB;
2651 } else {
2652 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2653 lp->media = BNC;
2654 next_tick = dc21041_autoconf(dev);
2655 } else {
2656 lp->local_state = 1;
2657 de4x5_init_connection(dev);
2658 }
2659 }
2660 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2661 lp->media = AUI_SUSPECT;
2662 next_tick = 3000;
2663 }
2664 break;
2665
2666 case AUI_SUSPECT:
2667 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2668 break;
2669
2670 case BNC:
2671 switch (lp->local_state) {
2672 case 0:
2673 if (lp->timeout < 0) {
2674 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
2675 outl(omr & ~OMR_FDX, DE4X5_OMR);
2676 }
2677 irqs = 0;
2678 irq_mask = 0;
2679 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2680 if (sts < 0) {
2681 next_tick = sts & ~TIMER_CB;
2682 } else {
2683 lp->local_state++; /* Ensure media connected */
2684 next_tick = dc21041_autoconf(dev);
2685 }
2686 break;
2687
2688 case 1:
2689 if (!lp->tx_enable) {
2690 if ((sts = ping_media(dev, 3000)) < 0) {
2691 next_tick = sts & ~TIMER_CB;
2692 } else {
2693 if (sts) {
2694 lp->local_state = 0;
2695 lp->media = NC;
2696 } else {
2697 de4x5_init_connection(dev);
2698 }
2699 }
2700 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2701 lp->media = BNC_SUSPECT;
2702 next_tick = 3000;
2703 }
2704 break;
2705 }
2706 break;
2707
2708 case BNC_SUSPECT:
2709 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2710 break;
2711
2712 case NC:
2713 omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
2714 outl(omr | OMR_FDX, DE4X5_OMR);
2715 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2716 if (lp->media != lp->c_media) {
2717 de4x5_dbg_media(dev);
2718 lp->c_media = lp->media;
2719 }
2720 lp->media = INIT;
2721 lp->tx_enable = NO;
2722 break;
2723 }
2724
2725 return next_tick;
2726 }
2727
2728 /*
2729 ** Some autonegotiation chips are broken in that they do not return the
2730 ** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2731 ** register, except at the first power up negotiation.
2732 */
2733 static int
2734 dc21140m_autoconf(struct net_device *dev)
2735 {
2736 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2737 int ana, anlpa, cap, cr, slnk, sr;
2738 int next_tick = DE4X5_AUTOSENSE_MS;
2739 u_long imr, omr, iobase = dev->base_addr;
2740
2741 switch(lp->media) {
2742 case INIT:
2743 if (lp->timeout < 0) {
2744 DISABLE_IRQs;
2745 lp->tx_enable = FALSE;
2746 lp->linkOK = 0;
2747 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2748 }
2749 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2750 next_tick &= ~TIMER_CB;
2751 } else {
2752 if (lp->useSROM) {
2753 if (srom_map_media(dev) < 0) {
2754 lp->tcount++;
2755 return next_tick;
2756 }
2757 srom_exec(dev, lp->phy[lp->active].gep);
2758 if (lp->infoblock_media == ANS) {
2759 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2760 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2761 }
2762 } else {
2763 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2764 SET_10Mb;
2765 if (lp->autosense == _100Mb) {
2766 lp->media = _100Mb;
2767 } else if (lp->autosense == _10Mb) {
2768 lp->media = _10Mb;
2769 } else if ((lp->autosense == AUTO) &&
2770 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2771 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2772 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2773 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2774 lp->media = ANS;
2775 } else if (lp->autosense == AUTO) {
2776 lp->media = SPD_DET;
2777 } else if (is_spd_100(dev) && is_100_up(dev)) {
2778 lp->media = _100Mb;
2779 } else {
2780 lp->media = NC;
2781 }
2782 }
2783 lp->local_state = 0;
2784 next_tick = dc21140m_autoconf(dev);
2785 }
2786 break;
2787
2788 case ANS:
2789 switch (lp->local_state) {
2790 case 0:
2791 if (lp->timeout < 0) {
2792 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2793 }
2794 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
2795 if (cr < 0) {
2796 next_tick = cr & ~TIMER_CB;
2797 } else {
2798 if (cr) {
2799 lp->local_state = 0;
2800 lp->media = SPD_DET;
2801 } else {
2802 lp->local_state++;
2803 }
2804 next_tick = dc21140m_autoconf(dev);
2805 }
2806 break;
2807
2808 case 1:
2809 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
2810 next_tick = sr & ~TIMER_CB;
2811 } else {
2812 lp->media = SPD_DET;
2813 lp->local_state = 0;
2814 if (sr) { /* Success! */
2815 lp->tmp = MII_SR_ASSC;
2816 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2817 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2818 if (!(anlpa & MII_ANLPA_RF) &&
2819 (cap = anlpa & MII_ANLPA_TAF & ana)) {
2820 if (cap & MII_ANA_100M) {
2821 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
2822 lp->media = _100Mb;
2823 } else if (cap & MII_ANA_10M) {
2824 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
2825
2826 lp->media = _10Mb;
2827 }
2828 }
2829 } /* Auto Negotiation failed to finish */
2830 next_tick = dc21140m_autoconf(dev);
2831 } /* Auto Negotiation failed to start */
2832 break;
2833 }
2834 break;
2835
2836 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
2837 if (lp->timeout < 0) {
2838 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2839 (~gep_rd(dev) & GEP_LNP));
2840 SET_100Mb_PDET;
2841 }
2842 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2843 next_tick = slnk & ~TIMER_CB;
2844 } else {
2845 if (is_spd_100(dev) && is_100_up(dev)) {
2846 lp->media = _100Mb;
2847 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2848 lp->media = _10Mb;
2849 } else {
2850 lp->media = NC;
2851 }
2852 next_tick = dc21140m_autoconf(dev);
2853 }
2854 break;
2855
2856 case _100Mb: /* Set 100Mb/s */
2857 next_tick = 3000;
2858 if (!lp->tx_enable) {
2859 SET_100Mb;
2860 de4x5_init_connection(dev);
2861 } else {
2862 if (!lp->linkOK && (lp->autosense == AUTO)) {
2863 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2864 lp->media = INIT;
2865 lp->tcount++;
2866 next_tick = DE4X5_AUTOSENSE_MS;
2867 }
2868 }
2869 }
2870 break;
2871
2872 case BNC:
2873 case AUI:
2874 case _10Mb: /* Set 10Mb/s */
2875 next_tick = 3000;
2876 if (!lp->tx_enable) {
2877 SET_10Mb;
2878 de4x5_init_connection(dev);
2879 } else {
2880 if (!lp->linkOK && (lp->autosense == AUTO)) {
2881 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2882 lp->media = INIT;
2883 lp->tcount++;
2884 next_tick = DE4X5_AUTOSENSE_MS;
2885 }
2886 }
2887 }
2888 break;
2889
2890 case NC:
2891 if (lp->media != lp->c_media) {
2892 de4x5_dbg_media(dev);
2893 lp->c_media = lp->media;
2894 }
2895 lp->media = INIT;
2896 lp->tx_enable = FALSE;
2897 break;
2898 }
2899
2900 return next_tick;
2901 }
2902
2903 /*
2904 ** This routine may be merged into dc21140m_autoconf() sometime as I'm
2905 ** changing how I figure out the media - but trying to keep it backwards
2906 ** compatible with the de500-xa and de500-aa.
2907 ** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2908 ** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2909 ** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2910 ** active.
2911 ** When autonegotiation is working, the ANS part searches the SROM for
2912 ** the highest common speed (TP) link that both can run and if that can
2913 ** be full duplex. That infoblock is executed and then the link speed set.
2914 **
2915 ** Only _10Mb and _100Mb are tested here.
2916 */
2917 static int
2918 dc2114x_autoconf(struct net_device *dev)
2919 {
2920 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2921 u_long iobase = dev->base_addr;
2922 s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2923 int next_tick = DE4X5_AUTOSENSE_MS;
2924
2925 switch (lp->media) {
2926 case INIT:
2927 if (lp->timeout < 0) {
2928 DISABLE_IRQs;
2929 lp->tx_enable = FALSE;
2930 lp->linkOK = 0;
2931 lp->timeout = -1;
2932 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2933 if (lp->params.autosense & ~AUTO) {
2934 srom_map_media(dev); /* Fixed media requested */
2935 if (lp->media != lp->params.autosense) {
2936 lp->tcount++;
2937 lp->media = INIT;
2938 return next_tick;
2939 }
2940 lp->media = INIT;
2941 }
2942 }
2943 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2944 next_tick &= ~TIMER_CB;
2945 } else {
2946 if (lp->autosense == _100Mb) {
2947 lp->media = _100Mb;
2948 } else if (lp->autosense == _10Mb) {
2949 lp->media = _10Mb;
2950 } else if (lp->autosense == TP) {
2951 lp->media = TP;
2952 } else if (lp->autosense == BNC) {
2953 lp->media = BNC;
2954 } else if (lp->autosense == AUI) {
2955 lp->media = AUI;
2956 } else {
2957 lp->media = SPD_DET;
2958 if ((lp->infoblock_media == ANS) &&
2959 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2960 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2961 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2962 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2963 lp->media = ANS;
2964 }
2965 }
2966 lp->local_state = 0;
2967 next_tick = dc2114x_autoconf(dev);
2968 }
2969 break;
2970
2971 case ANS:
2972 switch (lp->local_state) {
2973 case 0:
2974 if (lp->timeout < 0) {
2975 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2976 }
2977 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
2978 if (cr < 0) {
2979 next_tick = cr & ~TIMER_CB;
2980 } else {
2981 if (cr) {
2982 lp->local_state = 0;
2983 lp->media = SPD_DET;
2984 } else {
2985 lp->local_state++;
2986 }
2987 next_tick = dc2114x_autoconf(dev);
2988 }
2989 break;
2990
2991 case 1:
2992 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
2993 next_tick = sr & ~TIMER_CB;
2994 } else {
2995 lp->media = SPD_DET;
2996 lp->local_state = 0;
2997 if (sr) { /* Success! */
2998 lp->tmp = MII_SR_ASSC;
2999 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3000 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3001 if (!(anlpa & MII_ANLPA_RF) &&
3002 (cap = anlpa & MII_ANLPA_TAF & ana)) {
3003 if (cap & MII_ANA_100M) {
3004 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
3005 lp->media = _100Mb;
3006 } else if (cap & MII_ANA_10M) {
3007 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
3008 lp->media = _10Mb;
3009 }
3010 }
3011 } /* Auto Negotiation failed to finish */
3012 next_tick = dc2114x_autoconf(dev);
3013 } /* Auto Negotiation failed to start */
3014 break;
3015 }
3016 break;
3017
3018 case AUI:
3019 if (!lp->tx_enable) {
3020 if (lp->timeout < 0) {
3021 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
3022 outl(omr & ~OMR_FDX, DE4X5_OMR);
3023 }
3024 irqs = 0;
3025 irq_mask = 0;
3026 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3027 if (sts < 0) {
3028 next_tick = sts & ~TIMER_CB;
3029 } else {
3030 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3031 lp->media = BNC;
3032 next_tick = dc2114x_autoconf(dev);
3033 } else {
3034 lp->local_state = 1;
3035 de4x5_init_connection(dev);
3036 }
3037 }
3038 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3039 lp->media = AUI_SUSPECT;
3040 next_tick = 3000;
3041 }
3042 break;
3043
3044 case AUI_SUSPECT:
3045 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3046 break;
3047
3048 case BNC:
3049 switch (lp->local_state) {
3050 case 0:
3051 if (lp->timeout < 0) {
3052 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
3053 outl(omr & ~OMR_FDX, DE4X5_OMR);
3054 }
3055 irqs = 0;
3056 irq_mask = 0;
3057 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3058 if (sts < 0) {
3059 next_tick = sts & ~TIMER_CB;
3060 } else {
3061 lp->local_state++; /* Ensure media connected */
3062 next_tick = dc2114x_autoconf(dev);
3063 }
3064 break;
3065
3066 case 1:
3067 if (!lp->tx_enable) {
3068 if ((sts = ping_media(dev, 3000)) < 0) {
3069 next_tick = sts & ~TIMER_CB;
3070 } else {
3071 if (sts) {
3072 lp->local_state = 0;
3073 lp->tcount++;
3074 lp->media = INIT;
3075 } else {
3076 de4x5_init_connection(dev);
3077 }
3078 }
3079 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3080 lp->media = BNC_SUSPECT;
3081 next_tick = 3000;
3082 }
3083 break;
3084 }
3085 break;
3086
3087 case BNC_SUSPECT:
3088 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3089 break;
3090
3091 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
3092 if (srom_map_media(dev) < 0) {
3093 lp->tcount++;
3094 lp->media = INIT;
3095 return next_tick;
3096 }
3097 if (lp->media == _100Mb) {
3098 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3099 lp->media = SPD_DET;
3100 return (slnk & ~TIMER_CB);
3101 }
3102 } else {
3103 if (wait_for_link(dev) < 0) {
3104 lp->media = SPD_DET;
3105 return PDET_LINK_WAIT;
3106 }
3107 }
3108 if (lp->media == ANS) { /* Do MII parallel detection */
3109 if (is_spd_100(dev)) {
3110 lp->media = _100Mb;
3111 } else {
3112 lp->media = _10Mb;
3113 }
3114 next_tick = dc2114x_autoconf(dev);
3115 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3116 (((lp->media == _10Mb) || (lp->media == TP) ||
3117 (lp->media == BNC) || (lp->media == AUI)) &&
3118 is_10_up(dev))) {
3119 next_tick = dc2114x_autoconf(dev);
3120 } else {
3121 lp->tcount++;
3122 lp->media = INIT;
3123 }
3124 break;
3125
3126 case _10Mb:
3127 next_tick = 3000;
3128 if (!lp->tx_enable) {
3129 SET_10Mb;
3130 de4x5_init_connection(dev);
3131 } else {
3132 if (!lp->linkOK && (lp->autosense == AUTO)) {
3133 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3134 lp->media = INIT;
3135 lp->tcount++;
3136 next_tick = DE4X5_AUTOSENSE_MS;
3137 }
3138 }
3139 }
3140 break;
3141
3142 case _100Mb:
3143 next_tick = 3000;
3144 if (!lp->tx_enable) {
3145 SET_100Mb;
3146 de4x5_init_connection(dev);
3147 } else {
3148 if (!lp->linkOK && (lp->autosense == AUTO)) {
3149 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3150 lp->media = INIT;
3151 lp->tcount++;
3152 next_tick = DE4X5_AUTOSENSE_MS;
3153 }
3154 }
3155 }
3156 break;
3157
3158 default:
3159 lp->tcount++;
3160 printk("Huh?: media:%02x\n", lp->media);
3161 lp->media = INIT;
3162 break;
3163 }
3164
3165 return next_tick;
3166 }
3167
3168 static int
3169 srom_autoconf(struct net_device *dev)
3170 {
3171 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3172
3173 return lp->infoleaf_fn(dev);
3174 }
3175
3176 /*
3177 ** This mapping keeps the original media codes and FDX flag unchanged.
3178 ** While it isn't strictly necessary, it helps me for the moment...
3179 ** The early return avoids a media state / SROM media space clash.
3180 */
3181 static int
3182 srom_map_media(struct net_device *dev)
3183 {
3184 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3185
3186 lp->fdx = 0;
3187 if (lp->infoblock_media == lp->media)
3188 return 0;
3189
3190 switch(lp->infoblock_media) {
3191 case SROM_10BASETF:
3192 if (!lp->params.fdx) return -1;
3193 lp->fdx = TRUE;
3194 case SROM_10BASET:
3195 if (lp->params.fdx && !lp->fdx) return -1;
3196 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3197 lp->media = _10Mb;
3198 } else {
3199 lp->media = TP;
3200 }
3201 break;
3202
3203 case SROM_10BASE2:
3204 lp->media = BNC;
3205 break;
3206
3207 case SROM_10BASE5:
3208 lp->media = AUI;
3209 break;
3210
3211 case SROM_100BASETF:
3212 if (!lp->params.fdx) return -1;
3213 lp->fdx = TRUE;
3214 case SROM_100BASET:
3215 if (lp->params.fdx && !lp->fdx) return -1;
3216 lp->media = _100Mb;
3217 break;
3218
3219 case SROM_100BASET4:
3220 lp->media = _100Mb;
3221 break;
3222
3223 case SROM_100BASEFF:
3224 if (!lp->params.fdx) return -1;
3225 lp->fdx = TRUE;
3226 case SROM_100BASEF:
3227 if (lp->params.fdx && !lp->fdx) return -1;
3228 lp->media = _100Mb;
3229 break;
3230
3231 case ANS:
3232 lp->media = ANS;
3233 break;
3234
3235 default:
3236 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3237 lp->infoblock_media);
3238 return -1;
3239 break;
3240 }
3241
3242 return 0;
3243 }
3244
3245 static void
3246 de4x5_init_connection(struct net_device *dev)
3247 {
3248 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3249 u_long iobase = dev->base_addr;
3250 u_long flags = 0;
3251
3252 if (lp->media != lp->c_media) {
3253 de4x5_dbg_media(dev);
3254 lp->c_media = lp->media; /* Stop scrolling media messages */
3255 }
3256
3257 spin_lock_irqsave(&lp->lock, flags);
3258 de4x5_rst_desc_ring(dev);
3259 de4x5_setup_intr(dev);
3260 lp->tx_enable = YES;
3261 dev->tbusy = 0;
3262 spin_unlock_irqrestore(&lp->lock, flags);
3263 outl(POLL_DEMAND, DE4X5_TPD);
3264 mark_bh(NET_BH);
3265
3266 return;
3267 }
3268
3269 /*
3270 ** General PHY reset function. Some MII devices don't reset correctly
3271 ** since their MII address pins can float at voltages that are dependent
3272 ** on the signal pin use. Do a double reset to ensure a reset.
3273 */
3274 static int
3275 de4x5_reset_phy(struct net_device *dev)
3276 {
3277 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3278 u_long iobase = dev->base_addr;
3279 int next_tick = 0;
3280
3281 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3282 if (lp->timeout < 0) {
3283 if (lp->useSROM) {
3284 if (lp->phy[lp->active].rst) {
3285 srom_exec(dev, lp->phy[lp->active].rst);
3286 srom_exec(dev, lp->phy[lp->active].rst);
3287 } else if (lp->rst) { /* Type 5 infoblock reset */
3288 srom_exec(dev, lp->rst);
3289 srom_exec(dev, lp->rst);
3290 }
3291 } else {
3292 PHY_HARD_RESET;
3293 }
3294 if (lp->useMII) {
3295 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3296 }
3297 }
3298 if (lp->useMII) {
3299 next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, FALSE, 500);
3300 }
3301 } else if (lp->chipset == DC21140) {
3302 PHY_HARD_RESET;
3303 }
3304
3305 return next_tick;
3306 }
3307
3308 static int
3309 test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3310 {
3311 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3312 u_long iobase = dev->base_addr;
3313 s32 sts, csr12;
3314
3315 if (lp->timeout < 0) {
3316 lp->timeout = msec/100;
3317 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */
3318 reset_init_sia(dev, csr13, csr14, csr15);
3319 }
3320
3321 /* set up the interrupt mask */
3322 outl(irq_mask, DE4X5_IMR);
3323
3324 /* clear all pending interrupts */
3325 sts = inl(DE4X5_STS);
3326 outl(sts, DE4X5_STS);
3327
3328 /* clear csr12 NRA and SRA bits */
3329 if ((lp->chipset == DC21041) || lp->useSROM) {
3330 csr12 = inl(DE4X5_SISR);
3331 outl(csr12, DE4X5_SISR);
3332 }
3333 }
3334
3335 sts = inl(DE4X5_STS) & ~TIMER_CB;
3336
3337 if (!(sts & irqs) && --lp->timeout) {
3338 sts = 100 | TIMER_CB;
3339 } else {
3340 lp->timeout = -1;
3341 }
3342
3343 return sts;
3344 }
3345
3346 static int
3347 test_tp(struct net_device *dev, s32 msec)
3348 {
3349 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3350 u_long iobase = dev->base_addr;
3351 int sisr;
3352
3353 if (lp->timeout < 0) {
3354 lp->timeout = msec/100;
3355 }
3356
3357 sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3358
3359 if (sisr && --lp->timeout) {
3360 sisr = 100 | TIMER_CB;
3361 } else {
3362 lp->timeout = -1;
3363 }
3364
3365 return sisr;
3366 }
3367
3368 /*
3369 ** Samples the 100Mb Link State Signal. The sample interval is important
3370 ** because too fast a rate can give erroneous results and confuse the
3371 ** speed sense algorithm.
3372 */
3373 #define SAMPLE_INTERVAL 500 /* ms */
3374 #define SAMPLE_DELAY 2000 /* ms */
3375 static int
3376 test_for_100Mb(struct net_device *dev, int msec)
3377 {
3378 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3379 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3380
3381 if (lp->timeout < 0) {
3382 if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3383 if (msec > SAMPLE_DELAY) {
3384 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3385 gep = SAMPLE_DELAY | TIMER_CB;
3386 return gep;
3387 } else {
3388 lp->timeout = msec/SAMPLE_INTERVAL;
3389 }
3390 }
3391
3392 if (lp->phy[lp->active].id || lp->useSROM) {
3393 gep = is_100_up(dev) | is_spd_100(dev);
3394 } else {
3395 gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3396 }
3397 if (!(gep & ret) && --lp->timeout) {
3398 gep = SAMPLE_INTERVAL | TIMER_CB;
3399 } else {
3400 lp->timeout = -1;
3401 }
3402
3403 return gep;
3404 }
3405
3406 static int
3407 wait_for_link(struct net_device *dev)
3408 {
3409 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3410
3411 if (lp->timeout < 0) {
3412 lp->timeout = 1;
3413 }
3414
3415 if (lp->timeout--) {
3416 return TIMER_CB;
3417 } else {
3418 lp->timeout = -1;
3419 }
3420
3421 return 0;
3422 }
3423
3424 /*
3425 **
3426 **
3427 */
3428 static int
3429 test_mii_reg(struct net_device *dev, int reg, int mask, int pol, long msec)
3430 {
3431 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3432 int test;
3433 u_long iobase = dev->base_addr;
3434
3435 if (lp->timeout < 0) {
3436 lp->timeout = msec/100;
3437 }
3438
3439 if (pol) pol = ~0;
3440 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3441 test = (reg ^ pol) & mask;
3442
3443 if (test && --lp->timeout) {
3444 reg = 100 | TIMER_CB;
3445 } else {
3446 lp->timeout = -1;
3447 }
3448
3449 return reg;
3450 }
3451
3452 static int
3453 is_spd_100(struct net_device *dev)
3454 {
3455 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3456 u_long iobase = dev->base_addr;
3457 int spd;
3458
3459 if (lp->useMII) {
3460 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3461 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3462 spd &= lp->phy[lp->active].spd.mask;
3463 } else if (!lp->useSROM) { /* de500-xa */
3464 spd = ((~gep_rd(dev)) & GEP_SLNK);
3465 } else {
3466 if ((lp->ibn == 2) || !lp->asBitValid)
3467 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3468
3469 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3470 (lp->linkOK & ~lp->asBitValid);
3471 }
3472
3473 return spd;
3474 }
3475
3476 static int
3477 is_100_up(struct net_device *dev)
3478 {
3479 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3480 u_long iobase = dev->base_addr;
3481
3482 if (lp->useMII) {
3483 /* Double read for sticky bits & temporary drops */
3484 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3485 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3486 } else if (!lp->useSROM) { /* de500-xa */
3487 return ((~gep_rd(dev)) & GEP_SLNK);
3488 } else {
3489 if ((lp->ibn == 2) || !lp->asBitValid)
3490 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3491
3492 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3493 (lp->linkOK & ~lp->asBitValid));
3494 }
3495 }
3496
3497 static int
3498 is_10_up(struct net_device *dev)
3499 {
3500 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3501 u_long iobase = dev->base_addr;
3502
3503 if (lp->useMII) {
3504 /* Double read for sticky bits & temporary drops */
3505 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3506 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3507 } else if (!lp->useSROM) { /* de500-xa */
3508 return ((~gep_rd(dev)) & GEP_LNP);
3509 } else {
3510 if ((lp->ibn == 2) || !lp->asBitValid)
3511 return (((lp->chipset & ~0x00ff) == DC2114x) ?
3512 (~inl(DE4X5_SISR)&SISR_LS10):
3513 0);
3514
3515 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3516 (lp->linkOK & ~lp->asBitValid));
3517 }
3518 }
3519
3520 static int
3521 is_anc_capable(struct net_device *dev)
3522 {
3523 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3524 u_long iobase = dev->base_addr;
3525
3526 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3527 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII));
3528 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3529 return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3530 } else {
3531 return 0;
3532 }
3533 }
3534
3535 /*
3536 ** Send a packet onto the media and watch for send errors that indicate the
3537 ** media is bad or unconnected.
3538 */
3539 static int
3540 ping_media(struct net_device *dev, int msec)
3541 {
3542 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3543 u_long iobase = dev->base_addr;
3544 int sisr;
3545
3546 if (lp->timeout < 0) {
3547 lp->timeout = msec/100;
3548
3549 lp->tmp = lp->tx_new; /* Remember the ring position */
3550 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), NULL);
3551 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
3552 outl(POLL_DEMAND, DE4X5_TPD);
3553 }
3554
3555 sisr = inl(DE4X5_SISR);
3556
3557 if ((!(sisr & SISR_NCR)) &&
3558 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3559 (--lp->timeout)) {
3560 sisr = 100 | TIMER_CB;
3561 } else {
3562 if ((!(sisr & SISR_NCR)) &&
3563 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3564 lp->timeout) {
3565 sisr = 0;
3566 } else {
3567 sisr = 1;
3568 }
3569 lp->timeout = -1;
3570 }
3571
3572 return sisr;
3573 }
3574
3575 /*
3576 ** This function does 2 things: on Intels it kmalloc's another buffer to
3577 ** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3578 ** into which the packet is copied.
3579 */
3580 static struct sk_buff *
3581 de4x5_alloc_rx_buff(struct net_device *dev, int index, int len)
3582 {
3583 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3584 struct sk_buff *p;
3585
3586 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
3587 struct sk_buff *ret;
3588 u_long i=0, tmp;
3589
3590 p = dev_alloc_skb(IEEE802_3_SZ + ALIGN + 2);
3591 if (!p) return NULL;
3592
3593 p->dev = dev;
3594 tmp = virt_to_bus(p->data);
3595 i = ((tmp + ALIGN) & ~ALIGN) - tmp;
3596 skb_reserve(p, i);
3597 lp->rx_ring[index].buf = tmp + i;
3598
3599 ret = lp->rx_skb[index];
3600 lp->rx_skb[index] = p;
3601
3602 if ((u_long) ret > 1) {
3603 skb_put(ret, len);
3604 }
3605
3606 return ret;
3607
3608 #else
3609 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3610
3611 p = dev_alloc_skb(len + 2);
3612 if (!p) return NULL;
3613
3614 p->dev = dev;
3615 skb_reserve(p, 2); /* Align */
3616 if (index < lp->rx_old) { /* Wrapped buffer */
3617 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3618 memcpy(skb_put(p,tlen),
3619 bus_to_virt(le32_to_cpu(lp->rx_ring[lp->rx_old].buf)),tlen);
3620 memcpy(skb_put(p,len-tlen),
3621 bus_to_virt(le32_to_cpu(lp->rx_ring[0].buf)), len-tlen);
3622 } else { /* Linear buffer */
3623 memcpy(skb_put(p,len),
3624 bus_to_virt(le32_to_cpu(lp->rx_ring[lp->rx_old].buf)),len);
3625 }
3626
3627 return p;
3628 #endif
3629 }
3630
3631 static void
3632 de4x5_free_rx_buffs(struct net_device *dev)
3633 {
3634 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3635 int i;
3636
3637 for (i=0; i<lp->rxRingSize; i++) {
3638 if ((u_long) lp->rx_skb[i] > 1) {
3639 dev_kfree_skb(lp->rx_skb[i]);
3640 }
3641 lp->rx_ring[i].status = 0;
3642 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */
3643 }
3644
3645 return;
3646 }
3647
3648 static void
3649 de4x5_free_tx_buffs(struct net_device *dev)
3650 {
3651 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3652 int i;
3653
3654 for (i=0; i<lp->txRingSize; i++) {
3655 if (lp->tx_skb[i]) {
3656 dev_kfree_skb(lp->tx_skb[i]);
3657 lp->tx_skb[i] = NULL;
3658 }
3659 lp->tx_ring[i].status = 0;
3660 }
3661
3662 /* Unload the locally queued packets */
3663 while (lp->cache.skb) {
3664 dev_kfree_skb(de4x5_get_cache(dev));
3665 }
3666
3667 return;
3668 }
3669
3670 /*
3671 ** When a user pulls a connection, the DECchip can end up in a
3672 ** 'running - waiting for end of transmission' state. This means that we
3673 ** have to perform a chip soft reset to ensure that we can synchronize
3674 ** the hardware and software and make any media probes using a loopback
3675 ** packet meaningful.
3676 */
3677 static void
3678 de4x5_save_skbs(struct net_device *dev)
3679 {
3680 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3681 u_long iobase = dev->base_addr;
3682 s32 omr;
3683
3684 if (!lp->cache.save_cnt) {
3685 STOP_DE4X5;
3686 de4x5_tx(dev); /* Flush any sent skb's */
3687 de4x5_free_tx_buffs(dev);
3688 de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3689 de4x5_sw_reset(dev);
3690 de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3691 lp->cache.save_cnt++;
3692 START_DE4X5;
3693 }
3694
3695 return;
3696 }
3697
3698 static void
3699 de4x5_rst_desc_ring(struct net_device *dev)
3700 {
3701 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3702 u_long iobase = dev->base_addr;
3703 int i;
3704 s32 omr;
3705
3706 if (lp->cache.save_cnt) {
3707 STOP_DE4X5;
3708 outl(virt_to_bus(lp->rx_ring), DE4X5_RRBA);
3709 outl(virt_to_bus(lp->tx_ring), DE4X5_TRBA);
3710
3711 lp->rx_new = lp->rx_old = 0;
3712 lp->tx_new = lp->tx_old = 0;
3713
3714 for (i = 0; i < lp->rxRingSize; i++) {
3715 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3716 }
3717
3718 for (i = 0; i < lp->txRingSize; i++) {
3719 lp->tx_ring[i].status = cpu_to_le32(0);
3720 }
3721
3722 barrier();
3723 lp->cache.save_cnt--;
3724 START_DE4X5;
3725 }
3726
3727 return;
3728 }
3729
3730 static void
3731 de4x5_cache_state(struct net_device *dev, int flag)
3732 {
3733 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3734 u_long iobase = dev->base_addr;
3735
3736 switch(flag) {
3737 case DE4X5_SAVE_STATE:
3738 lp->cache.csr0 = inl(DE4X5_BMR);
3739 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3740 lp->cache.csr7 = inl(DE4X5_IMR);
3741 break;
3742
3743 case DE4X5_RESTORE_STATE:
3744 outl(lp->cache.csr0, DE4X5_BMR);
3745 outl(lp->cache.csr6, DE4X5_OMR);
3746 outl(lp->cache.csr7, DE4X5_IMR);
3747 if (lp->chipset == DC21140) {
3748 gep_wr(lp->cache.gepc, dev);
3749 gep_wr(lp->cache.gep, dev);
3750 } else {
3751 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3752 lp->cache.csr15);
3753 }
3754 break;
3755 }
3756
3757 return;
3758 }
3759
3760 static void
3761 de4x5_put_cache(struct net_device *dev, struct sk_buff *skb)
3762 {
3763 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3764 struct sk_buff *p;
3765
3766 if (lp->cache.skb) {
3767 for (p=lp->cache.skb; p->next; p=p->next);
3768 p->next = skb;
3769 } else {
3770 lp->cache.skb = skb;
3771 }
3772 skb->next = NULL;
3773
3774 return;
3775 }
3776
3777 static void
3778 de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb)
3779 {
3780 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3781 struct sk_buff *p = lp->cache.skb;
3782
3783 lp->cache.skb = skb;
3784 skb->next = p;
3785
3786 return;
3787 }
3788
3789 static struct sk_buff *
3790 de4x5_get_cache(struct net_device *dev)
3791 {
3792 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3793 struct sk_buff *p = lp->cache.skb;
3794
3795 if (p) {
3796 lp->cache.skb = p->next;
3797 p->next = NULL;
3798 }
3799
3800 return p;
3801 }
3802
3803 /*
3804 ** Check the Auto Negotiation State. Return OK when a link pass interrupt
3805 ** is received and the auto-negotiation status is NWAY OK.
3806 */
3807 static int
3808 test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec)
3809 {
3810 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3811 u_long iobase = dev->base_addr;
3812 s32 sts, ans;
3813
3814 if (lp->timeout < 0) {
3815 lp->timeout = msec/100;
3816 outl(irq_mask, DE4X5_IMR);
3817
3818 /* clear all pending interrupts */
3819 sts = inl(DE4X5_STS);
3820 outl(sts, DE4X5_STS);
3821 }
3822
3823 ans = inl(DE4X5_SISR) & SISR_ANS;
3824 sts = inl(DE4X5_STS) & ~TIMER_CB;
3825
3826 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3827 sts = 100 | TIMER_CB;
3828 } else {
3829 lp->timeout = -1;
3830 }
3831
3832 return sts;
3833 }
3834
3835 static void
3836 de4x5_setup_intr(struct net_device *dev)
3837 {
3838 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3839 u_long iobase = dev->base_addr;
3840 s32 imr, sts;
3841
3842 if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */
3843 imr = 0;
3844 UNMASK_IRQs;
3845 sts = inl(DE4X5_STS); /* Reset any pending (stale) interrupts */
3846 outl(sts, DE4X5_STS);
3847 ENABLE_IRQs;
3848 }
3849
3850 return;
3851 }
3852
3853 /*
3854 **
3855 */
3856 static void
3857 reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15)
3858 {
3859 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3860 u_long iobase = dev->base_addr;
3861
3862 RESET_SIA;
3863 if (lp->useSROM) {
3864 if (lp->ibn == 3) {
3865 srom_exec(dev, lp->phy[lp->active].rst);
3866 srom_exec(dev, lp->phy[lp->active].gep);
3867 outl(1, DE4X5_SICR);
3868 return;
3869 } else {
3870 csr15 = lp->cache.csr15;
3871 csr14 = lp->cache.csr14;
3872 csr13 = lp->cache.csr13;
3873 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3874 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3875 }
3876 } else {
3877 outl(csr15, DE4X5_SIGR);
3878 }
3879 outl(csr14, DE4X5_STRR);
3880 outl(csr13, DE4X5_SICR);
3881
3882 de4x5_ms_delay(10);
3883
3884 return;
3885 }
3886
3887 /*
3888 ** Create a loopback ethernet packet
3889 */
3890 static void
3891 create_packet(struct net_device *dev, char *frame, int len)
3892 {
3893 int i;
3894 char *buf = frame;
3895
3896 for (i=0; i<ETH_ALEN; i++) { /* Use this source address */
3897 *buf++ = dev->dev_addr[i];
3898 }
3899 for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */
3900 *buf++ = dev->dev_addr[i];
3901 }
3902
3903 *buf++ = 0; /* Packet length (2 bytes) */
3904 *buf++ = 1;
3905
3906 return;
3907 }
3908
3909 /*
3910 ** Known delay in microseconds
3911 */
3912 static void
3913 de4x5_us_delay(u32 usec)
3914 {
3915 udelay(usec);
3916
3917 return;
3918 }
3919
3920 /*
3921 ** Known delay in milliseconds, in millisecond steps.
3922 */
3923 static void
3924 de4x5_ms_delay(u32 msec)
3925 {
3926 u_int i;
3927
3928 for (i=0; i<msec; i++) {
3929 de4x5_us_delay(1000);
3930 }
3931
3932 return;
3933 }
3934
3935
3936 /*
3937 ** Look for a particular board name in the EISA configuration space
3938 */
3939 static int
3940 EISA_signature(char *name, s32 eisa_id)
3941 {
3942 static c_char *signatures[] = DE4X5_SIGNATURE;
3943 char ManCode[DE4X5_STRLEN];
3944 union {
3945 s32 ID;
3946 char Id[4];
3947 } Eisa;
3948 int i, status = 0, siglen = sizeof(signatures)/sizeof(c_char *);
3949
3950 *name = '\0';
3951 Eisa.ID = inl(eisa_id);
3952
3953 ManCode[0]=(((Eisa.Id[0]>>2)&0x1f)+0x40);
3954 ManCode[1]=(((Eisa.Id[1]&0xe0)>>5)+((Eisa.Id[0]&0x03)<<3)+0x40);
3955 ManCode[2]=(((Eisa.Id[2]>>4)&0x0f)+0x30);
3956 ManCode[3]=((Eisa.Id[2]&0x0f)+0x30);
3957 ManCode[4]=(((Eisa.Id[3]>>4)&0x0f)+0x30);
3958 ManCode[5]='\0';
3959
3960 for (i=0;i<siglen;i++) {
3961 if (strstr(ManCode, signatures[i]) != NULL) {
3962 strcpy(name,ManCode);
3963 status = 1;
3964 break;
3965 }
3966 }
3967
3968 return status; /* return the device name string */
3969 }
3970
3971 /*
3972 ** Look for a particular board name in the PCI configuration space
3973 */
3974 static int
3975 PCI_signature(char *name, struct bus_type *lp)
3976 {
3977 static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
3978 int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *);
3979
3980 if (lp->chipset == DC21040) {
3981 strcpy(name, "DE434/5");
3982 return status;
3983 } else { /* Search for a DEC name in the SROM */
3984 int i = *((char *)&lp->srom + 19) * 3;
3985 strncpy(name, (char *)&lp->srom + 26 + i, 8);
3986 }
3987 name[8] = '\0';
3988 for (i=0; i<siglen; i++) {
3989 if (strstr(name,de4x5_signatures[i])!=NULL) break;
3990 }
3991 if (i == siglen) {
3992 if (dec_only) {
3993 *name = '\0';
3994 } else { /* Use chip name to avoid confusion */
3995 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
3996 ((lp->chipset == DC21041) ? "DC21041" :
3997 ((lp->chipset == DC21140) ? "DC21140" :
3998 ((lp->chipset == DC21142) ? "DC21142" :
3999 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
4000 )))))));
4001 }
4002 if (lp->chipset != DC21041) {
4003 useSROM = TRUE; /* card is not recognisably DEC */
4004 }
4005 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
4006 useSROM = TRUE;
4007 }
4008
4009 return status;
4010 }
4011
4012 /*
4013 ** Set up the Ethernet PROM counter to the start of the Ethernet address on
4014 ** the DC21040, else read the SROM for the other chips.
4015 ** The SROM may not be present in a multi-MAC card, so first read the
4016 ** MAC address and check for a bad address. If there is a bad one then exit
4017 ** immediately with the prior srom contents intact (the h/w address will
4018 ** be fixed up later).
4019 */
4020 static void
4021 DevicePresent(u_long aprom_addr)
4022 {
4023 int i, j=0;
4024 struct bus_type *lp = &bus;
4025
4026 if (lp->chipset == DC21040) {
4027 if (lp->bus == EISA) {
4028 enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
4029 } else {
4030 outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */
4031 }
4032 } else { /* Read new srom */
4033 u_short tmp, *p = (short *)((char *)&lp->srom + SROM_HWADD);
4034 for (i=0; i<(ETH_ALEN>>1); i++) {
4035 tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
4036 *p = le16_to_cpu(tmp);
4037 j += *p++;
4038 }
4039 if ((j == 0) || (j == 0x2fffd)) {
4040 return;
4041 }
4042
4043 p=(short *)&lp->srom;
4044 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
4045 tmp = srom_rd(aprom_addr, i);
4046 *p++ = le16_to_cpu(tmp);
4047 }
4048 de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
4049 }
4050
4051 return;
4052 }
4053
4054 /*
4055 ** Since the write on the Enet PROM register doesn't seem to reset the PROM
4056 ** pointer correctly (at least on my DE425 EISA card), this routine should do
4057 ** it...from depca.c.
4058 */
4059 static void
4060 enet_addr_rst(u_long aprom_addr)
4061 {
4062 union {
4063 struct {
4064 u32 a;
4065 u32 b;
4066 } llsig;
4067 char Sig[sizeof(u32) << 1];
4068 } dev;
4069 short sigLength=0;
4070 s8 data;
4071 int i, j;
4072
4073 dev.llsig.a = ETH_PROM_SIG;
4074 dev.llsig.b = ETH_PROM_SIG;
4075 sigLength = sizeof(u32) << 1;
4076
4077 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4078 data = inb(aprom_addr);
4079 if (dev.Sig[j] == data) { /* track signature */
4080 j++;
4081 } else { /* lost signature; begin search again */
4082 if (data == dev.Sig[0]) { /* rare case.... */
4083 j=1;
4084 } else {
4085 j=0;
4086 }
4087 }
4088 }
4089
4090 return;
4091 }
4092
4093 /*
4094 ** For the bad status case and no SROM, then add one to the previous
4095 ** address. However, need to add one backwards in case we have 0xff
4096 ** as one or more of the bytes. Only the last 3 bytes should be checked
4097 ** as the first three are invariant - assigned to an organisation.
4098 */
4099 static int
4100 get_hw_addr(struct net_device *dev)
4101 {
4102 u_long iobase = dev->base_addr;
4103 int broken, i, k, tmp, status = 0;
4104 u_short j,chksum;
4105 struct bus_type *lp = &bus;
4106
4107 broken = de4x5_bad_srom(lp);
4108
4109 for (i=0,k=0,j=0;j<3;j++) {
4110 k <<= 1;
4111 if (k > 0xffff) k-=0xffff;
4112
4113 if (lp->bus == PCI) {
4114 if (lp->chipset == DC21040) {
4115 while ((tmp = inl(DE4X5_APROM)) < 0);
4116 k += (u_char) tmp;
4117 dev->dev_addr[i++] = (u_char) tmp;
4118 while ((tmp = inl(DE4X5_APROM)) < 0);
4119 k += (u_short) (tmp << 8);
4120 dev->dev_addr[i++] = (u_char) tmp;
4121 } else if (!broken) {
4122 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4123 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4124 } else if ((broken == SMC) || (broken == ACCTON)) {
4125 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4126 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4127 }
4128 } else {
4129 k += (u_char) (tmp = inb(EISA_APROM));
4130 dev->dev_addr[i++] = (u_char) tmp;
4131 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4132 dev->dev_addr[i++] = (u_char) tmp;
4133 }
4134
4135 if (k > 0xffff) k-=0xffff;
4136 }
4137 if (k == 0xffff) k=0;
4138
4139 if (lp->bus == PCI) {
4140 if (lp->chipset == DC21040) {
4141 while ((tmp = inl(DE4X5_APROM)) < 0);
4142 chksum = (u_char) tmp;
4143 while ((tmp = inl(DE4X5_APROM)) < 0);
4144 chksum |= (u_short) (tmp << 8);
4145 if ((k != chksum) && (dec_only)) status = -1;
4146 }
4147 } else {
4148 chksum = (u_char) inb(EISA_APROM);
4149 chksum |= (u_short) (inb(EISA_APROM) << 8);
4150 if ((k != chksum) && (dec_only)) status = -1;
4151 }
4152
4153 /* If possible, try to fix a broken card - SMC only so far */
4154 srom_repair(dev, broken);
4155
4156 #ifdef CONFIG_PMAC
4157 /*
4158 ** If the address starts with 00 a0, we have to bit-reverse
4159 ** each byte of the address.
4160 */
4161 if (dev->dev_addr[0] == 0 && dev->dev_addr[1] == 0xa0) {
4162 for (i = 0; i < ETH_ALEN; ++i) {
4163 int x = dev->dev_addr[i];
4164 x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4165 x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4166 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4167 }
4168 }
4169 #endif /* CONFIG_PMAC */
4170
4171 /* Test for a bad enet address */
4172 status = test_bad_enet(dev, status);
4173
4174 return status;
4175 }
4176
4177 /*
4178 ** Test for enet addresses in the first 32 bytes. The built-in strncmp
4179 ** didn't seem to work here...?
4180 */
4181 static int
4182 de4x5_bad_srom(struct bus_type *lp)
4183 {
4184 int i, status = 0;
4185
4186 for (i=0; i<sizeof(enet_det)/ETH_ALEN; i++) {
4187 if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4188 !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4189 if (i == 0) {
4190 status = SMC;
4191 } else if (i == 1) {
4192 status = ACCTON;
4193 }
4194 break;
4195 }
4196 }
4197
4198 return status;
4199 }
4200
4201 static int
4202 de4x5_strncmp(char *a, char *b, int n)
4203 {
4204 int ret=0;
4205
4206 for (;n && !ret;n--) {
4207 ret = *a++ - *b++;
4208 }
4209
4210 return ret;
4211 }
4212
4213 static void
4214 srom_repair(struct net_device *dev, int card)
4215 {
4216 struct bus_type *lp = &bus;
4217
4218 switch(card) {
4219 case SMC:
4220 memset((char *)&bus.srom, 0, sizeof(struct de4x5_srom));
4221 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4222 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4223 useSROM = TRUE;
4224 break;
4225 }
4226
4227 return;
4228 }
4229
4230 /*
4231 ** Assume that the irq's do not follow the PCI spec - this is seems
4232 ** to be true so far (2 for 2).
4233 */
4234 static int
4235 test_bad_enet(struct net_device *dev, int status)
4236 {
4237 struct bus_type *lp = &bus;
4238 int i, tmp;
4239
4240 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4241 if ((tmp == 0) || (tmp == 0x5fa)) {
4242 if ((lp->chipset == last.chipset) &&
4243 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4244 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4245 for (i=ETH_ALEN-1; i>2; --i) {
4246 dev->dev_addr[i] += 1;
4247 if (dev->dev_addr[i] != 0) break;
4248 }
4249 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4250 if (!an_exception(lp)) {
4251 dev->irq = last.irq;
4252 }
4253
4254 status = 0;
4255 }
4256 } else if (!status) {
4257 last.chipset = lp->chipset;
4258 last.bus = lp->bus_num;
4259 last.irq = dev->irq;
4260 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4261 }
4262
4263 return status;
4264 }
4265
4266 /*
4267 ** List of board exceptions with correctly wired IRQs
4268 */
4269 static int
4270 an_exception(struct bus_type *lp)
4271 {
4272 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4273 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4274 return -1;
4275 }
4276
4277 return 0;
4278 }
4279
4280 /*
4281 ** SROM Read
4282 */
4283 static short
4284 srom_rd(u_long addr, u_char offset)
4285 {
4286 sendto_srom(SROM_RD | SROM_SR, addr);
4287
4288 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4289 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4290 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4291
4292 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4293 }
4294
4295 static void
4296 srom_latch(u_int command, u_long addr)
4297 {
4298 sendto_srom(command, addr);
4299 sendto_srom(command | DT_CLK, addr);
4300 sendto_srom(command, addr);
4301
4302 return;
4303 }
4304
4305 static void
4306 srom_command(u_int command, u_long addr)
4307 {
4308 srom_latch(command, addr);
4309 srom_latch(command, addr);
4310 srom_latch((command & 0x0000ff00) | DT_CS, addr);
4311
4312 return;
4313 }
4314
4315 static void
4316 srom_address(u_int command, u_long addr, u_char offset)
4317 {
4318 int i;
4319 char a;
4320
4321 a = (char)(offset << 2);
4322 for (i=0; i<6; i++, a <<= 1) {
4323 srom_latch(command | ((a < 0) ? DT_IN : 0), addr);
4324 }
4325 de4x5_us_delay(1);
4326
4327 i = (getfrom_srom(addr) >> 3) & 0x01;
4328
4329 return;
4330 }
4331
4332 static short
4333 srom_data(u_int command, u_long addr)
4334 {
4335 int i;
4336 short word = 0;
4337 s32 tmp;
4338
4339 for (i=0; i<16; i++) {
4340 sendto_srom(command | DT_CLK, addr);
4341 tmp = getfrom_srom(addr);
4342 sendto_srom(command, addr);
4343
4344 word = (word << 1) | ((tmp >> 3) & 0x01);
4345 }
4346
4347 sendto_srom(command & 0x0000ff00, addr);
4348
4349 return word;
4350 }
4351
4352 /*
4353 static void
4354 srom_busy(u_int command, u_long addr)
4355 {
4356 sendto_srom((command & 0x0000ff00) | DT_CS, addr);
4357
4358 while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4359 de4x5_ms_delay(1);
4360 }
4361
4362 sendto_srom(command & 0x0000ff00, addr);
4363
4364 return;
4365 }
4366 */
4367
4368 static void
4369 sendto_srom(u_int command, u_long addr)
4370 {
4371 outl(command, addr);
4372 udelay(1);
4373
4374 return;
4375 }
4376
4377 static int
4378 getfrom_srom(u_long addr)
4379 {
4380 s32 tmp;
4381
4382 tmp = inl(addr);
4383 udelay(1);
4384
4385 return tmp;
4386 }
4387
4388 static int
4389 srom_infoleaf_info(struct net_device *dev)
4390 {
4391 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4392 int i, count;
4393 u_char *p;
4394
4395 /* Find the infoleaf decoder function that matches this chipset */
4396 for (i=0; i<INFOLEAF_SIZE; i++) {
4397 if (lp->chipset == infoleaf_array[i].chipset) break;
4398 }
4399 if (i == INFOLEAF_SIZE) {
4400 lp->useSROM = FALSE;
4401 printk("%s: Cannot find correct chipset for SROM decoding!\n",
4402 dev->name);
4403 return -ENXIO;
4404 }
4405
4406 lp->infoleaf_fn = infoleaf_array[i].fn;
4407
4408 /* Find the information offset that this function should use */
4409 count = *((u_char *)&lp->srom + 19);
4410 p = (u_char *)&lp->srom + 26;
4411
4412 if (count > 1) {
4413 for (i=count; i; --i, p+=3) {
4414 if (lp->device == *p) break;
4415 }
4416 if (i == 0) {
4417 lp->useSROM = FALSE;
4418 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4419 dev->name, lp->device);
4420 return -ENXIO;
4421 }
4422 }
4423
4424 lp->infoleaf_offset = TWIDDLE(p+1);
4425
4426 return 0;
4427 }
4428
4429 /*
4430 ** This routine loads any type 1 or 3 MII info into the mii device
4431 ** struct and executes any type 5 code to reset PHY devices for this
4432 ** controller.
4433 ** The info for the MII devices will be valid since the index used
4434 ** will follow the discovery process from MII address 1-31 then 0.
4435 */
4436 static void
4437 srom_init(struct net_device *dev)
4438 {
4439 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4440 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4441 u_char count;
4442
4443 p+=2;
4444 if (lp->chipset == DC21140) {
4445 lp->cache.gepc = (*p++ | GEP_CTRL);
4446 gep_wr(lp->cache.gepc, dev);
4447 }
4448
4449 /* Block count */
4450 count = *p++;
4451
4452 /* Jump the infoblocks to find types */
4453 for (;count; --count) {
4454 if (*p < 128) {
4455 p += COMPACT_LEN;
4456 } else if (*(p+1) == 5) {
4457 type5_infoblock(dev, 1, p);
4458 p += ((*p & BLOCK_LEN) + 1);
4459 } else if (*(p+1) == 4) {
4460 p += ((*p & BLOCK_LEN) + 1);
4461 } else if (*(p+1) == 3) {
4462 type3_infoblock(dev, 1, p);
4463 p += ((*p & BLOCK_LEN) + 1);
4464 } else if (*(p+1) == 2) {
4465 p += ((*p & BLOCK_LEN) + 1);
4466 } else if (*(p+1) == 1) {
4467 type1_infoblock(dev, 1, p);
4468 p += ((*p & BLOCK_LEN) + 1);
4469 } else {
4470 p += ((*p & BLOCK_LEN) + 1);
4471 }
4472 }
4473
4474 return;
4475 }
4476
4477 /*
4478 ** A generic routine that writes GEP control, data and reset information
4479 ** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4480 */
4481 static void
4482 srom_exec(struct net_device *dev, u_char *p)
4483 {
4484 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4485 u_long iobase = dev->base_addr;
4486 u_char count = (p ? *p++ : 0);
4487 u_short *w = (u_short *)p;
4488
4489 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4490
4491 if (lp->chipset != DC21140) RESET_SIA;
4492
4493 while (count--) {
4494 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4495 *p++ : TWIDDLE(w++)), dev);
4496 mdelay(2); /* 2ms per action */
4497 }
4498
4499 if (lp->chipset != DC21140) {
4500 outl(lp->cache.csr14, DE4X5_STRR);
4501 outl(lp->cache.csr13, DE4X5_SICR);
4502 }
4503
4504 return;
4505 }
4506
4507 /*
4508 ** Basically this function is a NOP since it will never be called,
4509 ** unless I implement the DC21041 SROM functions. There's no need
4510 ** since the existing code will be satisfactory for all boards.
4511 */
4512 static int
4513 dc21041_infoleaf(struct net_device *dev)
4514 {
4515 return DE4X5_AUTOSENSE_MS;
4516 }
4517
4518 static int
4519 dc21140_infoleaf(struct net_device *dev)
4520 {
4521 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4522 u_char count = 0;
4523 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4524 int next_tick = DE4X5_AUTOSENSE_MS;
4525
4526 /* Read the connection type */
4527 p+=2;
4528
4529 /* GEP control */
4530 lp->cache.gepc = (*p++ | GEP_CTRL);
4531
4532 /* Block count */
4533 count = *p++;
4534
4535 /* Recursively figure out the info blocks */
4536 if (*p < 128) {
4537 next_tick = dc_infoblock[COMPACT](dev, count, p);
4538 } else {
4539 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4540 }
4541
4542 if (lp->tcount == count) {
4543 lp->media = NC;
4544 if (lp->media != lp->c_media) {
4545 de4x5_dbg_media(dev);
4546 lp->c_media = lp->media;
4547 }
4548 lp->media = INIT;
4549 lp->tcount = 0;
4550 lp->tx_enable = FALSE;
4551 }
4552
4553 return next_tick & ~TIMER_CB;
4554 }
4555
4556 static int
4557 dc21142_infoleaf(struct net_device *dev)
4558 {
4559 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4560 u_char count = 0;
4561 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4562 int next_tick = DE4X5_AUTOSENSE_MS;
4563
4564 /* Read the connection type */
4565 p+=2;
4566
4567 /* Block count */
4568 count = *p++;
4569
4570 /* Recursively figure out the info blocks */
4571 if (*p < 128) {
4572 next_tick = dc_infoblock[COMPACT](dev, count, p);
4573 } else {
4574 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4575 }
4576
4577 if (lp->tcount == count) {
4578 lp->media = NC;
4579 if (lp->media != lp->c_media) {
4580 de4x5_dbg_media(dev);
4581 lp->c_media = lp->media;
4582 }
4583 lp->media = INIT;
4584 lp->tcount = 0;
4585 lp->tx_enable = FALSE;
4586 }
4587
4588 return next_tick & ~TIMER_CB;
4589 }
4590
4591 static int
4592 dc21143_infoleaf(struct net_device *dev)
4593 {
4594 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4595 u_char count = 0;
4596 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4597 int next_tick = DE4X5_AUTOSENSE_MS;
4598
4599 /* Read the connection type */
4600 p+=2;
4601
4602 /* Block count */
4603 count = *p++;
4604
4605 /* Recursively figure out the info blocks */
4606 if (*p < 128) {
4607 next_tick = dc_infoblock[COMPACT](dev, count, p);
4608 } else {
4609 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4610 }
4611 if (lp->tcount == count) {
4612 lp->media = NC;
4613 if (lp->media != lp->c_media) {
4614 de4x5_dbg_media(dev);
4615 lp->c_media = lp->media;
4616 }
4617 lp->media = INIT;
4618 lp->tcount = 0;
4619 lp->tx_enable = FALSE;
4620 }
4621
4622 return next_tick & ~TIMER_CB;
4623 }
4624
4625 /*
4626 ** The compact infoblock is only designed for DC21140[A] chips, so
4627 ** we'll reuse the dc21140m_autoconf function. Non MII media only.
4628 */
4629 static int
4630 compact_infoblock(struct net_device *dev, u_char count, u_char *p)
4631 {
4632 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4633 u_char flags, csr6;
4634
4635 /* Recursively figure out the info blocks */
4636 if (--count > lp->tcount) {
4637 if (*(p+COMPACT_LEN) < 128) {
4638 return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4639 } else {
4640 return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4641 }
4642 }
4643
4644 if ((lp->media == INIT) && (lp->timeout < 0)) {
4645 lp->ibn = COMPACT;
4646 lp->active = 0;
4647 gep_wr(lp->cache.gepc, dev);
4648 lp->infoblock_media = (*p++) & COMPACT_MC;
4649 lp->cache.gep = *p++;
4650 csr6 = *p++;
4651 flags = *p++;
4652
4653 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4654 lp->defMedium = (flags & 0x40) ? -1 : 0;
4655 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4656 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4657 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4658 lp->useMII = FALSE;
4659
4660 de4x5_switch_mac_port(dev);
4661 }
4662
4663 return dc21140m_autoconf(dev);
4664 }
4665
4666 /*
4667 ** This block describes non MII media for the DC21140[A] only.
4668 */
4669 static int
4670 type0_infoblock(struct net_device *dev, u_char count, u_char *p)
4671 {
4672 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4673 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4674
4675 /* Recursively figure out the info blocks */
4676 if (--count > lp->tcount) {
4677 if (*(p+len) < 128) {
4678 return dc_infoblock[COMPACT](dev, count, p+len);
4679 } else {
4680 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4681 }
4682 }
4683
4684 if ((lp->media == INIT) && (lp->timeout < 0)) {
4685 lp->ibn = 0;
4686 lp->active = 0;
4687 gep_wr(lp->cache.gepc, dev);
4688 p+=2;
4689 lp->infoblock_media = (*p++) & BLOCK0_MC;
4690 lp->cache.gep = *p++;
4691 csr6 = *p++;
4692 flags = *p++;
4693
4694 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4695 lp->defMedium = (flags & 0x40) ? -1 : 0;
4696 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4697 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4698 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4699 lp->useMII = FALSE;
4700
4701 de4x5_switch_mac_port(dev);
4702 }
4703
4704 return dc21140m_autoconf(dev);
4705 }
4706
4707 /* These functions are under construction! */
4708
4709 static int
4710 type1_infoblock(struct net_device *dev, u_char count, u_char *p)
4711 {
4712 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4713 u_char len = (*p & BLOCK_LEN)+1;
4714
4715 /* Recursively figure out the info blocks */
4716 if (--count > lp->tcount) {
4717 if (*(p+len) < 128) {
4718 return dc_infoblock[COMPACT](dev, count, p+len);
4719 } else {
4720 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4721 }
4722 }
4723
4724 p += 2;
4725 if (lp->state == INITIALISED) {
4726 lp->ibn = 1;
4727 lp->active = *p++;
4728 lp->phy[lp->active].gep = (*p ? p : 0); p += (*p + 1);
4729 lp->phy[lp->active].rst = (*p ? p : 0); p += (*p + 1);
4730 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4731 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4732 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4733 lp->phy[lp->active].ttm = TWIDDLE(p);
4734 return 0;
4735 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4736 lp->ibn = 1;
4737 lp->active = *p;
4738 lp->infoblock_csr6 = OMR_MII_100;
4739 lp->useMII = TRUE;
4740 lp->infoblock_media = ANS;
4741
4742 de4x5_switch_mac_port(dev);
4743 }
4744
4745 return dc21140m_autoconf(dev);
4746 }
4747
4748 static int
4749 type2_infoblock(struct net_device *dev, u_char count, u_char *p)
4750 {
4751 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4752 u_char len = (*p & BLOCK_LEN)+1;
4753
4754 /* Recursively figure out the info blocks */
4755 if (--count > lp->tcount) {
4756 if (*(p+len) < 128) {
4757 return dc_infoblock[COMPACT](dev, count, p+len);
4758 } else {
4759 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4760 }
4761 }
4762
4763 if ((lp->media == INIT) && (lp->timeout < 0)) {
4764 lp->ibn = 2;
4765 lp->active = 0;
4766 p += 2;
4767 lp->infoblock_media = (*p) & MEDIA_CODE;
4768
4769 if ((*p++) & EXT_FIELD) {
4770 lp->cache.csr13 = TWIDDLE(p); p += 2;
4771 lp->cache.csr14 = TWIDDLE(p); p += 2;
4772 lp->cache.csr15 = TWIDDLE(p); p += 2;
4773 } else {
4774 lp->cache.csr13 = CSR13;
4775 lp->cache.csr14 = CSR14;
4776 lp->cache.csr15 = CSR15;
4777 }
4778 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4779 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16);
4780 lp->infoblock_csr6 = OMR_SIA;
4781 lp->useMII = FALSE;
4782
4783 de4x5_switch_mac_port(dev);
4784 }
4785
4786 return dc2114x_autoconf(dev);
4787 }
4788
4789 static int
4790 type3_infoblock(struct net_device *dev, u_char count, u_char *p)
4791 {
4792 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4793 u_char len = (*p & BLOCK_LEN)+1;
4794
4795 /* Recursively figure out the info blocks */
4796 if (--count > lp->tcount) {
4797 if (*(p+len) < 128) {
4798 return dc_infoblock[COMPACT](dev, count, p+len);
4799 } else {
4800 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4801 }
4802 }
4803
4804 p += 2;
4805 if (lp->state == INITIALISED) {
4806 lp->ibn = 3;
4807 lp->active = *p++;
4808 if (MOTO_SROM_BUG) lp->active = 0;
4809 lp->phy[lp->active].gep = (*p ? p : 0); p += (2 * (*p) + 1);
4810 lp->phy[lp->active].rst = (*p ? p : 0); p += (2 * (*p) + 1);
4811 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4812 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4813 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4814 lp->phy[lp->active].ttm = TWIDDLE(p); p += 2;
4815 lp->phy[lp->active].mci = *p;
4816 return 0;
4817 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4818 lp->ibn = 3;
4819 lp->active = *p;
4820 lp->infoblock_csr6 = OMR_MII_100;
4821 lp->useMII = TRUE;
4822 lp->infoblock_media = ANS;
4823
4824 de4x5_switch_mac_port(dev);
4825 }
4826
4827 return dc2114x_autoconf(dev);
4828 }
4829
4830 static int
4831 type4_infoblock(struct net_device *dev, u_char count, u_char *p)
4832 {
4833 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4834 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4835
4836 /* Recursively figure out the info blocks */
4837 if (--count > lp->tcount) {
4838 if (*(p+len) < 128) {
4839 return dc_infoblock[COMPACT](dev, count, p+len);
4840 } else {
4841 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4842 }
4843 }
4844
4845 if ((lp->media == INIT) && (lp->timeout < 0)) {
4846 lp->ibn = 4;
4847 lp->active = 0;
4848 p+=2;
4849 lp->infoblock_media = (*p++) & MEDIA_CODE;
4850 lp->cache.csr13 = CSR13; /* Hard coded defaults */
4851 lp->cache.csr14 = CSR14;
4852 lp->cache.csr15 = CSR15;
4853 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4854 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16); p += 2;
4855 csr6 = *p++;
4856 flags = *p++;
4857
4858 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4859 lp->defMedium = (flags & 0x40) ? -1 : 0;
4860 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4861 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4862 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4863 lp->useMII = FALSE;
4864
4865 de4x5_switch_mac_port(dev);
4866 }
4867
4868 return dc2114x_autoconf(dev);
4869 }
4870
4871 /*
4872 ** This block type provides information for resetting external devices
4873 ** (chips) through the General Purpose Register.
4874 */
4875 static int
4876 type5_infoblock(struct net_device *dev, u_char count, u_char *p)
4877 {
4878 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4879 u_char len = (*p & BLOCK_LEN)+1;
4880
4881 /* Recursively figure out the info blocks */
4882 if (--count > lp->tcount) {
4883 if (*(p+len) < 128) {
4884 return dc_infoblock[COMPACT](dev, count, p+len);
4885 } else {
4886 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4887 }
4888 }
4889
4890 /* Must be initializing to run this code */
4891 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4892 p+=2;
4893 lp->rst = p;
4894 srom_exec(dev, lp->rst);
4895 }
4896
4897 return DE4X5_AUTOSENSE_MS;
4898 }
4899
4900 /*
4901 ** MII Read/Write
4902 */
4903
4904 static int
4905 mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4906 {
4907 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4908 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4909 mii_wdata(MII_STRD, 4, ioaddr); /* SFD and Read operation */
4910 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4911 mii_address(phyreg, ioaddr); /* PHY Register to read */
4912 mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */
4913
4914 return mii_rdata(ioaddr); /* Read data */
4915 }
4916
4917 static void
4918 mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4919 {
4920 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4921 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4922 mii_wdata(MII_STWR, 4, ioaddr); /* SFD and Write operation */
4923 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4924 mii_address(phyreg, ioaddr); /* PHY Register to write */
4925 mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */
4926 data = mii_swap(data, 16); /* Swap data bit ordering */
4927 mii_wdata(data, 16, ioaddr); /* Write data */
4928
4929 return;
4930 }
4931
4932 static int
4933 mii_rdata(u_long ioaddr)
4934 {
4935 int i;
4936 s32 tmp = 0;
4937
4938 for (i=0; i<16; i++) {
4939 tmp <<= 1;
4940 tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4941 }
4942
4943 return tmp;
4944 }
4945
4946 static void
4947 mii_wdata(int data, int len, u_long ioaddr)
4948 {
4949 int i;
4950
4951 for (i=0; i<len; i++) {
4952 sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4953 data >>= 1;
4954 }
4955
4956 return;
4957 }
4958
4959 static void
4960 mii_address(u_char addr, u_long ioaddr)
4961 {
4962 int i;
4963
4964 addr = mii_swap(addr, 5);
4965 for (i=0; i<5; i++) {
4966 sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4967 addr >>= 1;
4968 }
4969
4970 return;
4971 }
4972
4973 static void
4974 mii_ta(u_long rw, u_long ioaddr)
4975 {
4976 if (rw == MII_STWR) {
4977 sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
4978 sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
4979 } else {
4980 getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */
4981 }
4982
4983 return;
4984 }
4985
4986 static int
4987 mii_swap(int data, int len)
4988 {
4989 int i, tmp = 0;
4990
4991 for (i=0; i<len; i++) {
4992 tmp <<= 1;
4993 tmp |= (data & 1);
4994 data >>= 1;
4995 }
4996
4997 return tmp;
4998 }
4999
5000 static void
5001 sendto_mii(u32 command, int data, u_long ioaddr)
5002 {
5003 u32 j;
5004
5005 j = (data & 1) << 17;
5006 outl(command | j, ioaddr);
5007 udelay(1);
5008 outl(command | MII_MDC | j, ioaddr);
5009 udelay(1);
5010
5011 return;
5012 }
5013
5014 static int
5015 getfrom_mii(u32 command, u_long ioaddr)
5016 {
5017 outl(command, ioaddr);
5018 udelay(1);
5019 outl(command | MII_MDC, ioaddr);
5020 udelay(1);
5021
5022 return ((inl(ioaddr) >> 19) & 1);
5023 }
5024
5025 /*
5026 ** Here's 3 ways to calculate the OUI from the ID registers.
5027 */
5028 static int
5029 mii_get_oui(u_char phyaddr, u_long ioaddr)
5030 {
5031 /*
5032 union {
5033 u_short reg;
5034 u_char breg[2];
5035 } a;
5036 int i, r2, r3, ret=0;*/
5037 int r2, r3;
5038
5039 /* Read r2 and r3 */
5040 r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
5041 r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
5042 /* SEEQ and Cypress way * /
5043 / * Shuffle r2 and r3 * /
5044 a.reg=0;
5045 r3 = ((r3>>10)|(r2<<6))&0x0ff;
5046 r2 = ((r2>>2)&0x3fff);
5047
5048 / * Bit reverse r3 * /
5049 for (i=0;i<8;i++) {
5050 ret<<=1;
5051 ret |= (r3&1);
5052 r3>>=1;
5053 }
5054
5055 / * Bit reverse r2 * /
5056 for (i=0;i<16;i++) {
5057 a.reg<<=1;
5058 a.reg |= (r2&1);
5059 r2>>=1;
5060 }
5061
5062 / * Swap r2 bytes * /
5063 i=a.breg[0];
5064 a.breg[0]=a.breg[1];
5065 a.breg[1]=i;
5066
5067 return ((a.reg<<8)|ret); */ /* SEEQ and Cypress way */
5068 /* return ((r2<<6)|(u_int)(r3>>10)); */ /* NATIONAL and BROADCOM way */
5069 return r2; /* (I did it) My way */
5070 }
5071
5072 /*
5073 ** The SROM spec forces us to search addresses [1-31 0]. Bummer.
5074 */
5075 static int
5076 mii_get_phy(struct net_device *dev)
5077 {
5078 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5079 u_long iobase = dev->base_addr;
5080 int i, j, k, n, limit=sizeof(phy_info)/sizeof(struct phy_table);
5081 int id;
5082
5083 lp->active = 0;
5084 lp->useMII = TRUE;
5085
5086 /* Search the MII address space for possible PHY devices */
5087 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(++i)%DE4X5_MAX_MII) {
5088 lp->phy[lp->active].addr = i;
5089 if (i==0) n++; /* Count cycles */
5090 while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
5091 id = mii_get_oui(i, DE4X5_MII);
5092 if ((id == 0) || (id == 65535)) continue; /* Valid ID? */
5093 for (j=0; j<limit; j++) { /* Search PHY table */
5094 if (id != phy_info[j].id) continue; /* ID match? */
5095 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5096 if (k < DE4X5_MAX_PHY) {
5097 memcpy((char *)&lp->phy[k],
5098 (char *)&phy_info[j], sizeof(struct phy_table));
5099 lp->phy[k].addr = i;
5100 lp->mii_cnt++;
5101 lp->active++;
5102 } else {
5103 goto purgatory; /* Stop the search */
5104 }
5105 break;
5106 }
5107 if ((j == limit) && (i < DE4X5_MAX_MII)) {
5108 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5109 lp->phy[k].addr = i;
5110 lp->phy[k].id = id;
5111 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */
5112 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */
5113 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */
5114 lp->mii_cnt++;
5115 lp->active++;
5116 printk("%s: Using generic MII device control. If the board doesn't operate, \nplease mail the following dump to the author:\n", dev->name);
5117 j = de4x5_debug;
5118 de4x5_debug |= DEBUG_MII;
5119 de4x5_dbg_mii(dev, k);
5120 de4x5_debug = j;
5121 printk("\n");
5122 }
5123 }
5124 purgatory:
5125 lp->active = 0;
5126 if (lp->phy[0].id) { /* Reset the PHY devices */
5127 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++) { /*For each PHY*/
5128 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5129 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5130
5131 de4x5_dbg_mii(dev, k);
5132 }
5133 }
5134 if (!lp->mii_cnt) lp->useMII = FALSE;
5135
5136 return lp->mii_cnt;
5137 }
5138
5139 static char *
5140 build_setup_frame(struct net_device *dev, int mode)
5141 {
5142 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5143 int i;
5144 char *pa = lp->setup_frame;
5145
5146 /* Initialise the setup frame */
5147 if (mode == ALL) {
5148 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5149 }
5150
5151 if (lp->setup_f == HASH_PERF) {
5152 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5153 *(pa + i) = dev->dev_addr[i]; /* Host address */
5154 if (i & 0x01) pa += 2;
5155 }
5156 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5157 } else {
5158 for (i=0; i<ETH_ALEN; i++) { /* Host address */
5159 *(pa + (i&1)) = dev->dev_addr[i];
5160 if (i & 0x01) pa += 4;
5161 }
5162 for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5163 *(pa + (i&1)) = (char) 0xff;
5164 if (i & 0x01) pa += 4;
5165 }
5166 }
5167
5168 return pa; /* Points to the next entry */
5169 }
5170
5171 static void
5172 enable_ast(struct net_device *dev, u32 time_out)
5173 {
5174 timeout(dev, (void *)&de4x5_ast, (u_long)dev, time_out);
5175
5176 return;
5177 }
5178
5179 static void
5180 disable_ast(struct net_device *dev)
5181 {
5182 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5183
5184 del_timer(&lp->timer);
5185
5186 return;
5187 }
5188
5189 static long
5190 de4x5_switch_mac_port(struct net_device *dev)
5191 {
5192 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5193 u_long iobase = dev->base_addr;
5194 s32 omr;
5195
5196 STOP_DE4X5;
5197
5198 /* Assert the OMR_PS bit in CSR6 */
5199 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5200 OMR_FDX));
5201 omr |= lp->infoblock_csr6;
5202 if (omr & OMR_PS) omr |= OMR_HBD;
5203 outl(omr, DE4X5_OMR);
5204
5205 /* Soft Reset */
5206 RESET_DE4X5;
5207
5208 /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5209 if (lp->chipset == DC21140) {
5210 gep_wr(lp->cache.gepc, dev);
5211 gep_wr(lp->cache.gep, dev);
5212 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5213 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5214 }
5215
5216 /* Restore CSR6 */
5217 outl(omr, DE4X5_OMR);
5218
5219 /* Reset CSR8 */
5220 inl(DE4X5_MFC);
5221
5222 return omr;
5223 }
5224
5225 static void
5226 gep_wr(s32 data, struct net_device *dev)
5227 {
5228 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5229 u_long iobase = dev->base_addr;
5230
5231 if (lp->chipset == DC21140) {
5232 outl(data, DE4X5_GEP);
5233 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5234 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5235 }
5236
5237 return;
5238 }
5239
5240 static int
5241 gep_rd(struct net_device *dev)
5242 {
5243 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5244 u_long iobase = dev->base_addr;
5245
5246 if (lp->chipset == DC21140) {
5247 return inl(DE4X5_GEP);
5248 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5249 return (inl(DE4X5_SIGR) & 0x000fffff);
5250 }
5251
5252 return 0;
5253 }
5254
5255 static void
5256 timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec)
5257 {
5258 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5259 int dt;
5260
5261 /* First, cancel any pending timer events */
5262 del_timer(&lp->timer);
5263
5264 /* Convert msec to ticks */
5265 dt = (msec * HZ) / 1000;
5266 if (dt==0) dt=1;
5267
5268 /* Set up timer */
5269 lp->timer.expires = jiffies + dt;
5270 lp->timer.function = fn;
5271 lp->timer.data = data;
5272 add_timer(&lp->timer);
5273
5274 return;
5275 }
5276
5277 static void
5278 yawn(struct net_device *dev, int state)
5279 {
5280 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5281 u_long iobase = dev->base_addr;
5282
5283 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5284
5285 if(lp->bus == EISA) {
5286 switch(state) {
5287 case WAKEUP:
5288 outb(WAKEUP, PCI_CFPM);
5289 de4x5_ms_delay(10);
5290 break;
5291
5292 case SNOOZE:
5293 outb(SNOOZE, PCI_CFPM);
5294 break;
5295
5296 case SLEEP:
5297 outl(0, DE4X5_SICR);
5298 outb(SLEEP, PCI_CFPM);
5299 break;
5300 }
5301 } else {
5302 switch(state) {
5303 case WAKEUP:
5304 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5305 PCI_CFDA_PSM, WAKEUP);
5306 de4x5_ms_delay(10);
5307 break;
5308
5309 case SNOOZE:
5310 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5311 PCI_CFDA_PSM, SNOOZE);
5312 break;
5313
5314 case SLEEP:
5315 outl(0, DE4X5_SICR);
5316 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5317 PCI_CFDA_PSM, SLEEP);
5318 break;
5319 }
5320 }
5321
5322 return;
5323 }
5324
5325 static void
5326 de4x5_parse_params(struct net_device *dev)
5327 {
5328 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5329 char *p, *q, t;
5330
5331 lp->params.fdx = 0;
5332 lp->params.autosense = AUTO;
5333
5334 if (args == NULL) return;
5335
5336 if ((p = strstr(args, dev->name))) {
5337 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5338 t = *q;
5339 *q = '\0';
5340
5341 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
5342 if (strstr(p, "force_eisa") || strstr(p, "FORCE_EISA")) forceEISA = 1;
5343 #endif
5344 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1;
5345
5346 if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5347 if (strstr(p, "TP")) {
5348 lp->params.autosense = TP;
5349 } else if (strstr(p, "TP_NW")) {
5350 lp->params.autosense = TP_NW;
5351 } else if (strstr(p, "BNC")) {
5352 lp->params.autosense = BNC;
5353 } else if (strstr(p, "AUI")) {
5354 lp->params.autosense = AUI;
5355 } else if (strstr(p, "BNC_AUI")) {
5356 lp->params.autosense = BNC;
5357 } else if (strstr(p, "10Mb")) {
5358 lp->params.autosense = _10Mb;
5359 } else if (strstr(p, "100Mb")) {
5360 lp->params.autosense = _100Mb;
5361 } else if (strstr(p, "AUTO")) {
5362 lp->params.autosense = AUTO;
5363 }
5364 }
5365 *q = t;
5366 }
5367
5368 return;
5369 }
5370
5371 static void
5372 de4x5_dbg_open(struct net_device *dev)
5373 {
5374 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5375 int i;
5376
5377 if (de4x5_debug & DEBUG_OPEN) {
5378 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5379 printk("\tphysical address: ");
5380 for (i=0;i<6;i++) {
5381 printk("%2.2x:",(short)dev->dev_addr[i]);
5382 }
5383 printk("\n");
5384 printk("Descriptor head addresses:\n");
5385 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5386 printk("Descriptor addresses:\nRX: ");
5387 for (i=0;i<lp->rxRingSize-1;i++){
5388 if (i < 3) {
5389 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5390 }
5391 }
5392 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5393 printk("TX: ");
5394 for (i=0;i<lp->txRingSize-1;i++){
5395 if (i < 3) {
5396 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5397 }
5398 }
5399 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5400 printk("Descriptor buffers:\nRX: ");
5401 for (i=0;i<lp->rxRingSize-1;i++){
5402 if (i < 3) {
5403 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5404 }
5405 }
5406 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5407 printk("TX: ");
5408 for (i=0;i<lp->txRingSize-1;i++){
5409 if (i < 3) {
5410 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5411 }
5412 }
5413 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5414 printk("Ring size: \nRX: %d\nTX: %d\n",
5415 (short)lp->rxRingSize,
5416 (short)lp->txRingSize);
5417 }
5418
5419 return;
5420 }
5421
5422 static void
5423 de4x5_dbg_mii(struct net_device *dev, int k)
5424 {
5425 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5426 u_long iobase = dev->base_addr;
5427
5428 if (de4x5_debug & DEBUG_MII) {
5429 printk("\nMII device address: %d\n", lp->phy[k].addr);
5430 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5431 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5432 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5433 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5434 if (lp->phy[k].id != BROADCOM_T4) {
5435 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5436 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5437 }
5438 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5439 if (lp->phy[k].id != BROADCOM_T4) {
5440 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5441 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5442 } else {
5443 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5444 }
5445 }
5446
5447 return;
5448 }
5449
5450 static void
5451 de4x5_dbg_media(struct net_device *dev)
5452 {
5453 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5454
5455 if (lp->media != lp->c_media) {
5456 if (de4x5_debug & DEBUG_MEDIA) {
5457 printk("%s: media is %s%s\n", dev->name,
5458 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5459 (lp->media == TP ? "TP" :
5460 (lp->media == ANS ? "TP/Nway" :
5461 (lp->media == BNC ? "BNC" :
5462 (lp->media == AUI ? "AUI" :
5463 (lp->media == BNC_AUI ? "BNC/AUI" :
5464 (lp->media == EXT_SIA ? "EXT SIA" :
5465 (lp->media == _100Mb ? "100Mb/s" :
5466 (lp->media == _10Mb ? "10Mb/s" :
5467 "???"
5468 ))))))))), (lp->fdx?" full duplex.":"."));
5469 }
5470 lp->c_media = lp->media;
5471 }
5472
5473 return;
5474 }
5475
5476 static void
5477 de4x5_dbg_srom(struct de4x5_srom *p)
5478 {
5479 int i;
5480
5481 if (de4x5_debug & DEBUG_SROM) {
5482 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5483 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
5484 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
5485 printk("SROM version: %02x\n", (u_char)(p->version));
5486 printk("# controllers: %02x\n", (u_char)(p->num_controllers));
5487
5488 printk("Hardware Address: ");
5489 for (i=0;i<ETH_ALEN-1;i++) {
5490 printk("%02x:", (u_char)*(p->ieee_addr+i));
5491 }
5492 printk("%02x\n", (u_char)*(p->ieee_addr+i));
5493 printk("CRC checksum: %04x\n", (u_short)(p->chksum));
5494 for (i=0; i<64; i++) {
5495 printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5496 }
5497 }
5498
5499 return;
5500 }
5501
5502 static void
5503 de4x5_dbg_rx(struct sk_buff *skb, int len)
5504 {
5505 int i, j;
5506
5507 if (de4x5_debug & DEBUG_RX) {
5508 printk("R: %02x:%02x:%02x:%02x:%02x:%02x <- %02x:%02x:%02x:%02x:%02x:%02x len/SAP:%02x%02x [%d]\n",
5509 (u_char)skb->data[0],
5510 (u_char)skb->data[1],
5511 (u_char)skb->data[2],
5512 (u_char)skb->data[3],
5513 (u_char)skb->data[4],
5514 (u_char)skb->data[5],
5515 (u_char)skb->data[6],
5516 (u_char)skb->data[7],
5517 (u_char)skb->data[8],
5518 (u_char)skb->data[9],
5519 (u_char)skb->data[10],
5520 (u_char)skb->data[11],
5521 (u_char)skb->data[12],
5522 (u_char)skb->data[13],
5523 len);
5524 if (de4x5_debug & DEBUG_RX) {
5525 for (j=0; len>0;j+=16, len-=16) {
5526 printk(" %03x: ",j);
5527 for (i=0; i<16 && i<len; i++) {
5528 printk("%02x ",(u_char)skb->data[i+j]);
5529 }
5530 printk("\n");
5531 }
5532 }
5533 }
5534
5535 return;
5536 }
5537
5538 /*
5539 ** Perform IOCTL call functions here. Some are privileged operations and the
5540 ** effective uid is checked in those cases. In the normal course of events
5541 ** this function is only used for my testing.
5542 */
5543 static int
5544 de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5545 {
5546 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5547 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_data;
5548 u_long iobase = dev->base_addr;
5549 int i, j, status = 0;
5550 s32 omr;
5551 union {
5552 u8 addr[144];
5553 u16 sval[72];
5554 u32 lval[36];
5555 } tmp;
5556 u_long flags = 0;
5557
5558 switch(ioc->cmd) {
5559 case DE4X5_GET_HWADDR: /* Get the hardware address */
5560 ioc->len = ETH_ALEN;
5561 for (i=0; i<ETH_ALEN; i++) {
5562 tmp.addr[i] = dev->dev_addr[i];
5563 }
5564 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5565 break;
5566
5567 case DE4X5_SET_HWADDR: /* Set the hardware address */
5568 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5569 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5570 for (i=0; i<ETH_ALEN; i++) {
5571 dev->dev_addr[i] = tmp.addr[i];
5572 }
5573 build_setup_frame(dev, PHYS_ADDR_ONLY);
5574 /* Set up the descriptor and give ownership to the card */
5575 while (test_and_set_bit(0, (void *)&dev->tbusy) != 0) barrier();
5576 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5577 SETUP_FRAME_LEN, NULL);
5578 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
5579 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
5580 dev->tbusy = 0; /* Unlock the TX ring */
5581 break;
5582
5583 case DE4X5_SET_PROM: /* Set Promiscuous Mode */
5584 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5585 omr = inl(DE4X5_OMR);
5586 omr |= OMR_PR;
5587 outl(omr, DE4X5_OMR);
5588 dev->flags |= IFF_PROMISC;
5589 break;
5590
5591 case DE4X5_CLR_PROM: /* Clear Promiscuous Mode */
5592 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5593 omr = inl(DE4X5_OMR);
5594 omr &= ~OMR_PR;
5595 outb(omr, DE4X5_OMR);
5596 dev->flags &= ~IFF_PROMISC;
5597 break;
5598
5599 case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */
5600 printk("%s: Boo!\n", dev->name);
5601 break;
5602
5603 case DE4X5_MCA_EN: /* Enable pass all multicast addressing */
5604 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5605 omr = inl(DE4X5_OMR);
5606 omr |= OMR_PM;
5607 outl(omr, DE4X5_OMR);
5608 break;
5609
5610 case DE4X5_GET_STATS: /* Get the driver statistics */
5611 ioc->len = sizeof(lp->pktStats);
5612 spin_lock_irqsave(&lp->lock, flags);
5613 if (copy_to_user(ioc->data, &lp->pktStats, ioc->len)) return -EFAULT;
5614 spin_unlock_irqrestore(&lp->lock, flags);
5615 break;
5616
5617 case DE4X5_CLR_STATS: /* Zero out the driver statistics */
5618 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5619 spin_lock_irqsave(&lp->lock, flags);
5620 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5621 spin_unlock_irqrestore(&lp->lock, flags);
5622 break;
5623
5624 case DE4X5_GET_OMR: /* Get the OMR Register contents */
5625 tmp.addr[0] = inl(DE4X5_OMR);
5626 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5627 break;
5628
5629 case DE4X5_SET_OMR: /* Set the OMR Register contents */
5630 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5631 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5632 outl(tmp.addr[0], DE4X5_OMR);
5633 break;
5634
5635 case DE4X5_GET_REG: /* Get the DE4X5 Registers */
5636 j = 0;
5637 tmp.lval[0] = inl(DE4X5_STS); j+=4;
5638 tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5639 tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5640 tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5641 tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5642 tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5643 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5644 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5645 ioc->len = j;
5646 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5647 break;
5648
5649 #define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
5650 /*
5651 case DE4X5_DUMP:
5652 j = 0;
5653 tmp.addr[j++] = dev->irq;
5654 for (i=0; i<ETH_ALEN; i++) {
5655 tmp.addr[j++] = dev->dev_addr[i];
5656 }
5657 tmp.addr[j++] = lp->rxRingSize;
5658 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5659 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5660
5661 for (i=0;i<lp->rxRingSize-1;i++){
5662 if (i < 3) {
5663 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5664 }
5665 }
5666 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5667 for (i=0;i<lp->txRingSize-1;i++){
5668 if (i < 3) {
5669 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5670 }
5671 }
5672 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5673
5674 for (i=0;i<lp->rxRingSize-1;i++){
5675 if (i < 3) {
5676 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5677 }
5678 }
5679 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5680 for (i=0;i<lp->txRingSize-1;i++){
5681 if (i < 3) {
5682 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5683 }
5684 }
5685 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5686
5687 for (i=0;i<lp->rxRingSize;i++){
5688 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5689 }
5690 for (i=0;i<lp->txRingSize;i++){
5691 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5692 }
5693
5694 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
5695 tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
5696 tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
5697 tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5698 tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5699 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
5700 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
5701 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
5702 tmp.lval[j>>2] = lp->chipset; j+=4;
5703 if (lp->chipset == DC21140) {
5704 tmp.lval[j>>2] = gep_rd(dev); j+=4;
5705 } else {
5706 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5707 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5708 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5709 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5710 }
5711 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5712 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5713 tmp.lval[j>>2] = lp->active; j+=4;
5714 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5715 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5716 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5717 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5718 if (lp->phy[lp->active].id != BROADCOM_T4) {
5719 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5720 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5721 }
5722 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5723 if (lp->phy[lp->active].id != BROADCOM_T4) {
5724 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5725 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5726 } else {
5727 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5728 }
5729 }
5730
5731 tmp.addr[j++] = lp->txRingSize;
5732 tmp.addr[j++] = dev->tbusy;
5733
5734 ioc->len = j;
5735 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5736 break;
5737
5738 */
5739 default:
5740 return -EOPNOTSUPP;
5741 }
5742
5743 return status;
5744 }
5745
5746 #ifdef MODULE
5747 /*
5748 ** Note now that module autoprobing is allowed under EISA and PCI. The
5749 ** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
5750 ** to "do the right thing".
5751 */
5752 #define LP(a) ((struct de4x5_private *)(a))
5753 static struct net_device *mdev = NULL;
5754 static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */
5755 MODULE_PARM(io, "i");
5756
5757 int
5758 init_module(void)
5759 {
5760 int i, num, status = -EIO;
5761 struct net_device *p;
5762
5763 num = count_adapters();
5764
5765 for (i=0; i<num; i++) {
5766 if ((p = insert_device(NULL, io, de4x5_probe)) == NULL)
5767 return -ENOMEM;
5768
5769 if (!mdev) mdev = p;
5770
5771 if (register_netdev(p) != 0) {
5772 struct de4x5_private *lp = (struct de4x5_private *)p->priv;
5773 if (lp) {
5774 release_region(p->base_addr, (lp->bus == PCI ?
5775 DE4X5_PCI_TOTAL_SIZE :
5776 DE4X5_EISA_TOTAL_SIZE));
5777 if (lp->cache.buf) { /* MAC buffers allocated? */
5778 kfree(lp->cache.buf); /* Free the MAC buffers */
5779 }
5780 if (lp->cache.priv) { /* Private area allocated? */
5781 kfree(lp->cache.priv); /* Free the private area */
5782 }
5783 }
5784 kfree(p);
5785 } else {
5786 status = 0; /* At least one adapter will work */
5787 lastModule = p;
5788 }
5789 }
5790
5791 return status;
5792 }
5793
5794 void
5795 cleanup_module(void)
5796 {
5797 while (mdev != NULL) {
5798 mdev = unlink_modules(mdev);
5799 }
5800
5801 return;
5802 }
5803
5804 static struct net_device *
5805 unlink_modules(struct net_device *p)
5806 {
5807 struct net_device *next = NULL;
5808
5809 if (p->priv) { /* Private areas allocated? */
5810 struct de4x5_private *lp = (struct de4x5_private *)p->priv;
5811
5812 next = lp->next_module;
5813 if (lp->cache.buf) { /* MAC buffers allocated? */
5814 kfree(lp->cache.buf); /* Free the MAC buffers */
5815 }
5816 release_region(p->base_addr, (lp->bus == PCI ?
5817 DE4X5_PCI_TOTAL_SIZE :
5818 DE4X5_EISA_TOTAL_SIZE));
5819 kfree(lp->cache.priv); /* Free the private area */
5820 }
5821 unregister_netdev(p);
5822 kfree(p); /* Free the device structure */
5823
5824 return next;
5825 }
5826
5827 static int
5828 count_adapters(void)
5829 {
5830 int i, j=0;
5831 u_short vendor;
5832 u_int class = DE4X5_CLASS_CODE;
5833 u_int device;
5834
5835 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
5836 char name[DE4X5_STRLEN];
5837 u_long iobase = 0x1000;
5838
5839 for (i=1; i<MAX_EISA_SLOTS; i++, iobase+=EISA_SLOT_INC) {
5840 if (EISA_signature(name, EISA_ID)) j++;
5841 }
5842 #endif
5843 if (!pcibios_present()) return j;
5844
5845 for (i=0; (pdev=pci_find_class(class, pdev))!= NULL; i++) {
5846 vendor = pdev->vendor;
5847 device = pdev->device << 8;
5848 if (is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x) j++;
5849 }
5850
5851 return j;
5852 }
5853
5854 /*
5855 ** If at end of eth device list and can't use current entry, malloc
5856 ** one up. If memory could not be allocated, print an error message.
5857 */
5858 static struct net_device * __init
5859 insert_device(struct net_device *dev, u_long iobase, int (*init)(struct net_device *))
5860 {
5861 struct net_device *new;
5862
5863 new = (struct net_device *)kmalloc(sizeof(struct net_device)+8, GFP_KERNEL);
5864 if (new == NULL) {
5865 printk("de4x5.c: Device not initialised, insufficient memory\n");
5866 return NULL;
5867 } else {
5868 memset((char *)new, 0, sizeof(struct net_device)+8);
5869 new->name = (char *)(new + 1);
5870 new->base_addr = iobase; /* assign the io address */
5871 new->init = init; /* initialisation routine */
5872 }
5873
5874 return new;
5875 }
5876
5877 #endif /* MODULE */
5878
5879 \f
5880 /*
5881 * Local variables:
5882 * compile-command: "gcc -D__KERNEL__ -I/linux/include -Wall -Wstrict-prototypes -fomit-frame-pointer -fno-strength-reduce -malign-loops=2 -malign-jumps=2 -malign-functions=2 -O2 -m486 -c de4x5.c"
5883 *
5884 * Delete -D__SMP__ below if you didn't define this in your kernel
5885 * Delete -DMODVERSIONS below if you didn't define this in your kernel
5886 *
5887 * compile-command: "gcc -D__KERNEL__ -DMODULE -I/linux/include -Wall -Wstrict-prototypes -fomit-frame-pointer -fno-strength-reduce -malign-loops=2 -malign-jumps=2 -malign-functions=2 -O2 -m486 -DMODVERSIONS -include /linux/include/linux/modversions.h -c de4x5.c"
5888 * End:
5889 */