drivers/dec21140A/dec21140A.h

   1 #ifndef INCL_DEC21041_H_GUARD
   2 #define INCL_DEC21041_H_GUARD
   3 /*
   4 de.h
   5
   6 Header for the driver of the DEC 21140A ethernet card as emulated
   7 by VirtualPC 2007
   8
   9 Created: 09/01/2009   Nicolas Tittley (first.last @ gmail DOT com)
  10 */
  11
  12
  13 #define DE_FKEY 8  /* Shitf+ this value will dump info on console */
  14
  15 #undef  NULL
  16 #define NULL ((void *)0)
  17 #define NOT(x) (~(x))
  18
  19 #if debug == 1
  20 #       define DEBUG(statm) statm
  21 #else
  22 #       define DEBUG(statm)
  23 #endif
  24
  25
  26 #define SA_ADDR_LEN     sizeof(ether_addr_t)
  27
  28 #define DE_NB_SEND_DESCR    32
  29 #define DE_SEND_BUF_SIZE    (ETH_MAX_PACK_SIZE+2)
  30 #define DE_NB_RECV_DESCR    32
  31 #define DE_RECV_BUF_SIZE    (ETH_MAX_PACK_SIZE+2)
  32 #define IOVEC_NR            16
  33 #define DE_MIN_BASE_ADDR    0x0400
  34 #define DE_SROM_EA_OFFSET   20
  35 #define DE_SETUP_FRAME_SIZE 192
  36 #define DEC21140A_VID       0x1011
  37 #define DEC21140A_DID       0x0009
  38
  39
  40 typedef struct iovec_dat_s {
  41   iovec_s_t iod_iovec[IOVEC_NR];
  42   int iod_iovec_s;
  43   int iod_proc_nr;
  44   cp_grant_id_t iod_grant;
  45   vir_bytes iod_iovec_offset;
  46 } iovec_dat_s_t;
  47
  48 typedef struct de_descr {
  49   u32_t des[4];
  50 } de_descr_t;
  51
  52 typedef struct de_local_descr {
  53   de_descr_t *descr;
  54   u8_t *buf1;
  55   u8_t *buf2;
  56 } de_loc_descr_t;
  57
  58 typedef struct dpeth {
  59
  60   message rx_return_msg;        /* Holds VREAD message until int */
  61   message tx_return_msg;        /* Holds VWRITE message until int */
  62   char de_name[32];              /* Name of this interface */
  63   port_t de_base_port;          /* Base port, for multiple card instance */
  64   int de_irq;                   /* IRQ line number */
  65   int de_hook;                  /* interrupt hook at kernel */
  66
  67   int de_type;                  /* What kind of hardware */
  68
  69   ether_addr_t de_address;      /* Ethernet Address */
  70   eth_stat_t de_stat;           /* Stats */
  71   unsigned long bytes_tx;       /* Number of bytes sent */
  72   unsigned long bytes_rx;       /* Number of bytes recv */
  73
  74   /* Space reservation. We will allocate all structures later in the code.
  75      here we just make sure we have the space we need at compile time */
  76   u8_t sendrecv_descr_buf[(DE_NB_SEND_DESCR+DE_NB_RECV_DESCR)*
  77                           sizeof(de_descr_t)];
  78   u8_t sendrecv_buf[DE_NB_SEND_DESCR*DE_SEND_BUF_SIZE +
  79                     DE_NB_RECV_DESCR*DE_RECV_BUF_SIZE];
  80   phys_bytes sendrecv_descr_phys_addr[2];
  81   de_loc_descr_t descr[2][MAX(DE_NB_RECV_DESCR, DE_NB_SEND_DESCR)];
  82   int cur_descr[2];
  83
  84 #define DESCR_RECV 0
  85 #define DESCR_TRAN 1
  86
  87   int de_flags;                 /* Send/Receive mode (Configuration) */
  88
  89 #define DEF_EMPTY       0x0000
  90 #define DEF_READING     0x0001
  91 #define DEF_RECV_BUSY   0x0002
  92 #define DEF_ACK_RECV    0x0004
  93 #define DEF_SENDING     0x0010
  94 #define DEF_XMIT_BUSY   0x0020
  95 #define DEF_ACK_SEND    0x0040
  96 #define DEF_PROMISC     0x0100
  97 #define DEF_MULTI       0x0200
  98 #define DEF_BROAD       0x0400
  99 #define DEF_ENABLED     0x2000
 100 #define DEF_STOPPED     0x4000
 101
 102   int de_mode;                  /* Status of the Interface */
 103
 104 #define DEM_DISABLED    0x0000
 105 #define DEM_SINK        0x0001
 106 #define DEM_ENABLED     0x0002
 107
 108
 109   /* Serial ROM */
 110 #define SROM_BITWIDTH 6
 111
 112   u8_t srom[((1<<SROM_BITWIDTH)-1)*2];    /* Space to read in
 113                                              all the configuration ROM */
 114
 115
 116   /* Temporary storage for RECV/SEND requests */
 117   iovec_dat_s_t de_read_iovec;
 118   iovec_dat_s_t de_write_iovec;
 119   vir_bytes de_read_s;
 120   vir_bytes de_send_s;
 121   endpoint_t de_client;
 122
 123 } dpeth_t;
 124
 125
 126 /************/
 127 /* Revisons */
 128 /************/
 129
 130 #define DEC_21140A 0x20
 131 #define DE_TYPE_UNKNOWN 0x0
 132 /* #define CSR_ADDR(x, i) csraddr2(x->de_base_port + i) */
 133 #define CSR_ADDR(x, i) (x->de_base_port + i)
 134
 135 /* CSRs */
 136 #define CSR0 0x00
 137 #define     CSR0_SWR   0x00000001 /* sw reset */
 138 #define     CSR0_BAR   0x00000002 /* bus arbitration */
 139 #define     CSR0_CAL_8 0x00004000 /* cache align 8 long word */
 140 #define     CSR0_TAP   0x00080000 /* trans auto polling */
 141 #define CSR1 0x08 /* transmit poll demand */
 142 #define CSR2 0x10 /* receive poll demand */
 143 #define CSR3 0x18 /* receive list address */
 144 #define CSR4 0x20 /* transmit list address */
 145 #define CSR5 0x28              /* status register */
 146 #define     CSR5_EB  0x03800000 /* error bits */
 147 #define     CSR5_TS  0x00700000 /* Transmit proc state */
 148 #define     CSR5_RS  0x000E0000 /* Receive proc state */
 149 #define     CSR5_NIS 0x00010000 /* Norm Int summ */
 150 #define     CSR5_AIS 0x00008000 /* Abnorm Int sum */
 151 #define     CSR5_FBE 0x00002000 /* Fatal bit error */
 152 #define     CSR5_GTE 0x00000800 /* Gen-purp timer exp */
 153 #define     CSR5_ETI 0x00000400 /* Early Trans int */
 154 #define     CSR5_RWT 0x00000200 /* Recv watchdog timeout */
 155 #define     CSR5_RPS 0x00000100 /* Recv proc stop */
 156 #define     CSR5_RU  0x00000080 /* Recv buf unavail */
 157 #define     CSR5_RI  0x00000040 /* Recv interrupt */
 158 #define     CSR5_UNF 0x00000020 /* Trans underflow */
 159 #define     CSR5_TJT 0x00000008 /* Trans Jabber Timeout */
 160 #define     CSR5_TU  0x00000004 /* Trans buf unavail */
 161 #define     CSR5_TPS 0x00000002 /* Trans proc stopped */
 162 #define     CSR5_TI  0x00000001 /* Trans interrupt */
 163 #define CSR6 0x30 /* Operation mode */
 164 #define     CSR6_SC  0x80000000 /* Special capt effect ena 31 */
 165 #define     CSR6_RA  0x40000000 /* receive all 30 */
 166 #define     CSR6_MBO 0x02000000 /* must be one 25 */
 167 #define     CSR6_SCR 0x01000000 /* Scrambler mode 24 */
 168 #define     CSR6_PCS 0x00800000 /* PCS function 23 */
 169 #define     CSR6_TTM 0x00400000 /* Trans threshold mode 22 */
 170 #define     CSR6_SF  0x00200000 /* store and forward 21 */
 171 #define     CSR6_HBD 0x00080000 /* Heartbeat disable 19 */
 172 #define     CSR6_PS  0x00040000 /* port select 18 */
 173 #define     CSR6_CA  0x00020000 /* Capt effect ena 17 */
 174 #define     CSR6_TR_00 0x00000000 /* Trans thresh 15:14 */
 175 #define     CSR6_TR_01 0x00004000 /* Trans thresh 15:14 */
 176 #define     CSR6_TR_10 0x00008000 /* Trans thresh 15:14 */
 177 #define     CSR6_TR_11 0x0000C000 /* Trans thresh 15:14 */
 178 #define     CSR6_ST  0x00002000 /* start/stop trans 13 */
 179 #define     CSR6_FD  0x00000200 /* Full Duplex 9 */
 180 #define     CSR6_PM  0x00000080 /* Pass all multicast 7 */
 181 #define     CSR6_PR  0x00000040 /* Promisc mode 6 */
 182 #define     CSR6_IF  0x00000010 /* Inv filtering 4 */
 183 #define     CSR6_HO  0x00000004 /* Hash-only filtering 2 */
 184 #define     CSR6_SR  0x00000002 /* start/stop recv 1 */
 185 #define     CSR6_HP  0x00000001 /* Hash/perfect recv filt mode 0 */
 186 #define CSR7 0x38 /* Interrupt enable */
 187 #define     CSR7_NI  0x00010000 /* Normal interrupt ena */
 188 #define     CSR7_AI  0x00008000 /* Abnormal int ena */
 189 #define     CSR7_TI  0x00000001 /* trans int ena */
 190 #define     CSR7_TU  0x00000004 /* trans buf unavail ena */
 191 #define     CSR7_RI  0x00000040 /* recv interp ena */
 192 #define     CSR7_GPT 0x00000800 /* gen purpose timer ena */
 193 #define CSR9 0x48 /* Boot Rom, serial ROM, MII */
 194 #define     CSR9_SR  0x0800 /* serial ROM select */
 195 #define     CSR9_RD  0x4000 /* read */
 196 #define     CSR9_DO  0x0008 /* data out */
 197 #define     CSR9_DI  0x0004 /* data in */
 198 #define     CSR9_SRC 0x0002 /* serial clock */
 199 #define     CSR9_CS  0x0001 /* serial rom chip select */
 200 /* Send/Recv Descriptors */
 201
 202 #define DES0 0
 203 #define  DES0_OWN 0x80000000 /* descr ownership. 1=211140A */
 204 #define  DES0_FL  0x3FFF0000 /* frame length */
 205 #define   DES0_FL_SHIFT 16   /* shift to fix frame length */
 206 #define   DES0_ES 0x00008000 /* Error sum */
 207 #define   DES0_TO 0x00004000 /* Trans jabber timeout */
 208 #define   DES0_LO 0x00000800 /* Loss of carrier */
 209 #define   DES0_NC 0x00000400 /* no carrier */
 210 #define   DES0_LC 0x00000200 /* Late coll */
 211 #define   DES0_EC 0x00000100 /* Excessive coll */
 212 #define   DES0_UF 0x00000002 /* Underflow error */
 213 #define   DES0_RE 0x00000008 /* MII error */
 214 #define   DES0_FS 0x00000200 /* first descr */
 215 #define   DES0_LS 0x00000100 /* last descr */
 216 #define DES1 1
 217 #define  DES1_ER  0x02000000 /* end of ring */
 218 #define  DES1_SAC 0x01000000 /* 2nd address chained */
 219 #define  DES1_BS2 0x003FF800 /* 2nd buffer size */
 220 #define  DES1_BS2_SHFT 11    /* shift to obtain 2nd buffer size */
 221 #define  DES1_BS1 0x000007FF /* 1nd buffer size */
 222 #define  DES1_IC  0x80000000 /* Interrupt on completion 31 */
 223 #define  DES1_LS  0x40000000 /* Last Segment 30 */
 224 #define  DES1_FS  0x20000000 /* First Segment 29 */
 225 #define  DES1_FT1 0x10000000 /* Filtering type 28 */
 226 #define  DES1_SET 0x08000000 /* Setup frame 27 */
 227 #define  DES1_AC  0x04000000 /* Add CRC disable 26 */
 228 #define  DES1_DPD 0x00800000 /* Disabled padding 23 */
 229 #define  DES1_FT0 0x00400000 /* Filtering type 22 */
 230 #define DES2 2 /* 1st buffer addr */
 231 #define DES3 3 /* 2nd buffer addr */
 232
 233 #define DES_BUF1 DES2
 234 #define DES_BUF2 DES3
 235
 236 #endif /* Include Guard */