1 /* $NetBSD: mutex.h,v 1.20 2015/02/25 13:52:42 joerg Exp $ */
4 * Copyright (c) 2002, 2007 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe and Andrew Doran.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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36 * The ARM mutex implementation is troublesome, because pre-v6 ARM lacks a
37 * compare-and-swap operation. However, there aren't any MP pre-v6 ARM
38 * systems to speak of.
40 * ARMv6 and later, however, does have ldrex/strex, and can thus implement an
41 * MP-safe compare-and-swap.
43 * So, what we have done is implement simple mutexes using a compare-and-swap.
44 * We support pre-ARMv6 by implementing CAS as a restartable atomic sequence
45 * that is checked by the IRQ vector.
49 #ifndef __MUTEX_PRIVATE
55 #else /* __MUTEX_PRIVATE */
60 volatile uintptr_t mtxa_owner
; /* 0-3 */
65 * Since the low bit of mtxa_owner is used to flag this
66 * mutex as a spin mutex, we can't use the first byte
67 * or the last byte to store the ipl or lock values.
69 volatile uint8_t mtxs_dummy
;
70 ipl_cookie_t mtxs_ipl
;
71 __cpu_simple_lock_t mtxs_lock
;
72 volatile uint8_t mtxs_unused
;
77 #define mtx_owner u.mtxa_owner
78 #define mtx_ipl u.s.mtxs_ipl
79 #define mtx_lock u.s.mtxs_lock
82 #define __HAVE_MUTEX_STUBS 1
83 #define __HAVE_SPIN_MUTEX_STUBS 1
85 #define __HAVE_SIMPLE_MUTEXES 1
88 * MUTEX_{GIVE,RECEIVE}: no memory barrier is required in the UP case;
89 * we're synchronizing against interrupts, not multiple processors.
93 #define MUTEX_RECEIVE(mtx) __asm __volatile("dmb" ::: "memory")
95 #define MUTEX_RECEIVE(mtx) membar_consumer()
98 #define MUTEX_RECEIVE(mtx) /* nothing */
101 #ifdef MULTIPROCESSOR
103 #define MUTEX_GIVE(mtx) __asm __volatile("dsb" ::: "memory")
105 #define MUTEX_GIVE(mtx) membar_producer()
108 #define MUTEX_GIVE(mtx) /* nothing */
111 #define MUTEX_CAS(p, o, n) \
112 (atomic_cas_ulong((volatile unsigned long *)(p), (o), (n)) == (o))
113 #ifdef MULTIPROCESSOR
114 #define MUTEX_SMT_PAUSE() __asm __volatile("wfe")
115 #define MUTEX_SMT_WAKE() __asm __volatile("sev")
118 #endif /* __MUTEX_PRIVATE */
120 #endif /* _ARM_MUTEX_H_ */