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Going Insane
commitf0fbc2c1c6e87a7bccadff23052675a79cc13b2b
authormilesdig <mil@norb.it>
Sun, 21 May 2017 22:52:51 +0000 (21 23:52 +0100)
committermilesdig <mil@norb.it>
Sun, 21 May 2017 22:52:51 +0000 (21 23:52 +0100)
tree2d5632fdca764f6c748a2d8f848cdb7f06016340tree | snapshot (tar.gz zip)
parentf29ce181ca26e4fac22372359062776f5971d1cacommit | diff
Going Insane
47 files changed:
Homework_2/CompArch_HMW2_Y3839090.pdf [moved from Homework_2/report.pdf with 100% similarity] blob | blame | history
Project/ControlSignals.xlsx diff | blob | blame | history
Project/Machine_Code_Program.mc [new file with mode: 0644] blob
Project/NEW_instruction_set.ist [new file with mode: 0644] blob
Project/Project/ALU_param.vhi [new file with mode: 0644] blob
Project/Project/ClockDivider.vhd [new file with mode: 0644] blob
Project/Project/ClockDivider.vhi [new file with mode: 0644] blob
Project/Project/ClockDividerColors.wcfg [new file with mode: 0644] blob
Project/Project/ClockDividerTB.vhd [new file with mode: 0644] blob
Project/Project/ControlFSM.spl [new file with mode: 0644] blob
Project/Project/ControlFSM.sym [new file with mode: 0644] blob
Project/Project/ControlFSM.vhd diff | blob | blame | history
Project/Project/ControlFSM.vhi [new file with mode: 0644] blob
Project/Project/ControlUnit.vhd [new file with mode: 0644] blob
Project/Project/ControlUnit.vhi [new file with mode: 0644] blob
Project/Project/DataPath_C.vhi [new file with mode: 0644] blob
Project/Project/DataPath_C_TB_isim_beh1.wdb [new file with mode: 0644] blob
Project/Project/Decoder.vhd [new file with mode: 0644] blob
Project/Project/DecoderColor.wcfg [new file with mode: 0644] blob
Project/Project/Decoder_Block.vhi [new file with mode: 0644] blob
Project/Project/Decoder_TB.vhd [new file with mode: 0644] blob
Project/Project/Decoder_TB_isim_beh1.wdb [new file with mode: 0644] blob
Project/Project/DualPortMemory.vhd [new file with mode: 0644] blob
Project/Project/DualPortMemory.vhi [new file with mode: 0644] blob
Project/Project/DualPortMemoryTB.vhd [new file with mode: 0644] blob
Project/Project/MMU.vhd [new file with mode: 0644] blob
Project/Project/MMU.vhi [new file with mode: 0644] blob
Project/Project/MMUColors.wcfg [new file with mode: 0644] blob
Project/Project/MMU_TB.vhd [new file with mode: 0644] blob
Project/Project/OutputReg.vhd [new file with mode: 0644] blob
Project/Project/OutputReg.vhi [new file with mode: 0644] blob
Project/Project/OutputRegTB.vhd [new file with mode: 0644] blob
Project/Project/OutputRegTB_isim_beh1.wdb [new file with mode: 0644] blob
Project/Project/Proccessor.vhd diff | blob | blame | history
Project/Project/Processor.vhi [new file with mode: 0644] blob
Project/Project/ProcessorColors.wcfg [new file with mode: 0644] blob
Project/Project/ProcessorTB.vhd [new file with mode: 0644] blob
Project/Project/Project.xise diff | blob | blame | history
Project/Project/SeqencerColors.wcfg [new file with mode: 0644] blob
Project/Project/Sequencer.vhd diff | blob | blame | history
Project/Project/Sequencer.vhi [new file with mode: 0644] blob
Project/Project/SequencerTB.vhd diff | blob | blame | history
Project/Project/schem.xps [new file with mode: 0644] blob
Project/SequencerTestData.xlsx [deleted file] blob | blame | history
Project/TestData.xlsx [new file with mode: 0644] blob
Project/TestProgram.rtf [new file with mode: 0644] blob
Project/program.txt [new file with mode: 0644] blob
Computer Architectures project to design a 16/32 bit microprocessor in VHDL